SAM3S8/SD8 Software Package: libraries/libchip_sam3s/include/SAM3S8.h Source File

SAM3S8/SD8 Software Package 1.2

# SAM3S8.h

    00001 /* ---------------------------------------------------------------------------- */
    00002 /*                  Atmel Microcontroller Software Support                      */
    00003 /* ---------------------------------------------------------------------------- */
    00004 /* Copyright (c) 2011, Atmel Corporation                                        */
    00005 /*                                                                              */
    00006 /* All rights reserved.                                                         */
    00007 /*                                                                              */
    00008 /* Redistribution and use in source and binary forms, with or without           */
    00009 /* modification, are permitted provided that the following condition is met:    */
    00010 /*                                                                              */
    00011 /* - Redistributions of source code must retain the above copyright notice,     */
    00012 /* this list of conditions and the disclaimer below.                            */
    00013 /*                                                                              */
    00014 /* Atmel's name may not be used to endorse or promote products derived from     */
    00015 /* this software without specific prior written permission.                     */
    00016 /*                                                                              */
    00017 /* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
    00018 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
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    00020 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
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    00025 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
    00026 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
    00027 /* ---------------------------------------------------------------------------- */
    00028 /*                                                                              */
    00029 /* File Name    : SAM3S8.h */
    00030 /* Object       : SAM3S8 definitions */
    00031 /* Generated by : AT91 SW Application Group */
    00032 /* Generated on : 2011-04-19 */
    00033
    00034 #ifndef SAM3S8_H
    00035 #define SAM3S8_H
    00036
    00037 /** \addtogroup SAM3S8_definitions SAM3S8 definitions
    00038   This file defines all structures and symbols for SAM3S8:
    00039     - registers and bitfields
    00040     - peripheral base address
    00041     - peripheral ID
    00042     - PIO definitions
    00043 */
    00044 /*@{*/
    00045
    00046 #ifdef __cplusplus
    00047  extern "C" {
    00048 #endif
    00049
    00050 #ifndef __ASSEMBLY__
    00051 #include <stdint.h>
    00052 #ifndef __cplusplus
    00053 typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
    00054 #else
    00055 typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
    00056 #endif
    00057 typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
    00058 typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
    00059 #define CAST(type, value) ((type *)(value))
    00060 #define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
    00061 #else
    00062 #define CAST(type, value) (value)
    00063 #define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
    00064 #endif
    00065
    00066 /* ************************************************************************** */
    00067 /*   CMSIS DEFINITIONS FOR SAM3S8 */
    00068 /* ************************************************************************** */
    00069 /** \addtogroup SAM3S8_cmsis CMSIS Definitions */
    00070 /*@{*/
    00071
    00072 /**< Interrupt Number Definition */
    00073 typedef enum IRQn
    00074 {
    00075 /******  Cortex-M3 Processor Exceptions Numbers ******************************/
    00076   NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
    00077   MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
    00078   BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
    00079   UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
    00080   SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
    00081   DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
    00082   PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
    00083   SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
    00084 /******  SAM3S8 specific Interrupt Numbers *********************************/
    00085
    00086   SUPC_IRQn            =  0, /**<  0 SAM3S8 Supply Controller (SUPC) */
    00087   RSTC_IRQn            =  1, /**<  1 SAM3S8 Reset Controller (RSTC) */
    00088   RTC_IRQn             =  2, /**<  2 SAM3S8 Real Time Clock (RTC) */
    00089   RTT_IRQn             =  3, /**<  3 SAM3S8 Real Time Timer (RTT) */
    00090   WDT_IRQn             =  4, /**<  4 SAM3S8 Watchdog Timer (WDT) */
    00091   PMC_IRQn             =  5, /**<  5 SAM3S8 Power Management Controller (PMC) */
    00092   EFC_IRQn             =  6, /**<  6 SAM3S8 Enhanced Embedded Flash Controller (EFC) */
    00093   UART0_IRQn           =  8, /**<  8 SAM3S8 UART 0 (UART0) */
    00094   UART1_IRQn           =  9, /**<  9 SAM3S8 UART 1 (UART1) */
    00095   SMC_IRQn             = 10, /**< 10 SAM3S8 Static Memory Controller (SMC) */
    00096   PIOA_IRQn            = 11, /**< 11 SAM3S8 Parallel I/O Controller A (PIOA) */
    00097   PIOB_IRQn            = 12, /**< 12 SAM3S8 Parallel I/O Controller B (PIOB) */
    00098   PIOC_IRQn            = 13, /**< 13 SAM3S8 Parallel I/O Controller C (PIOC) */
    00099   USART0_IRQn          = 14, /**< 14 SAM3S8 USART 0 (USART0) */
    00100   USART1_IRQn          = 15, /**< 15 SAM3S8 USART 1 (USART1) */
    00101   USART2_IRQn          = 16, /**< 16 SAM3S8 USART 2 (SAM3SD8 100 pins only) (USART2) */
    00102   HSMCI_IRQn           = 18, /**< 18 SAM3S8 Multimedia Card Interface (HSMCI) */
    00103   TWI0_IRQn            = 19, /**< 19 SAM3S8 Two Wire Interface 0 (TWI0) */
    00104   TWI1_IRQn            = 20, /**< 20 SAM3S8 Two Wire Interface 1 (TWI1) */
    00105   SPI_IRQn             = 21, /**< 21 SAM3S8 Serial Peripheral Interface (SPI) */
    00106   SSC_IRQn             = 22, /**< 22 SAM3S8 Synchronous Serial Controler (SSC) */
    00107   TC0_IRQn             = 23, /**< 23 SAM3S8 Timer/Counter 0 (TC0) */
    00108   TC1_IRQn             = 24, /**< 24 SAM3S8 Timer/Counter 1 (TC1) */
    00109   TC2_IRQn             = 25, /**< 25 SAM3S8 Timer/Counter 2 (TC2) */
    00110   TC3_IRQn             = 26, /**< 26 SAM3S8 Timer/Counter 3 (TC3) */
    00111   TC4_IRQn             = 27, /**< 27 SAM3S8 Timer/Counter 4 (TC4) */
    00112   TC5_IRQn             = 28, /**< 28 SAM3S8 Timer/Counter 5 (TC5) */
    00113   ADC_IRQn             = 29, /**< 29 SAM3S8 Analog To Digital Converter (ADC) */
    00114   DACC_IRQn            = 30, /**< 30 SAM3S8 Digital To Analog Converter (DACC) */
    00115   PWM_IRQn             = 31, /**< 31 SAM3S8 Pulse Width Modulation (PWM) */
    00116   CRCCU_IRQn           = 32, /**< 32 SAM3S8 CRC Calculation Unit (CRCCU) */
    00117   ACC_IRQn             = 33, /**< 33 SAM3S8 Analog Comparator (ACC) */
    00118   UDP_IRQn             = 34  /**< 34 SAM3S8 USB Device Port (UDP) */
    00119 } IRQn_Type;
    00120
    00121 /**
    00122  * \brief Configuration of the Cortex-M3 Processor and Core Peripherals
    00123  */
    00124
    00125 #define __MPU_PRESENT          1 /**< SAM3S8 does provide a MPU */
    00126 #define __NVIC_PRIO_BITS       4 /**< SAM3S8 uses 4 Bits for the Priority Levels */
    00127 #define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
    00128
    00129 /*
    00130  * \brief CMSIS includes
    00131  */
    00132 #if ( (defined (__ICCARM__)) && (__VER__ >= 6020000) )
    00133 /* Use CMSIS in EWARM if the version is 6.20.0 or later */
    00134 #include <core_cm3.h>
    00135 #else
    00136 /* Use CMSIS in software package */
    00137 #include "cmsis/core_cm3.h"
    00138 #endif
    00139
    00140 /*@}*/
    00141
    00142 /* ************************************************************************** */
    00143 /**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3S8 */
    00144 /* ************************************************************************** */
    00145 /** \addtogroup SAM3S8_api Peripheral Software API */
    00146 /*@{*/
    00147 /* ============================================================================= */
    00148 /**  SOFTWARE API DEFINITION FOR Analog Comparator Controller */
    00149 /* ============================================================================= */
    00150 /** \addtogroup SAM3S8_ACC Analog Comparator Controller */
    00151 /*@{*/
    00152
    00153 #ifndef __ASSEMBLY__
    00154 /** \brief Acc hardware registers */
    00155 typedef struct {
    00156   WoReg ACC_CR;        /**< \brief (Acc Offset: 0x00) Control Register */
    00157   RwReg ACC_MR;        /**< \brief (Acc Offset: 0x04) Mode Register */
    00158   RoReg Reserved1[7];
    00159   WoReg ACC_IER;       /**< \brief (Acc Offset: 0x24) Interrupt Enable Register */
    00160   WoReg ACC_IDR;       /**< \brief (Acc Offset: 0x28) Interrupt Disable Register */
    00161   RoReg ACC_IMR;       /**< \brief (Acc Offset: 0x2C) Interrupt Mask Register */
    00162   RoReg ACC_ISR;       /**< \brief (Acc Offset: 0x30) Interrupt Status Register */
    00163   RoReg Reserved2[24];
    00164   RwReg ACC_ACR;       /**< \brief (Acc Offset: 0x94) Analog Control Register */
    00165   RoReg Reserved3[19];
    00166   RwReg ACC_WPMR;      /**< \brief (Acc Offset: 0xE4) Write Protect Mode Register */
    00167   RoReg ACC_WPSR;      /**< \brief (Acc Offset: 0xE8) Write Protect Status Register */
    00168 } Acc;
    00169 #endif /* __ASSEMBLY__ */
    00170 /* -------- ACC_CR : (ACC Offset: 0x00) Control Register -------- */
    00171 #define ACC_CR_SWRST (0x1u << 0) /**< \brief (ACC_CR) SoftWare ReSeT */
    00172 /* -------- ACC_MR : (ACC Offset: 0x04) Mode Register -------- */
    00173 #define ACC_MR_SELMINUS_Pos 0
    00174 #define ACC_MR_SELMINUS_Msk (0x7u << ACC_MR_SELMINUS_Pos) /**< \brief (ACC_MR) SELection for MINUS comparator input */
    00175 #define   ACC_MR_SELMINUS_TS (0x0u << 0) /**< \brief (ACC_MR) SelectTS */
    00176 #define   ACC_MR_SELMINUS_ADVREF (0x1u << 0) /**< \brief (ACC_MR) Select ADVREF */
    00177 #define   ACC_MR_SELMINUS_DAC0 (0x2u << 0) /**< \brief (ACC_MR) Select DAC0 */
    00178 #define   ACC_MR_SELMINUS_DAC1 (0x3u << 0) /**< \brief (ACC_MR) Select DAC1 */
    00179 #define   ACC_MR_SELMINUS_AD0 (0x4u << 0) /**< \brief (ACC_MR) Select AD0 */
    00180 #define   ACC_MR_SELMINUS_AD1 (0x5u << 0) /**< \brief (ACC_MR) Select AD1 */
    00181 #define   ACC_MR_SELMINUS_AD2 (0x6u << 0) /**< \brief (ACC_MR) Select AD2 */
    00182 #define   ACC_MR_SELMINUS_AD3 (0x7u << 0) /**< \brief (ACC_MR) Select AD3 */
    00183 #define ACC_MR_SELPLUS_Pos 4
    00184 #define ACC_MR_SELPLUS_Msk (0x7u << ACC_MR_SELPLUS_Pos) /**< \brief (ACC_MR) SELection for PLUS comparator input */
    00185 #define   ACC_MR_SELPLUS_AD0 (0x0u << 4) /**< \brief (ACC_MR) Select AD0 */
    00186 #define   ACC_MR_SELPLUS_AD1 (0x1u << 4) /**< \brief (ACC_MR) Select AD1 */
    00187 #define   ACC_MR_SELPLUS_AD2 (0x2u << 4) /**< \brief (ACC_MR) Select AD2 */
    00188 #define   ACC_MR_SELPLUS_AD3 (0x3u << 4) /**< \brief (ACC_MR) Select AD3 */
    00189 #define   ACC_MR_SELPLUS_AD4 (0x4u << 4) /**< \brief (ACC_MR) Select AD4 */
    00190 #define   ACC_MR_SELPLUS_AD5 (0x5u << 4) /**< \brief (ACC_MR) Select AD5 */
    00191 #define   ACC_MR_SELPLUS_AD6 (0x6u << 4) /**< \brief (ACC_MR) Select AD6 */
    00192 #define   ACC_MR_SELPLUS_AD7 (0x7u << 4) /**< \brief (ACC_MR) Select AD7 */
    00193 #define ACC_MR_ACEN (0x1u << 8) /**< \brief (ACC_MR) Analog Comparator ENable */
    00194 #define   ACC_MR_ACEN_DIS (0x0u << 8) /**< \brief (ACC_MR) Analog Comparator Disabled. */
    00195 #define   ACC_MR_ACEN_EN (0x1u << 8) /**< \brief (ACC_MR) Analog Comparator Enabled. */
    00196 #define ACC_MR_EDGETYP_Pos 9
    00197 #define ACC_MR_EDGETYP_Msk (0x3u << ACC_MR_EDGETYP_Pos) /**< \brief (ACC_MR) EDGE TYPe */
    00198 #define   ACC_MR_EDGETYP_RISING (0x0u << 9) /**< \brief (ACC_MR) only rising edge of comparator output */
    00199 #define   ACC_MR_EDGETYP_FALLING (0x1u << 9) /**< \brief (ACC_MR) falling edge of comparator output */
    00200 #define   ACC_MR_EDGETYP_ANY (0x2u << 9) /**< \brief (ACC_MR) any edge of comparator output */
    00201 #define ACC_MR_INV (0x1u << 12) /**< \brief (ACC_MR) INVert comparator output */
    00202 #define   ACC_MR_INV_DIS (0x0u << 12) /**< \brief (ACC_MR) Analog Comparator output is directly processed. */
    00203 #define   ACC_MR_INV_EN (0x1u << 12) /**< \brief (ACC_MR) Analog Comparator output is inverted prior to being processed. */
    00204 #define ACC_MR_SELFS (0x1u << 13) /**< \brief (ACC_MR) SELection of Fault Source */
    00205 #define   ACC_MR_SELFS_CF (0x0u << 13) /**< \brief (ACC_MR) the CF flag is used to drive the FAULT output. */
    00206 #define   ACC_MR_SELFS_OUTPUT (0x1u << 13) /**< \brief (ACC_MR) the output of the Analog Comparator flag is used to drive the FAULT output. */
    00207 #define ACC_MR_FE (0x1u << 14) /**< \brief (ACC_MR) Fault Enable */
    00208 #define   ACC_MR_FE_DIS (0x0u << 14) /**< \brief (ACC_MR) the FAULT output is tied to 0. */
    00209 #define   ACC_MR_FE_EN (0x1u << 14) /**< \brief (ACC_MR) the FAULT output is driven by the signal defined by SELFS. */
    00210 /* -------- ACC_IER : (ACC Offset: 0x24) Interrupt Enable Register -------- */
    00211 #define ACC_IER_CE (0x1u << 0) /**< \brief (ACC_IER) Comparison Edge */
    00212 /* -------- ACC_IDR : (ACC Offset: 0x28) Interrupt Disable Register -------- */
    00213 #define ACC_IDR_CE (0x1u << 0) /**< \brief (ACC_IDR) Comparison Edge */
    00214 /* -------- ACC_IMR : (ACC Offset: 0x2C) Interrupt Mask Register -------- */
    00215 #define ACC_IMR_CE (0x1u << 0) /**< \brief (ACC_IMR) Comparison Edge */
    00216 /* -------- ACC_ISR : (ACC Offset: 0x30) Interrupt Status Register -------- */
    00217 #define ACC_ISR_CE (0x1u << 0) /**< \brief (ACC_ISR) Comparison Edge */
    00218 #define ACC_ISR_SCO (0x1u << 1) /**< \brief (ACC_ISR) Synchronized Comparator Output */
    00219 #define ACC_ISR_MASK (0x1u << 31) /**< \brief (ACC_ISR)  */
    00220 /* -------- ACC_ACR : (ACC Offset: 0x94) Analog Control Register -------- */
    00221 #define ACC_ACR_ISEL (0x1u << 0) /**< \brief (ACC_ACR) Current SELection */
    00222 #define   ACC_ACR_ISEL_LOPW (0x0u << 0) /**< \brief (ACC_ACR) low power option. */
    00223 #define   ACC_ACR_ISEL_HISP (0x1u << 0) /**< \brief (ACC_ACR) high speed option. */
    00224 #define ACC_ACR_HYST_Pos 1
    00225 #define ACC_ACR_HYST_Msk (0x3u << ACC_ACR_HYST_Pos) /**< \brief (ACC_ACR) HYSTeresis selection */
    00226 #define ACC_ACR_HYST(value) ((ACC_ACR_HYST_Msk & ((value) << ACC_ACR_HYST_Pos)))
    00227 /* -------- ACC_WPMR : (ACC Offset: 0xE4) Write Protect Mode Register -------- */
    00228 #define ACC_WPMR_WPEN (0x1u << 0) /**< \brief (ACC_WPMR) Write Protect Enable */
    00229 #define ACC_WPMR_WPKEY_Pos 8
    00230 #define ACC_WPMR_WPKEY_Msk (0xffffffu << ACC_WPMR_WPKEY_Pos) /**< \brief (ACC_WPMR) Write Protect KEY */
    00231 #define ACC_WPMR_WPKEY(value) ((ACC_WPMR_WPKEY_Msk & ((value) << ACC_WPMR_WPKEY_Pos)))
    00232 /* -------- ACC_WPSR : (ACC Offset: 0xE8) Write Protect Status Register -------- */
    00233 #define ACC_WPSR_WPROTERR (0x1u << 0) /**< \brief (ACC_WPSR) Write PROTection ERRor */
    00234
    00235 /*@}*/
    00236
    00237 /* ============================================================================= */
    00238 /**  SOFTWARE API DEFINITION FOR Analog-to-digital Converter */
    00239 /* ============================================================================= */
    00240 /** \addtogroup SAM3S8_ADC Analog-to-digital Converter */
    00241 /*@{*/
    00242
    00243 #ifndef __ASSEMBLY__
    00244 /** \brief Adc hardware registers */
    00245 typedef struct {
    00246   WoReg ADC_CR;        /**< \brief (Adc Offset: 0x00) Control Register */
    00247   RwReg ADC_MR;        /**< \brief (Adc Offset: 0x04) Mode Register */
    00248   RwReg ADC_SEQR1;     /**< \brief (Adc Offset: 0x08) Channel Sequence Register 1 */
    00249   RwReg ADC_SEQR2;     /**< \brief (Adc Offset: 0x0C) Channel Sequence Register 2 */
    00250   WoReg ADC_CHER;      /**< \brief (Adc Offset: 0x10) Channel Enable Register */
    00251   WoReg ADC_CHDR;      /**< \brief (Adc Offset: 0x14) Channel Disable Register */
    00252   RoReg ADC_CHSR;      /**< \brief (Adc Offset: 0x18) Channel Status Register */
    00253   RoReg Reserved1[1];
    00254   RoReg ADC_LCDR;      /**< \brief (Adc Offset: 0x20) Last Converted Data Register */
    00255   WoReg ADC_IER;       /**< \brief (Adc Offset: 0x24) Interrupt Enable Register */
    00256   WoReg ADC_IDR;       /**< \brief (Adc Offset: 0x28) Interrupt Disable Register */
    00257   RoReg ADC_IMR;       /**< \brief (Adc Offset: 0x2C) Interrupt Mask Register */
    00258   RoReg ADC_ISR;       /**< \brief (Adc Offset: 0x30) Interrupt Status Register */
    00259   RoReg Reserved2[2];
    00260   RoReg ADC_OVER;      /**< \brief (Adc Offset: 0x3C) Overrun Status Register */
    00261   RwReg ADC_EMR;       /**< \brief (Adc Offset: 0x40) Extended Mode Register */
    00262   RwReg ADC_CWR;       /**< \brief (Adc Offset: 0x44) Compare Window Register */
    00263   RwReg ADC_CGR;       /**< \brief (Adc Offset: 0x48) Channel Gain Register */
    00264   RwReg ADC_COR;       /**< \brief (Adc Offset: 0x4C) Channel Offset Register */
    00265   RoReg ADC_CDR[15];   /**< \brief (Adc Offset: 0x50) Channel Data Register */
    00266   RoReg Reserved3[2];
    00267   RwReg ADC_ACR;       /**< \brief (Adc Offset: 0x94) Analog Control Register */
    00268   RoReg Reserved4[19];
    00269   RwReg ADC_WPMR;      /**< \brief (Adc Offset: 0xE4) Write Protect Mode Register */
    00270   RoReg ADC_WPSR;      /**< \brief (Adc Offset: 0xE8) Write Protect Status Register */
    00271   RoReg Reserved5[5];
    00272   RwReg ADC_RPR;       /**< \brief (Adc Offset: 0x100) Receive Pointer Register */
    00273   RwReg ADC_RCR;       /**< \brief (Adc Offset: 0x104) Receive Counter Register */
    00274   RwReg ADC_TPR;       /**< \brief (Adc Offset: 0x108) Transmit Pointer Register */
    00275   RwReg ADC_TCR;       /**< \brief (Adc Offset: 0x10C) Transmit Counter Register */
    00276   RwReg ADC_RNPR;      /**< \brief (Adc Offset: 0x110) Receive Next Pointer Register */
    00277   RwReg ADC_RNCR;      /**< \brief (Adc Offset: 0x114) Receive Next Counter Register */
    00278   RwReg ADC_TNPR;      /**< \brief (Adc Offset: 0x118) Transmit Next Pointer Register */
    00279   RwReg ADC_TNCR;      /**< \brief (Adc Offset: 0x11C) Transmit Next Counter Register */
    00280   WoReg ADC_PTCR;      /**< \brief (Adc Offset: 0x120) Transfer Control Register */
    00281   RoReg ADC_PTSR;      /**< \brief (Adc Offset: 0x124) Transfer Status Register */
    00282 } Adc;
    00283 #endif /* __ASSEMBLY__ */
    00284 /* -------- ADC_CR : (ADC Offset: 0x00) Control Register -------- */
    00285 #define ADC_CR_SWRST (0x1u << 0) /**< \brief (ADC_CR) Software Reset */
    00286 #define ADC_CR_START (0x1u << 1) /**< \brief (ADC_CR) Start Conversion */
    00287 #define ADC_CR_AUTOCAL (0x1u << 3) /**< \brief (ADC_CR) Automatic Calibration of ADC */
    00288 /* -------- ADC_MR : (ADC Offset: 0x04) Mode Register -------- */
    00289 #define ADC_MR_TRGEN (0x1u << 0) /**< \brief (ADC_MR) Trigger Enable */
    00290 #define   ADC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (ADC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. */
    00291 #define   ADC_MR_TRGEN_EN (0x1u << 0) /**< \brief (ADC_MR) Hardware trigger selected by TRGSEL field is enabled. */
    00292 #define ADC_MR_TRGSEL_Pos 1
    00293 #define ADC_MR_TRGSEL_Msk (0x7u << ADC_MR_TRGSEL_Pos) /**< \brief (ADC_MR) Trigger Selection */
    00294 #define   ADC_MR_TRGSEL_ADC_TRIG0 (0x0u << 1) /**< \brief (ADC_MR) External trigger */
    00295 #define   ADC_MR_TRGSEL_ADC_TRIG1 (0x1u << 1) /**< \brief (ADC_MR) TIO Output of the Timer Counter Channel 0 */
    00296 #define   ADC_MR_TRGSEL_ADC_TRIG2 (0x2u << 1) /**< \brief (ADC_MR) TIO Output of the Timer Counter Channel 1 */
    00297 #define   ADC_MR_TRGSEL_ADC_TRIG3 (0x3u << 1) /**< \brief (ADC_MR) TIO Output of the Timer Counter Channel 2 */
    00298 #define   ADC_MR_TRGSEL_ADC_TRIG4 (0x4u << 1) /**< \brief (ADC_MR) PWM Event Line 0 */
    00299 #define   ADC_MR_TRGSEL_ADC_TRIG5 (0x5u << 1) /**< \brief (ADC_MR) PWM Event Line 1 */
    00300 #define ADC_MR_LOWRES (0x1u << 4) /**< \brief (ADC_MR) Resolution */
    00301 #define   ADC_MR_LOWRES_BITS_12 (0x0u << 4) /**< \brief (ADC_MR) 12-bit resolution */
    00302 #define   ADC_MR_LOWRES_BITS_10 (0x1u << 4) /**< \brief (ADC_MR) 10-bit resolution */
    00303 #define ADC_MR_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode */
    00304 #define   ADC_MR_SLEEP_NORMAL (0x0u << 5) /**< \brief (ADC_MR) Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions */
    00305 #define   ADC_MR_SLEEP_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode: The ADC Core and reference voltage circuitry are OFF between conversions */
    00306 #define ADC_MR_FWUP (0x1u << 6) /**< \brief (ADC_MR) Fast Wake Up */
    00307 #define   ADC_MR_FWUP_OFF (0x0u << 6) /**< \brief (ADC_MR) Normal Sleep Mode: The sleep mode is defined by the SLEEP bit */
    00308 #define   ADC_MR_FWUP_ON (0x1u << 6) /**< \brief (ADC_MR) Fast Wake Up Sleep Mode: The Voltage reference is ON between conversions and ADC Core is OFF */
    00309 #define ADC_MR_FREERUN (0x1u << 7) /**< \brief (ADC_MR) Free Run Mode */
    00310 #define   ADC_MR_FREERUN_OFF (0x0u << 7) /**< \brief (ADC_MR) Normal Mode */
    00311 #define   ADC_MR_FREERUN_ON (0x1u << 7) /**< \brief (ADC_MR) Free Run Mode: Never wait for any trigger. */
    00312 #define ADC_MR_PRESCAL_Pos 8
    00313 #define ADC_MR_PRESCAL_Msk (0xffu << ADC_MR_PRESCAL_Pos) /**< \brief (ADC_MR) Prescaler Rate Selection */
    00314 #define ADC_MR_PRESCAL(value) ((ADC_MR_PRESCAL_Msk & ((value) << ADC_MR_PRESCAL_Pos)))
    00315 #define ADC_MR_STARTUP_Pos 16
    00316 #define ADC_MR_STARTUP_Msk (0xfu << ADC_MR_STARTUP_Pos) /**< \brief (ADC_MR) Start Up Time */
    00317 #define   ADC_MR_STARTUP_SUT0 (0x0u << 16) /**< \brief (ADC_MR) 0 periods of ADCClock */
    00318 #define   ADC_MR_STARTUP_SUT8 (0x1u << 16) /**< \brief (ADC_MR) 8 periods of ADCClock */
    00319 #define   ADC_MR_STARTUP_SUT16 (0x2u << 16) /**< \brief (ADC_MR) 16 periods of ADCClock */
    00320 #define   ADC_MR_STARTUP_SUT24 (0x3u << 16) /**< \brief (ADC_MR) 24 periods of ADCClock */
    00321 #define   ADC_MR_STARTUP_SUT64 (0x4u << 16) /**< \brief (ADC_MR) 64 periods of ADCClock */
    00322 #define   ADC_MR_STARTUP_SUT80 (0x5u << 16) /**< \brief (ADC_MR) 80 periods of ADCClock */
    00323 #define   ADC_MR_STARTUP_SUT96 (0x6u << 16) /**< \brief (ADC_MR) 96 periods of ADCClock */
    00324 #define   ADC_MR_STARTUP_SUT112 (0x7u << 16) /**< \brief (ADC_MR) 112 periods of ADCClock */
    00325 #define   ADC_MR_STARTUP_SUT512 (0x8u << 16) /**< \brief (ADC_MR) 512 periods of ADCClock */
    00326 #define   ADC_MR_STARTUP_SUT576 (0x9u << 16) /**< \brief (ADC_MR) 576 periods of ADCClock */
    00327 #define   ADC_MR_STARTUP_SUT640 (0xAu << 16) /**< \brief (ADC_MR) 640 periods of ADCClock */
    00328 #define   ADC_MR_STARTUP_SUT704 (0xBu << 16) /**< \brief (ADC_MR) 704 periods of ADCClock */
    00329 #define   ADC_MR_STARTUP_SUT768 (0xCu << 16) /**< \brief (ADC_MR) 768 periods of ADCClock */
    00330 #define   ADC_MR_STARTUP_SUT832 (0xDu << 16) /**< \brief (ADC_MR) 832 periods of ADCClock */
    00331 #define   ADC_MR_STARTUP_SUT896 (0xEu << 16) /**< \brief (ADC_MR) 896 periods of ADCClock */
    00332 #define   ADC_MR_STARTUP_SUT960 (0xFu << 16) /**< \brief (ADC_MR) 960 periods of ADCClock */
    00333 #define ADC_MR_SETTLING_Pos 20
    00334 #define ADC_MR_SETTLING_Msk (0x3u << ADC_MR_SETTLING_Pos) /**< \brief (ADC_MR) Analog Settling Time */
    00335 #define   ADC_MR_SETTLING_AST3 (0x0u << 20) /**< \brief (ADC_MR) 3 periods of ADCClock */
    00336 #define   ADC_MR_SETTLING_AST5 (0x1u << 20) /**< \brief (ADC_MR) 5 periods of ADCClock */
    00337 #define   ADC_MR_SETTLING_AST9 (0x2u << 20) /**< \brief (ADC_MR) 9 periods of ADCClock */
    00338 #define   ADC_MR_SETTLING_AST17 (0x3u << 20) /**< \brief (ADC_MR) 17 periods of ADCClock */
    00339 #define ADC_MR_ANACH (0x1u << 23) /**< \brief (ADC_MR) Analog Change */
    00340 #define   ADC_MR_ANACH_NONE (0x0u << 23) /**< \brief (ADC_MR) No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for all channels */
    00341 #define   ADC_MR_ANACH_ALLOWED (0x1u << 23) /**< \brief (ADC_MR) Allows different analog settings for each channel. See ADC_CGR and ADC_COR Registers */
    00342 #define ADC_MR_TRACKTIM_Pos 24
    00343 #define ADC_MR_TRACKTIM_Msk (0xfu << ADC_MR_TRACKTIM_Pos) /**< \brief (ADC_MR) Tracking Time */
    00344 #define ADC_MR_TRACKTIM(value) ((ADC_MR_TRACKTIM_Msk & ((value) << ADC_MR_TRACKTIM_Pos)))
    00345 #define ADC_MR_TRANSFER_Pos 28
    00346 #define ADC_MR_TRANSFER_Msk (0x3u << ADC_MR_TRANSFER_Pos) /**< \brief (ADC_MR) Transfer Period */
    00347 #define ADC_MR_TRANSFER(value) ((ADC_MR_TRANSFER_Msk & ((value) << ADC_MR_TRANSFER_Pos)))
    00348 #define ADC_MR_USEQ (0x1u << 31) /**< \brief (ADC_MR) Use Sequence Enable */
    00349 #define   ADC_MR_USEQ_NUM_ORDER (0x0u << 31) /**< \brief (ADC_MR) Normal Mode: The controller converts channels in a simple numeric order. */
    00350 #define   ADC_MR_USEQ_REG_ORDER (0x1u << 31) /**< \brief (ADC_MR) User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers. */
    00351 /* -------- ADC_SEQR1 : (ADC Offset: 0x08) Channel Sequence Register 1 -------- */
    00352 #define ADC_SEQR1_USCH1_Pos 0
    00353 #define ADC_SEQR1_USCH1_Msk (0x7u << ADC_SEQR1_USCH1_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 1 */
    00354 #define ADC_SEQR1_USCH1(value) ((ADC_SEQR1_USCH1_Msk & ((value) << ADC_SEQR1_USCH1_Pos)))
    00355 #define ADC_SEQR1_USCH2_Pos 4
    00356 #define ADC_SEQR1_USCH2_Msk (0x7u << ADC_SEQR1_USCH2_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 2 */
    00357 #define ADC_SEQR1_USCH2(value) ((ADC_SEQR1_USCH2_Msk & ((value) << ADC_SEQR1_USCH2_Pos)))
    00358 #define ADC_SEQR1_USCH3_Pos 8
    00359 #define ADC_SEQR1_USCH3_Msk (0x7u << ADC_SEQR1_USCH3_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 3 */
    00360 #define ADC_SEQR1_USCH3(value) ((ADC_SEQR1_USCH3_Msk & ((value) << ADC_SEQR1_USCH3_Pos)))
    00361 #define ADC_SEQR1_USCH4_Pos 12
    00362 #define ADC_SEQR1_USCH4_Msk (0x7u << ADC_SEQR1_USCH4_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 4 */
    00363 #define ADC_SEQR1_USCH4(value) ((ADC_SEQR1_USCH4_Msk & ((value) << ADC_SEQR1_USCH4_Pos)))
    00364 #define ADC_SEQR1_USCH5_Pos 16
    00365 #define ADC_SEQR1_USCH5_Msk (0x7u << ADC_SEQR1_USCH5_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 5 */
    00366 #define ADC_SEQR1_USCH5(value) ((ADC_SEQR1_USCH5_Msk & ((value) << ADC_SEQR1_USCH5_Pos)))
    00367 #define ADC_SEQR1_USCH6_Pos 20
    00368 #define ADC_SEQR1_USCH6_Msk (0x7u << ADC_SEQR1_USCH6_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 6 */
    00369 #define ADC_SEQR1_USCH6(value) ((ADC_SEQR1_USCH6_Msk & ((value) << ADC_SEQR1_USCH6_Pos)))
    00370 #define ADC_SEQR1_USCH7_Pos 24
    00371 #define ADC_SEQR1_USCH7_Msk (0x7u << ADC_SEQR1_USCH7_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 7 */
    00372 #define ADC_SEQR1_USCH7(value) ((ADC_SEQR1_USCH7_Msk & ((value) << ADC_SEQR1_USCH7_Pos)))
    00373 #define ADC_SEQR1_USCH8_Pos 28
    00374 #define ADC_SEQR1_USCH8_Msk (0x7u << ADC_SEQR1_USCH8_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 8 */
    00375 #define ADC_SEQR1_USCH8(value) ((ADC_SEQR1_USCH8_Msk & ((value) << ADC_SEQR1_USCH8_Pos)))
    00376 /* -------- ADC_SEQR2 : (ADC Offset: 0x0C) Channel Sequence Register 2 -------- */
    00377 #define ADC_SEQR2_USCH9_Pos 0
    00378 #define ADC_SEQR2_USCH9_Msk (0x7u << ADC_SEQR2_USCH9_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 9 */
    00379 #define ADC_SEQR2_USCH9(value) ((ADC_SEQR2_USCH9_Msk & ((value) << ADC_SEQR2_USCH9_Pos)))
    00380 #define ADC_SEQR2_USCH10_Pos 4
    00381 #define ADC_SEQR2_USCH10_Msk (0x7u << ADC_SEQR2_USCH10_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 10 */
    00382 #define ADC_SEQR2_USCH10(value) ((ADC_SEQR2_USCH10_Msk & ((value) << ADC_SEQR2_USCH10_Pos)))
    00383 #define ADC_SEQR2_USCH11_Pos 8
    00384 #define ADC_SEQR2_USCH11_Msk (0x7u << ADC_SEQR2_USCH11_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 11 */
    00385 #define ADC_SEQR2_USCH11(value) ((ADC_SEQR2_USCH11_Msk & ((value) << ADC_SEQR2_USCH11_Pos)))
    00386 #define ADC_SEQR2_USCH12_Pos 12
    00387 #define ADC_SEQR2_USCH12_Msk (0x7u << ADC_SEQR2_USCH12_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 12 */
    00388 #define ADC_SEQR2_USCH12(value) ((ADC_SEQR2_USCH12_Msk & ((value) << ADC_SEQR2_USCH12_Pos)))
    00389 #define ADC_SEQR2_USCH13_Pos 16
    00390 #define ADC_SEQR2_USCH13_Msk (0x7u << ADC_SEQR2_USCH13_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 13 */
    00391 #define ADC_SEQR2_USCH13(value) ((ADC_SEQR2_USCH13_Msk & ((value) << ADC_SEQR2_USCH13_Pos)))
    00392 #define ADC_SEQR2_USCH14_Pos 20
    00393 #define ADC_SEQR2_USCH14_Msk (0x7u << ADC_SEQR2_USCH14_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 14 */
    00394 #define ADC_SEQR2_USCH14(value) ((ADC_SEQR2_USCH14_Msk & ((value) << ADC_SEQR2_USCH14_Pos)))
    00395 #define ADC_SEQR2_USCH15_Pos 24
    00396 #define ADC_SEQR2_USCH15_Msk (0x7u << ADC_SEQR2_USCH15_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 15 */
    00397 #define ADC_SEQR2_USCH15(value) ((ADC_SEQR2_USCH15_Msk & ((value) << ADC_SEQR2_USCH15_Pos)))
    00398 #define ADC_SEQR2_USCH16_Pos 28
    00399 #define ADC_SEQR2_USCH16_Msk (0x7u << ADC_SEQR2_USCH16_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 16 */
    00400 #define ADC_SEQR2_USCH16(value) ((ADC_SEQR2_USCH16_Msk & ((value) << ADC_SEQR2_USCH16_Pos)))
    00401 /* -------- ADC_CHER : (ADC Offset: 0x10) Channel Enable Register -------- */
    00402 #define ADC_CHER_CH0 (0x1u << 0) /**< \brief (ADC_CHER) Channel 0 Enable */
    00403 #define ADC_CHER_CH1 (0x1u << 1) /**< \brief (ADC_CHER) Channel 1 Enable */
    00404 #define ADC_CHER_CH2 (0x1u << 2) /**< \brief (ADC_CHER) Channel 2 Enable */
    00405 #define ADC_CHER_CH3 (0x1u << 3) /**< \brief (ADC_CHER) Channel 3 Enable */
    00406 #define ADC_CHER_CH4 (0x1u << 4) /**< \brief (ADC_CHER) Channel 4 Enable */
    00407 #define ADC_CHER_CH5 (0x1u << 5) /**< \brief (ADC_CHER) Channel 5 Enable */
    00408 #define ADC_CHER_CH6 (0x1u << 6) /**< \brief (ADC_CHER) Channel 6 Enable */
    00409 #define ADC_CHER_CH7 (0x1u << 7) /**< \brief (ADC_CHER) Channel 7 Enable */
    00410 #define ADC_CHER_CH8 (0x1u << 8) /**< \brief (ADC_CHER) Channel 8 Enable */
    00411 #define ADC_CHER_CH9 (0x1u << 9) /**< \brief (ADC_CHER) Channel 9 Enable */
    00412 #define ADC_CHER_CH10 (0x1u << 10) /**< \brief (ADC_CHER) Channel 10 Enable */
    00413 #define ADC_CHER_CH11 (0x1u << 11) /**< \brief (ADC_CHER) Channel 11 Enable */
    00414 #define ADC_CHER_CH12 (0x1u << 12) /**< \brief (ADC_CHER) Channel 12 Enable */
    00415 #define ADC_CHER_CH13 (0x1u << 13) /**< \brief (ADC_CHER) Channel 13 Enable */
    00416 #define ADC_CHER_CH14 (0x1u << 14) /**< \brief (ADC_CHER) Channel 14 Enable */
    00417 #define ADC_CHER_CH15 (0x1u << 15) /**< \brief (ADC_CHER) Channel 15 Enable */
    00418 /* -------- ADC_CHDR : (ADC Offset: 0x14) Channel Disable Register -------- */
    00419 #define ADC_CHDR_CH0 (0x1u << 0) /**< \brief (ADC_CHDR) Channel 0 Disable */
    00420 #define ADC_CHDR_CH1 (0x1u << 1) /**< \brief (ADC_CHDR) Channel 1 Disable */
    00421 #define ADC_CHDR_CH2 (0x1u << 2) /**< \brief (ADC_CHDR) Channel 2 Disable */
    00422 #define ADC_CHDR_CH3 (0x1u << 3) /**< \brief (ADC_CHDR) Channel 3 Disable */
    00423 #define ADC_CHDR_CH4 (0x1u << 4) /**< \brief (ADC_CHDR) Channel 4 Disable */
    00424 #define ADC_CHDR_CH5 (0x1u << 5) /**< \brief (ADC_CHDR) Channel 5 Disable */
    00425 #define ADC_CHDR_CH6 (0x1u << 6) /**< \brief (ADC_CHDR) Channel 6 Disable */
    00426 #define ADC_CHDR_CH7 (0x1u << 7) /**< \brief (ADC_CHDR) Channel 7 Disable */
    00427 #define ADC_CHDR_CH8 (0x1u << 8) /**< \brief (ADC_CHDR) Channel 8 Disable */
    00428 #define ADC_CHDR_CH9 (0x1u << 9) /**< \brief (ADC_CHDR) Channel 9 Disable */
    00429 #define ADC_CHDR_CH10 (0x1u << 10) /**< \brief (ADC_CHDR) Channel 10 Disable */
    00430 #define ADC_CHDR_CH11 (0x1u << 11) /**< \brief (ADC_CHDR) Channel 11 Disable */
    00431 #define ADC_CHDR_CH12 (0x1u << 12) /**< \brief (ADC_CHDR) Channel 12 Disable */
    00432 #define ADC_CHDR_CH13 (0x1u << 13) /**< \brief (ADC_CHDR) Channel 13 Disable */
    00433 #define ADC_CHDR_CH14 (0x1u << 14) /**< \brief (ADC_CHDR) Channel 14 Disable */
    00434 #define ADC_CHDR_CH15 (0x1u << 15) /**< \brief (ADC_CHDR) Channel 15 Disable */
    00435 /* -------- ADC_CHSR : (ADC Offset: 0x18) Channel Status Register -------- */
    00436 #define ADC_CHSR_CH0 (0x1u << 0) /**< \brief (ADC_CHSR) Channel 0 Status */
    00437 #define ADC_CHSR_CH1 (0x1u << 1) /**< \brief (ADC_CHSR) Channel 1 Status */
    00438 #define ADC_CHSR_CH2 (0x1u << 2) /**< \brief (ADC_CHSR) Channel 2 Status */
    00439 #define ADC_CHSR_CH3 (0x1u << 3) /**< \brief (ADC_CHSR) Channel 3 Status */
    00440 #define ADC_CHSR_CH4 (0x1u << 4) /**< \brief (ADC_CHSR) Channel 4 Status */
    00441 #define ADC_CHSR_CH5 (0x1u << 5) /**< \brief (ADC_CHSR) Channel 5 Status */
    00442 #define ADC_CHSR_CH6 (0x1u << 6) /**< \brief (ADC_CHSR) Channel 6 Status */
    00443 #define ADC_CHSR_CH7 (0x1u << 7) /**< \brief (ADC_CHSR) Channel 7 Status */
    00444 #define ADC_CHSR_CH8 (0x1u << 8) /**< \brief (ADC_CHSR) Channel 8 Status */
    00445 #define ADC_CHSR_CH9 (0x1u << 9) /**< \brief (ADC_CHSR) Channel 9 Status */
    00446 #define ADC_CHSR_CH10 (0x1u << 10) /**< \brief (ADC_CHSR) Channel 10 Status */
    00447 #define ADC_CHSR_CH11 (0x1u << 11) /**< \brief (ADC_CHSR) Channel 11 Status */
    00448 #define ADC_CHSR_CH12 (0x1u << 12) /**< \brief (ADC_CHSR) Channel 12 Status */
    00449 #define ADC_CHSR_CH13 (0x1u << 13) /**< \brief (ADC_CHSR) Channel 13 Status */
    00450 #define ADC_CHSR_CH14 (0x1u << 14) /**< \brief (ADC_CHSR) Channel 14 Status */
    00451 #define ADC_CHSR_CH15 (0x1u << 15) /**< \brief (ADC_CHSR) Channel 15 Status */
    00452 /* -------- ADC_LCDR : (ADC Offset: 0x20) Last Converted Data Register -------- */
    00453 #define ADC_LCDR_LDATA_Pos 0
    00454 #define ADC_LCDR_LDATA_Msk (0xfffu << ADC_LCDR_LDATA_Pos) /**< \brief (ADC_LCDR) Last Data Converted */
    00455 #define ADC_LCDR_CHNB_Pos 12
    00456 #define ADC_LCDR_CHNB_Msk (0xfu << ADC_LCDR_CHNB_Pos) /**< \brief (ADC_LCDR) Channel Number */
    00457 /* -------- ADC_IER : (ADC Offset: 0x24) Interrupt Enable Register -------- */
    00458 #define ADC_IER_EOC0 (0x1u << 0) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 0 */
    00459 #define ADC_IER_EOC1 (0x1u << 1) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 1 */
    00460 #define ADC_IER_EOC2 (0x1u << 2) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 2 */
    00461 #define ADC_IER_EOC3 (0x1u << 3) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 3 */
    00462 #define ADC_IER_EOC4 (0x1u << 4) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 4 */
    00463 #define ADC_IER_EOC5 (0x1u << 5) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 5 */
    00464 #define ADC_IER_EOC6 (0x1u << 6) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 6 */
    00465 #define ADC_IER_EOC7 (0x1u << 7) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 7 */
    00466 #define ADC_IER_EOC8 (0x1u << 8) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 8 */
    00467 #define ADC_IER_EOC9 (0x1u << 9) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 9 */
    00468 #define ADC_IER_EOC10 (0x1u << 10) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 10 */
    00469 #define ADC_IER_EOC11 (0x1u << 11) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 11 */
    00470 #define ADC_IER_EOC12 (0x1u << 12) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 12 */
    00471 #define ADC_IER_EOC13 (0x1u << 13) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 13 */
    00472 #define ADC_IER_EOC14 (0x1u << 14) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 14 */
    00473 #define ADC_IER_EOC15 (0x1u << 15) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 15 */
    00474 #define ADC_IER_EOCAL (0x1u << 23) /**< \brief (ADC_IER) End of Auto Calibration Interrupt Enable*/
    00475 #define ADC_IER_DRDY (0x1u << 24) /**< \brief (ADC_IER) Data Ready Interrupt Enable */
    00476 #define ADC_IER_GOVRE (0x1u << 25) /**< \brief (ADC_IER) General Overrun Error Interrupt Enable */
    00477 #define ADC_IER_COMPE (0x1u << 26) /**< \brief (ADC_IER) Comparison Event Interrupt Enable */
    00478 #define ADC_IER_ENDRX (0x1u << 27) /**< \brief (ADC_IER) End of Receive Buffer Interrupt Enable */
    00479 #define ADC_IER_RXBUFF (0x1u << 28) /**< \brief (ADC_IER) Receive Buffer Full Interrupt Enable */
    00480 /* -------- ADC_IDR : (ADC Offset: 0x28) Interrupt Disable Register -------- */
    00481 #define ADC_IDR_EOC0 (0x1u << 0) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 0 */
    00482 #define ADC_IDR_EOC1 (0x1u << 1) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 1 */
    00483 #define ADC_IDR_EOC2 (0x1u << 2) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 2 */
    00484 #define ADC_IDR_EOC3 (0x1u << 3) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 3 */
    00485 #define ADC_IDR_EOC4 (0x1u << 4) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 4 */
    00486 #define ADC_IDR_EOC5 (0x1u << 5) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 5 */
    00487 #define ADC_IDR_EOC6 (0x1u << 6) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 6 */
    00488 #define ADC_IDR_EOC7 (0x1u << 7) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 7 */
    00489 #define ADC_IDR_EOC8 (0x1u << 8) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 8 */
    00490 #define ADC_IDR_EOC9 (0x1u << 9) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 9 */
    00491 #define ADC_IDR_EOC10 (0x1u << 10) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 10 */
    00492 #define ADC_IDR_EOC11 (0x1u << 11) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 11 */
    00493 #define ADC_IDR_EOC12 (0x1u << 12) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 12 */
    00494 #define ADC_IDR_EOC13 (0x1u << 13) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 13 */
    00495 #define ADC_IDR_EOC14 (0x1u << 14) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 14 */
    00496 #define ADC_IDR_EOC15 (0x1u << 15) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 15 */
    00497 #define ADC_IDR_EOCAL (0x1u << 23) /**< \brief (ADC_IER) End of Auto Calibration Interrupt Disable*/
    00498 #define ADC_IDR_DRDY (0x1u << 24) /**< \brief (ADC_IDR) Data Ready Interrupt Disable */
    00499 #define ADC_IDR_GOVRE (0x1u << 25) /**< \brief (ADC_IDR) General Overrun Error Interrupt Disable */
    00500 #define ADC_IDR_COMPE (0x1u << 26) /**< \brief (ADC_IDR) Comparison Event Interrupt Disable */
    00501 #define ADC_IDR_ENDRX (0x1u << 27) /**< \brief (ADC_IDR) End of Receive Buffer Interrupt Disable */
    00502 #define ADC_IDR_RXBUFF (0x1u << 28) /**< \brief (ADC_IDR) Receive Buffer Full Interrupt Disable */
    00503 /* -------- ADC_IMR : (ADC Offset: 0x2C) Interrupt Mask Register -------- */
    00504 #define ADC_IMR_EOC0 (0x1u << 0) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 0 */
    00505 #define ADC_IMR_EOC1 (0x1u << 1) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 1 */
    00506 #define ADC_IMR_EOC2 (0x1u << 2) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 2 */
    00507 #define ADC_IMR_EOC3 (0x1u << 3) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 3 */
    00508 #define ADC_IMR_EOC4 (0x1u << 4) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 4 */
    00509 #define ADC_IMR_EOC5 (0x1u << 5) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 5 */
    00510 #define ADC_IMR_EOC6 (0x1u << 6) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 6 */
    00511 #define ADC_IMR_EOC7 (0x1u << 7) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 7 */
    00512 #define ADC_IMR_EOC8 (0x1u << 8) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 8 */
    00513 #define ADC_IMR_EOC9 (0x1u << 9) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 9 */
    00514 #define ADC_IMR_EOC10 (0x1u << 10) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 10 */
    00515 #define ADC_IMR_EOC11 (0x1u << 11) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 11 */
    00516 #define ADC_IMR_EOC12 (0x1u << 12) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 12 */
    00517 #define ADC_IMR_EOC13 (0x1u << 13) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 13 */
    00518 #define ADC_IMR_EOC14 (0x1u << 14) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 14 */
    00519 #define ADC_IMR_EOC15 (0x1u << 15) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 15 */
    00520 #define ADC_IMR_EOCAL (0x1u << 23) /**< \brief (ADC_IER) End of Auto Calibration Interrupt Mask*/
    00521 #define ADC_IMR_DRDY (0x1u << 24) /**< \brief (ADC_IMR) Data Ready Interrupt Mask */
    00522 #define ADC_IMR_GOVRE (0x1u << 25) /**< \brief (ADC_IMR) General Overrun Error Interrupt Mask */
    00523 #define ADC_IMR_COMPE (0x1u << 26) /**< \brief (ADC_IMR) Comparison Event Interrupt Mask */
    00524 #define ADC_IMR_ENDRX (0x1u << 27) /**< \brief (ADC_IMR) End of Receive Buffer Interrupt Mask */
    00525 #define ADC_IMR_RXBUFF (0x1u << 28) /**< \brief (ADC_IMR) Receive Buffer Full Interrupt Mask */
    00526 /* -------- ADC_ISR : (ADC Offset: 0x30) Interrupt Status Register -------- */
    00527 #define ADC_ISR_EOC0 (0x1u << 0) /**< \brief (ADC_ISR) End of Conversion 0 */
    00528 #define ADC_ISR_EOC1 (0x1u << 1) /**< \brief (ADC_ISR) End of Conversion 1 */
    00529 #define ADC_ISR_EOC2 (0x1u << 2) /**< \brief (ADC_ISR) End of Conversion 2 */
    00530 #define ADC_ISR_EOC3 (0x1u << 3) /**< \brief (ADC_ISR) End of Conversion 3 */
    00531 #define ADC_ISR_EOC4 (0x1u << 4) /**< \brief (ADC_ISR) End of Conversion 4 */
    00532 #define ADC_ISR_EOC5 (0x1u << 5) /**< \brief (ADC_ISR) End of Conversion 5 */
    00533 #define ADC_ISR_EOC6 (0x1u << 6) /**< \brief (ADC_ISR) End of Conversion 6 */
    00534 #define ADC_ISR_EOC7 (0x1u << 7) /**< \brief (ADC_ISR) End of Conversion 7 */
    00535 #define ADC_ISR_EOC8 (0x1u << 8) /**< \brief (ADC_ISR) End of Conversion 8 */
    00536 #define ADC_ISR_EOC9 (0x1u << 9) /**< \brief (ADC_ISR) End of Conversion 9 */
    00537 #define ADC_ISR_EOC10 (0x1u << 10) /**< \brief (ADC_ISR) End of Conversion 10 */
    00538 #define ADC_ISR_EOC11 (0x1u << 11) /**< \brief (ADC_ISR) End of Conversion 11 */
    00539 #define ADC_ISR_EOC12 (0x1u << 12) /**< \brief (ADC_ISR) End of Conversion 12 */
    00540 #define ADC_ISR_EOC13 (0x1u << 13) /**< \brief (ADC_ISR) End of Conversion 13 */
    00541 #define ADC_ISR_EOC14 (0x1u << 14) /**< \brief (ADC_ISR) End of Conversion 14 */
    00542 #define ADC_ISR_EOC15 (0x1u << 15) /**< \brief (ADC_ISR) End of Conversion 15 */
    00543 #define ADC_ISR_EOCAL (0x1u << 23) /**< \brief (ADC_ISR) End of Calibration Sequence */
    00544 #define ADC_ISR_DRDY (0x1u << 24) /**< \brief (ADC_ISR) Data Ready */
    00545 #define ADC_ISR_GOVRE (0x1u << 25) /**< \brief (ADC_ISR) General Overrun Error */
    00546 #define ADC_ISR_COMPE (0x1u << 26) /**< \brief (ADC_ISR) Comparison Error */
    00547 #define ADC_ISR_ENDRX (0x1u << 27) /**< \brief (ADC_ISR) End of RX Buffer */
    00548 #define ADC_ISR_RXBUFF (0x1u << 28) /**< \brief (ADC_ISR) RX Buffer Full */
    00549 /* -------- ADC_OVER : (ADC Offset: 0x3C) Overrun Status Register -------- */
    00550 #define ADC_OVER_OVRE0 (0x1u << 0) /**< \brief (ADC_OVER) Overrun Error 0 */
    00551 #define ADC_OVER_OVRE1 (0x1u << 1) /**< \brief (ADC_OVER) Overrun Error 1 */
    00552 #define ADC_OVER_OVRE2 (0x1u << 2) /**< \brief (ADC_OVER) Overrun Error 2 */
    00553 #define ADC_OVER_OVRE3 (0x1u << 3) /**< \brief (ADC_OVER) Overrun Error 3 */
    00554 #define ADC_OVER_OVRE4 (0x1u << 4) /**< \brief (ADC_OVER) Overrun Error 4 */
    00555 #define ADC_OVER_OVRE5 (0x1u << 5) /**< \brief (ADC_OVER) Overrun Error 5 */
    00556 #define ADC_OVER_OVRE6 (0x1u << 6) /**< \brief (ADC_OVER) Overrun Error 6 */
    00557 #define ADC_OVER_OVRE7 (0x1u << 7) /**< \brief (ADC_OVER) Overrun Error 7 */
    00558 #define ADC_OVER_OVRE8 (0x1u << 8) /**< \brief (ADC_OVER) Overrun Error 8 */
    00559 #define ADC_OVER_OVRE9 (0x1u << 9) /**< \brief (ADC_OVER) Overrun Error 9 */
    00560 #define ADC_OVER_OVRE10 (0x1u << 10) /**< \brief (ADC_OVER) Overrun Error 10 */
    00561 #define ADC_OVER_OVRE11 (0x1u << 11) /**< \brief (ADC_OVER) Overrun Error 11 */
    00562 #define ADC_OVER_OVRE12 (0x1u << 12) /**< \brief (ADC_OVER) Overrun Error 12 */
    00563 #define ADC_OVER_OVRE13 (0x1u << 13) /**< \brief (ADC_OVER) Overrun Error 13 */
    00564 #define ADC_OVER_OVRE14 (0x1u << 14) /**< \brief (ADC_OVER) Overrun Error 14 */
    00565 #define ADC_OVER_OVRE15 (0x1u << 15) /**< \brief (ADC_OVER) Overrun Error 15 */
    00566 /* -------- ADC_EMR : (ADC Offset: 0x40) Extended Mode Register -------- */
    00567 #define ADC_EMR_CMPMODE_Pos 0
    00568 #define ADC_EMR_CMPMODE_Msk (0x3u << ADC_EMR_CMPMODE_Pos) /**< \brief (ADC_EMR) Comparison Mode */
    00569 #define   ADC_EMR_CMPMODE_LOW (0x0u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is lower than the low threshold of the window. */
    00570 #define   ADC_EMR_CMPMODE_HIGH (0x1u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is higher than the high threshold of the window. */
    00571 #define   ADC_EMR_CMPMODE_IN (0x2u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is in the comparison window. */
    00572 #define   ADC_EMR_CMPMODE_OUT (0x3u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is out of the comparison window. */
    00573 #define ADC_EMR_CMPSEL_Pos 4
    00574 #define ADC_EMR_CMPSEL_Msk (0xfu << ADC_EMR_CMPSEL_Pos) /**< \brief (ADC_EMR) Comparison Selected Channel */
    00575 #define ADC_EMR_CMPSEL(value) ((ADC_EMR_CMPSEL_Msk & ((value) << ADC_EMR_CMPSEL_Pos)))
    00576 #define ADC_EMR_CMPALL (0x1u << 9) /**< \brief (ADC_EMR) Compare All Channels */
    00577 #define ADC_EMR_TAG (0x1u << 24) /**< \brief (ADC_EMR) TAG of ADC_LDCR register */
    00578 /* -------- ADC_CWR : (ADC Offset: 0x44) Compare Window Register -------- */
    00579 #define ADC_CWR_LOWTHRES_Pos 0
    00580 #define ADC_CWR_LOWTHRES_Msk (0xfffu << ADC_CWR_LOWTHRES_Pos) /**< \brief (ADC_CWR) Low Threshold */
    00581 #define ADC_CWR_LOWTHRES(value) ((ADC_CWR_LOWTHRES_Msk & ((value) << ADC_CWR_LOWTHRES_Pos)))
    00582 #define ADC_CWR_HIGHTHRES_Pos 16
    00583 #define ADC_CWR_HIGHTHRES_Msk (0xfffu << ADC_CWR_HIGHTHRES_Pos) /**< \brief (ADC_CWR) High Threshold */
    00584 #define ADC_CWR_HIGHTHRES(value) ((ADC_CWR_HIGHTHRES_Msk & ((value) << ADC_CWR_HIGHTHRES_Pos)))
    00585 /* -------- ADC_CGR : (ADC Offset: 0x48) Channel Gain Register -------- */
    00586 #define ADC_CGR_GAIN0_Pos 0
    00587 #define ADC_CGR_GAIN0_Msk (0x3u << ADC_CGR_GAIN0_Pos) /**< \brief (ADC_CGR) Gain for channel 0 */
    00588 #define ADC_CGR_GAIN0(value) ((ADC_CGR_GAIN0_Msk & ((value) << ADC_CGR_GAIN0_Pos)))
    00589 #define ADC_CGR_GAIN1_Pos 2
    00590 #define ADC_CGR_GAIN1_Msk (0x3u << ADC_CGR_GAIN1_Pos) /**< \brief (ADC_CGR) Gain for channel 1 */
    00591 #define ADC_CGR_GAIN1(value) ((ADC_CGR_GAIN1_Msk & ((value) << ADC_CGR_GAIN1_Pos)))
    00592 #define ADC_CGR_GAIN2_Pos 4
    00593 #define ADC_CGR_GAIN2_Msk (0x3u << ADC_CGR_GAIN2_Pos) /**< \brief (ADC_CGR) Gain for channel 2 */
    00594 #define ADC_CGR_GAIN2(value) ((ADC_CGR_GAIN2_Msk & ((value) << ADC_CGR_GAIN2_Pos)))
    00595 #define ADC_CGR_GAIN3_Pos 6
    00596 #define ADC_CGR_GAIN3_Msk (0x3u << ADC_CGR_GAIN3_Pos) /**< \brief (ADC_CGR) Gain for channel 3 */
    00597 #define ADC_CGR_GAIN3(value) ((ADC_CGR_GAIN3_Msk & ((value) << ADC_CGR_GAIN3_Pos)))
    00598 #define ADC_CGR_GAIN4_Pos 8
    00599 #define ADC_CGR_GAIN4_Msk (0x3u << ADC_CGR_GAIN4_Pos) /**< \brief (ADC_CGR) Gain for channel 4 */
    00600 #define ADC_CGR_GAIN4(value) ((ADC_CGR_GAIN4_Msk & ((value) << ADC_CGR_GAIN4_Pos)))
    00601 #define ADC_CGR_GAIN5_Pos 10
    00602 #define ADC_CGR_GAIN5_Msk (0x3u << ADC_CGR_GAIN5_Pos) /**< \brief (ADC_CGR) Gain for channel 5 */
    00603 #define ADC_CGR_GAIN5(value) ((ADC_CGR_GAIN5_Msk & ((value) << ADC_CGR_GAIN5_Pos)))
    00604 #define ADC_CGR_GAIN6_Pos 12
    00605 #define ADC_CGR_GAIN6_Msk (0x3u << ADC_CGR_GAIN6_Pos) /**< \brief (ADC_CGR) Gain for channel 6 */
    00606 #define ADC_CGR_GAIN6(value) ((ADC_CGR_GAIN6_Msk & ((value) << ADC_CGR_GAIN6_Pos)))
    00607 #define ADC_CGR_GAIN7_Pos 14
    00608 #define ADC_CGR_GAIN7_Msk (0x3u << ADC_CGR_GAIN7_Pos) /**< \brief (ADC_CGR) Gain for channel 7 */
    00609 #define ADC_CGR_GAIN7(value) ((ADC_CGR_GAIN7_Msk & ((value) << ADC_CGR_GAIN7_Pos)))
    00610 #define ADC_CGR_GAIN8_Pos 16
    00611 #define ADC_CGR_GAIN8_Msk (0x3u << ADC_CGR_GAIN8_Pos) /**< \brief (ADC_CGR) Gain for channel 8 */
    00612 #define ADC_CGR_GAIN8(value) ((ADC_CGR_GAIN8_Msk & ((value) << ADC_CGR_GAIN8_Pos)))
    00613 #define ADC_CGR_GAIN9_Pos 18
    00614 #define ADC_CGR_GAIN9_Msk (0x3u << ADC_CGR_GAIN9_Pos) /**< \brief (ADC_CGR) Gain for channel 9 */
    00615 #define ADC_CGR_GAIN9(value) ((ADC_CGR_GAIN9_Msk & ((value) << ADC_CGR_GAIN9_Pos)))
    00616 #define ADC_CGR_GAIN10_Pos 20
    00617 #define ADC_CGR_GAIN10_Msk (0x3u << ADC_CGR_GAIN10_Pos) /**< \brief (ADC_CGR) Gain for channel 10 */
    00618 #define ADC_CGR_GAIN10(value) ((ADC_CGR_GAIN10_Msk & ((value) << ADC_CGR_GAIN10_Pos)))
    00619 #define ADC_CGR_GAIN11_Pos 22
    00620 #define ADC_CGR_GAIN11_Msk (0x3u << ADC_CGR_GAIN11_Pos) /**< \brief (ADC_CGR) Gain for channel 11 */
    00621 #define ADC_CGR_GAIN11(value) ((ADC_CGR_GAIN11_Msk & ((value) << ADC_CGR_GAIN11_Pos)))
    00622 #define ADC_CGR_GAIN12_Pos 24
    00623 #define ADC_CGR_GAIN12_Msk (0x3u << ADC_CGR_GAIN12_Pos) /**< \brief (ADC_CGR) Gain for channel 12 */
    00624 #define ADC_CGR_GAIN12(value) ((ADC_CGR_GAIN12_Msk & ((value) << ADC_CGR_GAIN12_Pos)))
    00625 #define ADC_CGR_GAIN13_Pos 26
    00626 #define ADC_CGR_GAIN13_Msk (0x3u << ADC_CGR_GAIN13_Pos) /**< \brief (ADC_CGR) Gain for channel 13 */
    00627 #define ADC_CGR_GAIN13(value) ((ADC_CGR_GAIN13_Msk & ((value) << ADC_CGR_GAIN13_Pos)))
    00628 #define ADC_CGR_GAIN14_Pos 28
    00629 #define ADC_CGR_GAIN14_Msk (0x3u << ADC_CGR_GAIN14_Pos) /**< \brief (ADC_CGR) Gain for channel 14 */
    00630 #define ADC_CGR_GAIN14(value) ((ADC_CGR_GAIN14_Msk & ((value) << ADC_CGR_GAIN14_Pos)))
    00631 #define ADC_CGR_GAIN15_Pos 30
    00632 #define ADC_CGR_GAIN15_Msk (0x3u << ADC_CGR_GAIN15_Pos) /**< \brief (ADC_CGR) Gain for channel 15 */
    00633 #define ADC_CGR_GAIN15(value) ((ADC_CGR_GAIN15_Msk & ((value) << ADC_CGR_GAIN15_Pos)))
    00634 /* -------- ADC_COR : (ADC Offset: 0x4C) Channel Offset Register -------- */
    00635 #define ADC_COR_OFF0 (0x1u << 0) /**< \brief (ADC_COR) Offset for channel 0 */
    00636 #define ADC_COR_OFF1 (0x1u << 1) /**< \brief (ADC_COR) Offset for channel 1 */
    00637 #define ADC_COR_OFF2 (0x1u << 2) /**< \brief (ADC_COR) Offset for channel 2 */
    00638 #define ADC_COR_OFF3 (0x1u << 3) /**< \brief (ADC_COR) Offset for channel 3 */
    00639 #define ADC_COR_OFF4 (0x1u << 4) /**< \brief (ADC_COR) Offset for channel 4 */
    00640 #define ADC_COR_OFF5 (0x1u << 5) /**< \brief (ADC_COR) Offset for channel 5 */
    00641 #define ADC_COR_OFF6 (0x1u << 6) /**< \brief (ADC_COR) Offset for channel 6 */
    00642 #define ADC_COR_OFF7 (0x1u << 7) /**< \brief (ADC_COR) Offset for channel 7 */
    00643 #define ADC_COR_OFF8 (0x1u << 8) /**< \brief (ADC_COR) Offset for channel 8 */
    00644 #define ADC_COR_OFF9 (0x1u << 9) /**< \brief (ADC_COR) Offset for channel 9 */
    00645 #define ADC_COR_OFF10 (0x1u << 10) /**< \brief (ADC_COR) Offset for channel 10 */
    00646 #define ADC_COR_OFF11 (0x1u << 11) /**< \brief (ADC_COR) Offset for channel 11 */
    00647 #define ADC_COR_OFF12 (0x1u << 12) /**< \brief (ADC_COR) Offset for channel 12 */
    00648 #define ADC_COR_OFF13 (0x1u << 13) /**< \brief (ADC_COR) Offset for channel 13 */
    00649 #define ADC_COR_OFF14 (0x1u << 14) /**< \brief (ADC_COR) Offset for channel 14 */
    00650 #define ADC_COR_OFF15 (0x1u << 15) /**< \brief (ADC_COR) Offset for channel 15 */
    00651 #define ADC_COR_DIFF0 (0x1u << 16) /**< \brief (ADC_COR) Differential inputs for channel 0 */
    00652 #define ADC_COR_DIFF1 (0x1u << 17) /**< \brief (ADC_COR) Differential inputs for channel 1 */
    00653 #define ADC_COR_DIFF2 (0x1u << 18) /**< \brief (ADC_COR) Differential inputs for channel 2 */
    00654 #define ADC_COR_DIFF3 (0x1u << 19) /**< \brief (ADC_COR) Differential inputs for channel 3 */
    00655 #define ADC_COR_DIFF4 (0x1u << 20) /**< \brief (ADC_COR) Differential inputs for channel 4 */
    00656 #define ADC_COR_DIFF5 (0x1u << 21) /**< \brief (ADC_COR) Differential inputs for channel 5 */
    00657 #define ADC_COR_DIFF6 (0x1u << 22) /**< \brief (ADC_COR) Differential inputs for channel 6 */
    00658 #define ADC_COR_DIFF7 (0x1u << 23) /**< \brief (ADC_COR) Differential inputs for channel 7 */
    00659 #define ADC_COR_DIFF8 (0x1u << 24) /**< \brief (ADC_COR) Differential inputs for channel 8 */
    00660 #define ADC_COR_DIFF9 (0x1u << 25) /**< \brief (ADC_COR) Differential inputs for channel 9 */
    00661 #define ADC_COR_DIFF10 (0x1u << 26) /**< \brief (ADC_COR) Differential inputs for channel 10 */
    00662 #define ADC_COR_DIFF11 (0x1u << 27) /**< \brief (ADC_COR) Differential inputs for channel 11 */
    00663 #define ADC_COR_DIFF12 (0x1u << 28) /**< \brief (ADC_COR) Differential inputs for channel 12 */
    00664 #define ADC_COR_DIFF13 (0x1u << 29) /**< \brief (ADC_COR) Differential inputs for channel 13 */
    00665 #define ADC_COR_DIFF14 (0x1u << 30) /**< \brief (ADC_COR) Differential inputs for channel 14 */
    00666 #define ADC_COR_DIFF15 (0x1u << 31) /**< \brief (ADC_COR) Differential inputs for channel 15 */
    00667 /* -------- ADC_CDR[15] : (ADC Offset: 0x50) Channel Data Register -------- */
    00668 #define ADC_CDR_DATA_Pos 0
    00669 #define ADC_CDR_DATA_Msk (0xfffu << ADC_CDR_DATA_Pos) /**< \brief (ADC_CDR[15]) Converted Data */
    00670 /* -------- ADC_ACR : (ADC Offset: 0x94) Analog Control Register -------- */
    00671 #define ADC_ACR_TSON (0x1u << 4) /**< \brief (ADC_ACR) Temperature Sensor On */
    00672 #define ADC_ACR_IBCTL_Pos 8
    00673 #define ADC_ACR_IBCTL_Msk (0x3u << ADC_ACR_IBCTL_Pos) /**< \brief (ADC_ACR) ADC Bias Current Control */
    00674 #define ADC_ACR_IBCTL(value) ((ADC_ACR_IBCTL_Msk & ((value) << ADC_ACR_IBCTL_Pos)))
    00675 /* -------- ADC_WPMR : (ADC Offset: 0xE4) Write Protect Mode Register -------- */
    00676 #define ADC_WPMR_WPEN (0x1u << 0) /**< \brief (ADC_WPMR) Write Protect Enable */
    00677 #define ADC_WPMR_WPKEY_Pos 8
    00678 #define ADC_WPMR_WPKEY_Msk (0xffffffu << ADC_WPMR_WPKEY_Pos) /**< \brief (ADC_WPMR) Write Protect KEY */
    00679 #define ADC_WPMR_WPKEY(value) ((ADC_WPMR_WPKEY_Msk & ((value) << ADC_WPMR_WPKEY_Pos)))
    00680 /* -------- ADC_WPSR : (ADC Offset: 0xE8) Write Protect Status Register -------- */
    00681 #define ADC_WPSR_WPVS (0x1u << 0) /**< \brief (ADC_WPSR) Write Protect Violation Status */
    00682 #define ADC_WPSR_WPVSRC_Pos 8
    00683 #define ADC_WPSR_WPVSRC_Msk (0xffffu << ADC_WPSR_WPVSRC_Pos) /**< \brief (ADC_WPSR) Write Protect Violation Source */
    00684 /* -------- ADC_RPR : (ADC Offset: 0x100) Receive Pointer Register -------- */
    00685 #define ADC_RPR_RXPTR_Pos 0
    00686 #define ADC_RPR_RXPTR_Msk (0xffffffffu << ADC_RPR_RXPTR_Pos) /**< \brief (ADC_RPR) Receive Pointer Register */
    00687 #define ADC_RPR_RXPTR(value) ((ADC_RPR_RXPTR_Msk & ((value) << ADC_RPR_RXPTR_Pos)))
    00688 /* -------- ADC_RCR : (ADC Offset: 0x104) Receive Counter Register -------- */
    00689 #define ADC_RCR_RXCTR_Pos 0
    00690 #define ADC_RCR_RXCTR_Msk (0xffffu << ADC_RCR_RXCTR_Pos) /**< \brief (ADC_RCR) Receive Counter Register */
    00691 #define ADC_RCR_RXCTR(value) ((ADC_RCR_RXCTR_Msk & ((value) << ADC_RCR_RXCTR_Pos)))
    00692 /* -------- ADC_TPR : (ADC Offset: 0x108) Transmit Pointer Register -------- */
    00693 #define ADC_TPR_TXPTR_Pos 0
    00694 #define ADC_TPR_TXPTR_Msk (0xffffffffu << ADC_TPR_TXPTR_Pos) /**< \brief (ADC_TPR) Transmit Counter Register */
    00695 #define ADC_TPR_TXPTR(value) ((ADC_TPR_TXPTR_Msk & ((value) << ADC_TPR_TXPTR_Pos)))
    00696 /* -------- ADC_TCR : (ADC Offset: 0x10C) Transmit Counter Register -------- */
    00697 #define ADC_TCR_TXCTR_Pos 0
    00698 #define ADC_TCR_TXCTR_Msk (0xffffu << ADC_TCR_TXCTR_Pos) /**< \brief (ADC_TCR) Transmit Counter Register */
    00699 #define ADC_TCR_TXCTR(value) ((ADC_TCR_TXCTR_Msk & ((value) << ADC_TCR_TXCTR_Pos)))
    00700 /* -------- ADC_RNPR : (ADC Offset: 0x110) Receive Next Pointer Register -------- */
    00701 #define ADC_RNPR_RXNPTR_Pos 0
    00702 #define ADC_RNPR_RXNPTR_Msk (0xffffffffu << ADC_RNPR_RXNPTR_Pos) /**< \brief (ADC_RNPR) Receive Next Pointer */
    00703 #define ADC_RNPR_RXNPTR(value) ((ADC_RNPR_RXNPTR_Msk & ((value) << ADC_RNPR_RXNPTR_Pos)))
    00704 /* -------- ADC_RNCR : (ADC Offset: 0x114) Receive Next Counter Register -------- */
    00705 #define ADC_RNCR_RXNCTR_Pos 0
    00706 #define ADC_RNCR_RXNCTR_Msk (0xffffu << ADC_RNCR_RXNCTR_Pos) /**< \brief (ADC_RNCR) Receive Next Counter */
    00707 #define ADC_RNCR_RXNCTR(value) ((ADC_RNCR_RXNCTR_Msk & ((value) << ADC_RNCR_RXNCTR_Pos)))
    00708 /* -------- ADC_TNPR : (ADC Offset: 0x118) Transmit Next Pointer Register -------- */
    00709 #define ADC_TNPR_TXNPTR_Pos 0
    00710 #define ADC_TNPR_TXNPTR_Msk (0xffffffffu << ADC_TNPR_TXNPTR_Pos) /**< \brief (ADC_TNPR) Transmit Next Pointer */
    00711 #define ADC_TNPR_TXNPTR(value) ((ADC_TNPR_TXNPTR_Msk & ((value) << ADC_TNPR_TXNPTR_Pos)))
    00712 /* -------- ADC_TNCR : (ADC Offset: 0x11C) Transmit Next Counter Register -------- */
    00713 #define ADC_TNCR_TXNCTR_Pos 0
    00714 #define ADC_TNCR_TXNCTR_Msk (0xffffu << ADC_TNCR_TXNCTR_Pos) /**< \brief (ADC_TNCR) Transmit Counter Next */
    00715 #define ADC_TNCR_TXNCTR(value) ((ADC_TNCR_TXNCTR_Msk & ((value) << ADC_TNCR_TXNCTR_Pos)))
    00716 /* -------- ADC_PTCR : (ADC Offset: 0x120) Transfer Control Register -------- */
    00717 #define ADC_PTCR_RXTEN (0x1u << 0) /**< \brief (ADC_PTCR) Receiver Transfer Enable */
    00718 #define ADC_PTCR_RXTDIS (0x1u << 1) /**< \brief (ADC_PTCR) Receiver Transfer Disable */
    00719 #define ADC_PTCR_TXTEN (0x1u << 8) /**< \brief (ADC_PTCR) Transmitter Transfer Enable */
    00720 #define ADC_PTCR_TXTDIS (0x1u << 9) /**< \brief (ADC_PTCR) Transmitter Transfer Disable */
    00721 /* -------- ADC_PTSR : (ADC Offset: 0x124) Transfer Status Register -------- */
    00722 #define ADC_PTSR_RXTEN (0x1u << 0) /**< \brief (ADC_PTSR) Receiver Transfer Enable */
    00723 #define ADC_PTSR_TXTEN (0x1u << 8) /**< \brief (ADC_PTSR) Transmitter Transfer Enable */
    00724
    00725 /*@}*/
    00726
    00727 /* ============================================================================= */
    00728 /**  SOFTWARE API DEFINITION FOR Chip Identifier */
    00729 /* ============================================================================= */
    00730 /** \addtogroup SAM3S8_CHIPID Chip Identifier */
    00731 /*@{*/
    00732
    00733 #ifndef __ASSEMBLY__
    00734 /** \brief Chipid hardware registers */
    00735 typedef struct {
    00736   RoReg CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */
    00737   RoReg CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */
    00738 } Chipid;
    00739 #endif /* __ASSEMBLY__ */
    00740 /* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */
    00741 #define CHIPID_CIDR_VERSION_Pos 0
    00742 #define CHIPID_CIDR_VERSION_Msk (0x1fu << CHIPID_CIDR_VERSION_Pos) /**< \brief (CHIPID_CIDR) Version of the Device */
    00743 #define CHIPID_CIDR_EPROC_Pos 5
    00744 #define CHIPID_CIDR_EPROC_Msk (0x7u << CHIPID_CIDR_EPROC_Pos) /**< \brief (CHIPID_CIDR) Embedded Processor */
    00745 #define   CHIPID_CIDR_EPROC_ARM946ES (0x1u << 5) /**< \brief (CHIPID_CIDR) ARM946ES */
    00746 #define   CHIPID_CIDR_EPROC_ARM7TDMI (0x2u << 5) /**< \brief (CHIPID_CIDR) ARM7TDMI */
    00747 #define   CHIPID_CIDR_EPROC_CM3 (0x3u << 5) /**< \brief (CHIPID_CIDR) Cortex-M3 */
    00748 #define   CHIPID_CIDR_EPROC_ARM920T (0x4u << 5) /**< \brief (CHIPID_CIDR) ARM920T */
    00749 #define   CHIPID_CIDR_EPROC_ARM926EJS (0x5u << 5) /**< \brief (CHIPID_CIDR) ARM926EJS */
    00750 #define   CHIPID_CIDR_EPROC_CA5 (0x6u << 5) /**< \brief (CHIPID_CIDR) Cortex-A5 */
    00751 #define   CHIPID_CIDR_EPROC_CM4 (0x7u << 5) /**< \brief (CHIPID_CIDR) Cortex-M4 */
    00752 #define CHIPID_CIDR_NVPSIZ_Pos 8
    00753 #define CHIPID_CIDR_NVPSIZ_Msk (0xfu << CHIPID_CIDR_NVPSIZ_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */
    00754 #define   CHIPID_CIDR_NVPSIZ_NONE (0x0u << 8) /**< \brief (CHIPID_CIDR) None */
    00755 #define   CHIPID_CIDR_NVPSIZ_8K (0x1u << 8) /**< \brief (CHIPID_CIDR) 8K bytes */
    00756 #define   CHIPID_CIDR_NVPSIZ_16K (0x2u << 8) /**< \brief (CHIPID_CIDR) 16K bytes */
    00757 #define   CHIPID_CIDR_NVPSIZ_32K (0x3u << 8) /**< \brief (CHIPID_CIDR) 32K bytes */
    00758 #define   CHIPID_CIDR_NVPSIZ_64K (0x5u << 8) /**< \brief (CHIPID_CIDR) 64K bytes */
    00759 #define   CHIPID_CIDR_NVPSIZ_128K (0x7u << 8) /**< \brief (CHIPID_CIDR) 128K bytes */
    00760 #define   CHIPID_CIDR_NVPSIZ_256K (0x9u << 8) /**< \brief (CHIPID_CIDR) 256K bytes */
    00761 #define   CHIPID_CIDR_NVPSIZ_512K (0xAu << 8) /**< \brief (CHIPID_CIDR) 512K bytes */
    00762 #define   CHIPID_CIDR_NVPSIZ_1024K (0xCu << 8) /**< \brief (CHIPID_CIDR) 1024K bytes */
    00763 #define   CHIPID_CIDR_NVPSIZ_2048K (0xEu << 8) /**< \brief (CHIPID_CIDR) 2048K bytes */
    00764 #define CHIPID_CIDR_NVPSIZ2_Pos 12
    00765 #define CHIPID_CIDR_NVPSIZ2_Msk (0xfu << CHIPID_CIDR_NVPSIZ2_Pos) /**< \brief (CHIPID_CIDR)  */
    00766 #define   CHIPID_CIDR_NVPSIZ2_NONE (0x0u << 12) /**< \brief (CHIPID_CIDR) None */
    00767 #define   CHIPID_CIDR_NVPSIZ2_8K (0x1u << 12) /**< \brief (CHIPID_CIDR) 8K bytes */
    00768 #define   CHIPID_CIDR_NVPSIZ2_16K (0x2u << 12) /**< \brief (CHIPID_CIDR) 16K bytes */
    00769 #define   CHIPID_CIDR_NVPSIZ2_32K (0x3u << 12) /**< \brief (CHIPID_CIDR) 32K bytes */
    00770 #define   CHIPID_CIDR_NVPSIZ2_64K (0x5u << 12) /**< \brief (CHIPID_CIDR) 64K bytes */
    00771 #define   CHIPID_CIDR_NVPSIZ2_128K (0x7u << 12) /**< \brief (CHIPID_CIDR) 128K bytes */
    00772 #define   CHIPID_CIDR_NVPSIZ2_256K (0x9u << 12) /**< \brief (CHIPID_CIDR) 256K bytes */
    00773 #define   CHIPID_CIDR_NVPSIZ2_512K (0xAu << 12) /**< \brief (CHIPID_CIDR) 512K bytes */
    00774 #define   CHIPID_CIDR_NVPSIZ2_1024K (0xCu << 12) /**< \brief (CHIPID_CIDR) 1024K bytes */
    00775 #define   CHIPID_CIDR_NVPSIZ2_2048K (0xEu << 12) /**< \brief (CHIPID_CIDR) 2048K bytes */
    00776 #define CHIPID_CIDR_SRAMSIZ_Pos 16
    00777 #define CHIPID_CIDR_SRAMSIZ_Msk (0xfu << CHIPID_CIDR_SRAMSIZ_Pos) /**< \brief (CHIPID_CIDR) Internal SRAM Size */
    00778 #define   CHIPID_CIDR_SRAMSIZ_48K (0x0u << 16) /**< \brief (CHIPID_CIDR) 48K bytes */
    00779 #define   CHIPID_CIDR_SRAMSIZ_1K (0x1u << 16) /**< \brief (CHIPID_CIDR) 1K bytes */
    00780 #define   CHIPID_CIDR_SRAMSIZ_2K (0x2u << 16) /**< \brief (CHIPID_CIDR) 2K bytes */
    00781 #define   CHIPID_CIDR_SRAMSIZ_6K (0x3u << 16) /**< \brief (CHIPID_CIDR) 6K bytes */
    00782 #define   CHIPID_CIDR_SRAMSIZ_24K (0x4u << 16) /**< \brief (CHIPID_CIDR) 24K bytes */
    00783 #define   CHIPID_CIDR_SRAMSIZ_4K (0x5u << 16) /**< \brief (CHIPID_CIDR) 4K bytes */
    00784 #define   CHIPID_CIDR_SRAMSIZ_80K (0x6u << 16) /**< \brief (CHIPID_CIDR) 80K bytes */
    00785 #define   CHIPID_CIDR_SRAMSIZ_160K (0x7u << 16) /**< \brief (CHIPID_CIDR) 160K bytes */
    00786 #define   CHIPID_CIDR_SRAMSIZ_8K (0x8u << 16) /**< \brief (CHIPID_CIDR) 8K bytes */
    00787 #define   CHIPID_CIDR_SRAMSIZ_16K (0x9u << 16) /**< \brief (CHIPID_CIDR) 16K bytes */
    00788 #define   CHIPID_CIDR_SRAMSIZ_32K (0xAu << 16) /**< \brief (CHIPID_CIDR) 32K bytes */
    00789 #define   CHIPID_CIDR_SRAMSIZ_64K (0xBu << 16) /**< \brief (CHIPID_CIDR) 64K bytes */
    00790 #define   CHIPID_CIDR_SRAMSIZ_128K (0xCu << 16) /**< \brief (CHIPID_CIDR) 128K bytes */
    00791 #define   CHIPID_CIDR_SRAMSIZ_256K (0xDu << 16) /**< \brief (CHIPID_CIDR) 256K bytes */
    00792 #define   CHIPID_CIDR_SRAMSIZ_96K (0xEu << 16) /**< \brief (CHIPID_CIDR) 96K bytes */
    00793 #define   CHIPID_CIDR_SRAMSIZ_512K (0xFu << 16) /**< \brief (CHIPID_CIDR) 512K bytes */
    00794 #define CHIPID_CIDR_ARCH_Pos 20
    00795 #define CHIPID_CIDR_ARCH_Msk (0xffu << CHIPID_CIDR_ARCH_Pos) /**< \brief (CHIPID_CIDR) Architecture Identifier */
    00796 #define   CHIPID_CIDR_ARCH_AT91SAM9xx (0x19u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9xx Series */
    00797 #define   CHIPID_CIDR_ARCH_AT91SAM9XExx (0x29u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9XExx Series */
    00798 #define   CHIPID_CIDR_ARCH_AT91x34 (0x34u << 20) /**< \brief (CHIPID_CIDR) AT91x34 Series */
    00799 #define   CHIPID_CIDR_ARCH_CAP7 (0x37u << 20) /**< \brief (CHIPID_CIDR) CAP7 Series */
    00800 #define   CHIPID_CIDR_ARCH_CAP9 (0x39u << 20) /**< \brief (CHIPID_CIDR) CAP9 Series */
    00801 #define   CHIPID_CIDR_ARCH_CAP11 (0x3Bu << 20) /**< \brief (CHIPID_CIDR) CAP11 Series */
    00802 #define   CHIPID_CIDR_ARCH_AT91x40 (0x40u << 20) /**< \brief (CHIPID_CIDR) AT91x40 Series */
    00803 #define   CHIPID_CIDR_ARCH_AT91x42 (0x42u << 20) /**< \brief (CHIPID_CIDR) AT91x42 Series */
    00804 #define   CHIPID_CIDR_ARCH_AT91x55 (0x55u << 20) /**< \brief (CHIPID_CIDR) AT91x55 Series */
    00805 #define   CHIPID_CIDR_ARCH_AT91SAM7Axx (0x60u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Axx Series */
    00806 #define   CHIPID_CIDR_ARCH_AT91SAM7AQxx (0x61u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7AQxx Series */
    00807 #define   CHIPID_CIDR_ARCH_AT91x63 (0x63u << 20) /**< \brief (CHIPID_CIDR) AT91x63 Series */
    00808 #define   CHIPID_CIDR_ARCH_AT91SAM7Sxx (0x70u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Sxx Series */
    00809 #define   CHIPID_CIDR_ARCH_AT91SAM7XCxx (0x71u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7XCxx Series */
    00810 #define   CHIPID_CIDR_ARCH_AT91SAM7SExx (0x72u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SExx Series */
    00811 #define   CHIPID_CIDR_ARCH_AT91SAM7Lxx (0x73u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Lxx Series */
    00812 #define   CHIPID_CIDR_ARCH_AT91SAM7Xxx (0x75u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Xxx Series */
    00813 #define   CHIPID_CIDR_ARCH_AT91SAM7SLxx (0x76u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SLxx Series */
    00814 #define   CHIPID_CIDR_ARCH_SAM3UxC (0x80u << 20) /**< \brief (CHIPID_CIDR) SAM3UxC Series (100-pin version) */
    00815 #define   CHIPID_CIDR_ARCH_SAM3UxE (0x81u << 20) /**< \brief (CHIPID_CIDR) SAM3UxE Series (144-pin version) */
    00816 #define   CHIPID_CIDR_ARCH_SAM3ASAM4AxC (0x83u << 20) /**< \brief (CHIPID_CIDR) SAM3AxC or SAM4AxC Series (100-pin version) */
    00817 #define   CHIPID_CIDR_ARCH_SAM3XSAM4XxC (0x84u << 20) /**< \brief (CHIPID_CIDR) SAM3XxCor SAM4XxC Series (100-pin version) */
    00818 #define   CHIPID_CIDR_ARCH_SAM3XSAM4XxE (0x85u << 20) /**< \brief (CHIPID_CIDR) SAM3XxEor SAM4XxE Series (144-pin version) */
    00819 #define   CHIPID_CIDR_ARCH_SAM3XSAM4XxG (0x86u << 20) /**< \brief (CHIPID_CIDR) SAM3XxGor or SAM4XxG Series  (208/217-pin version) */
    00820 #define   CHIPID_CIDR_ARCH_SAM3SSAM4SxA (0x88u << 20) /**< \brief (CHIPID_CIDR) SAM3SxA or SAM4SxA Series (48-pin version) */
    00821 #define   CHIPID_CIDR_ARCH_SAM3SSAM4SxB (0x89u << 20) /**< \brief (CHIPID_CIDR) SAM3SxBor SAM4SxB Series (64-pin version) */
    00822 #define   CHIPID_CIDR_ARCH_SAM3SSAM4SxC (0x8Au << 20) /**< \brief (CHIPID_CIDR) SAM3SxCor SAM4SxC Series (100-pin version) */
    00823 #define   CHIPID_CIDR_ARCH_AT91x92 (0x92u << 20) /**< \brief (CHIPID_CIDR) AT91x92 Series */
    00824 #define   CHIPID_CIDR_ARCH_SAM3NxA (0x93u << 20) /**< \brief (CHIPID_CIDR) SAM3NxA Series (48-pin version) */
    00825 #define   CHIPID_CIDR_ARCH_SAM3NxB (0x94u << 20) /**< \brief (CHIPID_CIDR) SAM3NxB Series (64-pin version) */
    00826 #define   CHIPID_CIDR_ARCH_SAM3NxC (0x95u << 20) /**< \brief (CHIPID_CIDR) SAM3NxC Series (100-pin version) */
    00827 #define   CHIPID_CIDR_ARCH_SAM3SDxB (0x99u << 20) /**< \brief (CHIPID_CIDR) SAM3SDxB Series (64-pin version) */
    00828 #define   CHIPID_CIDR_ARCH_SAM3SDxC (0x9Au << 20) /**< \brief (CHIPID_CIDR) SAM3SDxC Series (100-pin version) */
    00829 #define   CHIPID_CIDR_ARCH_SAM5A (0xA5u << 20) /**< \brief (CHIPID_CIDR) SAM5A */
    00830 #define   CHIPID_CIDR_ARCH_AT75Cxx (0xF0u << 20) /**< \brief (CHIPID_CIDR) AT75Cxx Series */
    00831 #define CHIPID_CIDR_NVPTYP_Pos 28
    00832 #define CHIPID_CIDR_NVPTYP_Msk (0x7u << CHIPID_CIDR_NVPTYP_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */
    00833 #define   CHIPID_CIDR_NVPTYP_ROM (0x0u << 28) /**< \brief (CHIPID_CIDR) ROM */
    00834 #define   CHIPID_CIDR_NVPTYP_ROMLESS (0x1u << 28) /**< \brief (CHIPID_CIDR) ROMless or on-chip Flash */
    00835 #define   CHIPID_CIDR_NVPTYP_FLASH (0x2u << 28) /**< \brief (CHIPID_CIDR) Embedded Flash Memory */
    00836 #define   CHIPID_CIDR_NVPTYP_ROM_FLASH (0x3u << 28) /**< \brief (CHIPID_CIDR) ROM and Embedded Flash MemoryNVPSIZ is ROM size      NVPSIZ2 is Flash size */
    00837 #define   CHIPID_CIDR_NVPTYP_SRAM (0x4u << 28) /**< \brief (CHIPID_CIDR) SRAM emulating ROM */
    00838 #define CHIPID_CIDR_EXT (0x1u << 31) /**< \brief (CHIPID_CIDR) Extension Flag */
    00839 /* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */
    00840 #define CHIPID_EXID_EXID_Pos 0
    00841 #define CHIPID_EXID_EXID_Msk (0xffffffffu << CHIPID_EXID_EXID_Pos) /**< \brief (CHIPID_EXID) Chip ID Extension */
    00842
    00843 /*@}*/
    00844
    00845 /* ============================================================================= */
    00846 /**  SOFTWARE API DEFINITION FOR Cyclic Redundancy Check Calculation Unit */
    00847 /* ============================================================================= */
    00848 /** \addtogroup SAM3S8_CRCCU Cyclic Redundancy Check Calculation Unit */
    00849 /*@{*/
    00850
    00851 #ifndef __ASSEMBLY__
    00852 /** \brief Crccu hardware registers */
    00853 typedef struct {
    00854   RwReg CRCCU_DSCR;    /**< \brief (Crccu Offset: 0x00000000) CRCCU Descriptor Base Register */
    00855   RoReg Reserved1[1];
    00856   WoReg CRCCU_DMA_EN;  /**< \brief (Crccu Offset: 0x00000008) CRCCU DMA Enable Register */
    00857   WoReg CRCCU_DMA_DIS; /**< \brief (Crccu Offset: 0x0000000C) CRCCU DMA Disable Register */
    00858   RoReg CRCCU_DMA_SR;  /**< \brief (Crccu Offset: 0x00000010) CRCCU DMA Status Register */
    00859   WoReg CRCCU_DMA_IER; /**< \brief (Crccu Offset: 0x00000014) CRCCU DMA Interrupt Enable Register */
    00860   WoReg CRCCU_DMA_IDR; /**< \brief (Crccu Offset: 0x00000018) CRCCU DMA Interrupt Disable Register */
    00861   RoReg CRCCU_DMA_IMR; /**< \brief (Crccu Offset: 0x0000001C) CRCCU DMA Interrupt Mask Register */
    00862   RoReg CRCCU_DMA_ISR; /**< \brief (Crccu Offset: 0x00000020) CRCCU DMA Interrupt Status Register */
    00863   RoReg Reserved2[4];
    00864   WoReg CRCCU_CR;      /**< \brief (Crccu Offset: 0x00000034) CRCCU Control Register */
    00865   RwReg CRCCU_MR;      /**< \brief (Crccu Offset: 0x00000038) CRCCU Mode Register */
    00866   RoReg CRCCU_SR;      /**< \brief (Crccu Offset: 0x0000003C) CRCCU Status Register */
    00867   WoReg CRCCU_IER;     /**< \brief (Crccu Offset: 0x00000040) CRCCU Interrupt Enable Register */
    00868   WoReg CRCCU_IDR;     /**< \brief (Crccu Offset: 0x00000044) CRCCU Interrupt Disable Register */
    00869   RoReg CRCCU_IMR;     /**< \brief (Crccu Offset: 0x00000048) CRCCU Interrupt Mask Register */
    00870   RoReg CRCCU_ISR;     /**< \brief (Crccu Offset: 0x0000004C) CRCCU Interrupt Status Register */
    00871 } Crccu;
    00872 #endif /* __ASSEMBLY__ */
    00873 /* -------- CRCCU_DSCR : (CRCCU Offset: 0x00000000) CRCCU Descriptor Base Register -------- */
    00874 #define CRCCU_DSCR_DSCR_Pos 9
    00875 #define CRCCU_DSCR_DSCR_Msk (0x7fffffu << CRCCU_DSCR_DSCR_Pos) /**< \brief (CRCCU_DSCR) Descriptor Base Address */
    00876 #define CRCCU_DSCR_DSCR(value) ((CRCCU_DSCR_DSCR_Msk & ((value) << CRCCU_DSCR_DSCR_Pos)))
    00877 /* -------- CRCCU_DMA_EN : (CRCCU Offset: 0x00000008) CRCCU DMA Enable Register -------- */
    00878 #define CRCCU_DMA_EN_DMAEN (0x1u << 0) /**< \brief (CRCCU_DMA_EN) DMA Enable Register */
    00879 /* -------- CRCCU_DMA_DIS : (CRCCU Offset: 0x0000000C) CRCCU DMA Disable Register -------- */
    00880 #define CRCCU_DMA_DIS_DMADIS (0x1u << 0) /**< \brief (CRCCU_DMA_DIS) DMA Disable Register */
    00881 /* -------- CRCCU_DMA_SR : (CRCCU Offset: 0x00000010) CRCCU DMA Status Register -------- */
    00882 #define CRCCU_DMA_SR_DMASR (0x1u << 0) /**< \brief (CRCCU_DMA_SR) DMA Status Register */
    00883 /* -------- CRCCU_DMA_IER : (CRCCU Offset: 0x00000014) CRCCU DMA Interrupt Enable Register -------- */
    00884 #define CRCCU_DMA_IER_DMAIER (0x1u << 0) /**< \brief (CRCCU_DMA_IER) Interrupt Enable register */
    00885 /* -------- CRCCU_DMA_IDR : (CRCCU Offset: 0x00000018) CRCCU DMA Interrupt Disable Register -------- */
    00886 #define CRCCU_DMA_IDR_DMAIDR (0x1u << 0) /**< \brief (CRCCU_DMA_IDR) Interrupt Disable register */
    00887 /* -------- CRCCU_DMA_IMR : (CRCCU Offset: 0x0000001C) CRCCU DMA Interrupt Mask Register -------- */
    00888 #define CRCCU_DMA_IMR_DMAIMR (0x1u << 0) /**< \brief (CRCCU_DMA_IMR) Interrupt Mask Register */
    00889 /* -------- CRCCU_DMA_ISR : (CRCCU Offset: 0x00000020) CRCCU DMA Interrupt Status Register -------- */
    00890 #define CRCCU_DMA_ISR_DMAISR (0x1u << 0) /**< \brief (CRCCU_DMA_ISR) Interrupt Status register */
    00891 /* -------- CRCCU_CR : (CRCCU Offset: 0x00000034) CRCCU Control Register -------- */
    00892 #define CRCCU_CR_RESET (0x1u << 0) /**< \brief (CRCCU_CR) CRC Computation Reset */
    00893 /* -------- CRCCU_MR : (CRCCU Offset: 0x00000038) CRCCU Mode Register -------- */
    00894 #define CRCCU_MR_ENABLE (0x1u << 0) /**< \brief (CRCCU_MR) CRC Enable */
    00895 #define CRCCU_MR_COMPARE (0x1u << 1) /**< \brief (CRCCU_MR) CRC Compare */
    00896 #define CRCCU_MR_PTYPE_Pos 2
    00897 #define CRCCU_MR_PTYPE_Msk (0x3u << CRCCU_MR_PTYPE_Pos) /**< \brief (CRCCU_MR) Primitive Polynomial */
    00898 #define   CRCCU_MR_PTYPE_CCIT8023 (0x0u << 2) /**< \brief (CRCCU_MR) Polynom 0x04C11DB7 */
    00899 #define   CRCCU_MR_PTYPE_CASTAGNOLI (0x1u << 2) /**< \brief (CRCCU_MR) Polynom 0x1EDC6F41 */
    00900 #define   CRCCU_MR_PTYPE_CCIT16 (0x2u << 2) /**< \brief (CRCCU_MR) Polynom 0x1021 */
    00901 #define CRCCU_MR_DIVIDER_Pos 4
    00902 #define CRCCU_MR_DIVIDER_Msk (0xfu << CRCCU_MR_DIVIDER_Pos) /**< \brief (CRCCU_MR) Request Divider */
    00903 #define CRCCU_MR_DIVIDER(value) ((CRCCU_MR_DIVIDER_Msk & ((value) << CRCCU_MR_DIVIDER_Pos)))
    00904 /* -------- CRCCU_SR : (CRCCU Offset: 0x0000003C) CRCCU Status Register -------- */
    00905 #define CRCCU_SR_CRC_Pos 0
    00906 #define CRCCU_SR_CRC_Msk (0xffffffffu << CRCCU_SR_CRC_Pos) /**< \brief (CRCCU_SR) Cyclic Redundancy Check Value */
    00907 /* -------- CRCCU_IER : (CRCCU Offset: 0x00000040) CRCCU Interrupt Enable Register -------- */
    00908 #define CRCCU_IER_ERRIER (0x1u << 0) /**< \brief (CRCCU_IER) CRC Error Interrupt Enable */
    00909 /* -------- CRCCU_IDR : (CRCCU Offset: 0x00000044) CRCCU Interrupt Disable Register -------- */
    00910 #define CRCCU_IDR_ERRIDR (0x1u << 0) /**< \brief (CRCCU_IDR) CRC Error Interrupt Disable */
    00911 /* -------- CRCCU_IMR : (CRCCU Offset: 0x00000048) CRCCU Interrupt Mask Register -------- */
    00912 #define CRCCU_IMR_ERRIMR (0x1u << 0) /**< \brief (CRCCU_IMR) CRC Error Interrupt Mask */
    00913 /* -------- CRCCU_ISR : (CRCCU Offset: 0x0000004C) CRCCU Interrupt Status Register -------- */
    00914 #define CRCCU_ISR_ERRISR (0x1u << 0) /**< \brief (CRCCU_ISR) CRC Error Interrupt Status */
    00915
    00916 /*@}*/
    00917
    00918 /* ============================================================================= */
    00919 /**  SOFTWARE API DEFINITION FOR Digital-to-Analog Converter Controller */
    00920 /* ============================================================================= */
    00921 /** \addtogroup SAM3S8_DACC Digital-to-Analog Converter Controller */
    00922 /*@{*/
    00923
    00924 #ifndef __ASSEMBLY__
    00925 /** \brief Dacc hardware registers */
    00926 typedef struct {
    00927   WoReg DACC_CR;       /**< \brief (Dacc Offset: 0x00) Control Register */
    00928   RwReg DACC_MR;       /**< \brief (Dacc Offset: 0x04) Mode Register */
    00929   RoReg Reserved1[2];
    00930   WoReg DACC_CHER;     /**< \brief (Dacc Offset: 0x10) Channel Enable Register */
    00931   WoReg DACC_CHDR;     /**< \brief (Dacc Offset: 0x14) Channel Disable Register */
    00932   RoReg DACC_CHSR;     /**< \brief (Dacc Offset: 0x18) Channel Status Register */
    00933   RoReg Reserved2[1];
    00934   WoReg DACC_CDR;      /**< \brief (Dacc Offset: 0x20) Conversion Data Register */
    00935   WoReg DACC_IER;      /**< \brief (Dacc Offset: 0x24) Interrupt Enable Register */
    00936   WoReg DACC_IDR;      /**< \brief (Dacc Offset: 0x28) Interrupt Disable Register */
    00937   RoReg DACC_IMR;      /**< \brief (Dacc Offset: 0x2C) Interrupt Mask Register */
    00938   RoReg DACC_ISR;      /**< \brief (Dacc Offset: 0x30) Interrupt Status Register */
    00939   RoReg Reserved3[24];
    00940   RwReg DACC_ACR;      /**< \brief (Dacc Offset: 0x94) Analog Current Register */
    00941   RoReg Reserved4[19];
    00942   RwReg DACC_WPMR;     /**< \brief (Dacc Offset: 0xE4) Write Protect Mode register */
    00943   RoReg DACC_WPSR;     /**< \brief (Dacc Offset: 0xE8) Write Protect Status register */
    00944   RoReg Reserved5[5];
    00945   RwReg DACC_RPR;      /**< \brief (Dacc Offset: 0x100) Receive Pointer Register */
    00946   RwReg DACC_RCR;      /**< \brief (Dacc Offset: 0x104) Receive Counter Register */
    00947   RwReg DACC_TPR;      /**< \brief (Dacc Offset: 0x108) Transmit Pointer Register */
    00948   RwReg DACC_TCR;      /**< \brief (Dacc Offset: 0x10C) Transmit Counter Register */
    00949   RwReg DACC_RNPR;     /**< \brief (Dacc Offset: 0x110) Receive Next Pointer Register */
    00950   RwReg DACC_RNCR;     /**< \brief (Dacc Offset: 0x114) Receive Next Counter Register */
    00951   RwReg DACC_TNPR;     /**< \brief (Dacc Offset: 0x118) Transmit Next Pointer Register */
    00952   RwReg DACC_TNCR;     /**< \brief (Dacc Offset: 0x11C) Transmit Next Counter Register */
    00953   WoReg DACC_PTCR;     /**< \brief (Dacc Offset: 0x120) Transfer Control Register */
    00954   RoReg DACC_PTSR;     /**< \brief (Dacc Offset: 0x124) Transfer Status Register */
    00955 } Dacc;
    00956 #endif /* __ASSEMBLY__ */
    00957 /* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */
    00958 #define DACC_CR_SWRST (0x1u << 0) /**< \brief (DACC_CR) Software Reset */
    00959 /* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */
    00960 #define DACC_MR_TRGEN (0x1u << 0) /**< \brief (DACC_MR) Trigger Enable */
    00961 #define   DACC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (DACC_MR) External trigger mode disabled. DACC in free running mode. */
    00962 #define   DACC_MR_TRGEN_EN (0x1u << 0) /**< \brief (DACC_MR) External trigger mode enabled. */
    00963 #define DACC_MR_TRGSEL_Pos 1
    00964 #define DACC_MR_TRGSEL_Msk (0x7u << DACC_MR_TRGSEL_Pos) /**< \brief (DACC_MR) Trigger Selection */
    00965 #define DACC_MR_TRGSEL(value) ((DACC_MR_TRGSEL_Msk & ((value) << DACC_MR_TRGSEL_Pos)))
    00966 #define DACC_MR_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer */
    00967 #define   DACC_MR_WORD_HALF (0x0u << 4) /**< \brief (DACC_MR) Half-Word transfer */
    00968 #define   DACC_MR_WORD_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer */
    00969 #define DACC_MR_SLEEP (0x1u << 5) /**< \brief (DACC_MR) Sleep Mode */
    00970 #define DACC_MR_FASTWKUP (0x1u << 6) /**< \brief (DACC_MR) Fast Wake up Mode */
    00971 #define DACC_MR_REFRESH_Pos 8
    00972 #define DACC_MR_REFRESH_Msk (0xffu << DACC_MR_REFRESH_Pos) /**< \brief (DACC_MR) Refresh Period */
    00973 #define DACC_MR_REFRESH(value) ((DACC_MR_REFRESH_Msk & ((value) << DACC_MR_REFRESH_Pos)))
    00974 #define DACC_MR_USER_SEL_Pos 16
    00975 #define DACC_MR_USER_SEL_Msk (0x3u << DACC_MR_USER_SEL_Pos) /**< \brief (DACC_MR) User Channel Selection */
    00976 #define   DACC_MR_USER_SEL_CHANNEL0 (0x0u << 16) /**< \brief (DACC_MR) Channel 0 */
    00977 #define   DACC_MR_USER_SEL_CHANNEL1 (0x1u << 16) /**< \brief (DACC_MR) Channel 1 */
    00978 #define DACC_MR_TAG (0x1u << 20) /**< \brief (DACC_MR) Tag Selection Mode */
    00979 #define   DACC_MR_TAG_DIS (0x0u << 20) /**< \brief (DACC_MR) Tag selection mode disabled. Using USER_SEL to select the channel for the conversion. */
    00980 #define   DACC_MR_TAG_EN (0x1u << 20) /**< \brief (DACC_MR) Tag selection mode enabled */
    00981 #define DACC_MR_MAXS (0x1u << 21) /**< \brief (DACC_MR) Max Speed Mode */
    00982 #define DACC_MR_STARTUP_Pos 24
    00983 #define DACC_MR_STARTUP_Msk (0x3fu << DACC_MR_STARTUP_Pos) /**< \brief (DACC_MR) Startup Time Selection */
    00984 #define   DACC_MR_STARTUP_0 (0x0u << 24) /**< \brief (DACC_MR) 0 periods of DACClock */
    00985 #define   DACC_MR_STARTUP_8 (0x1u << 24) /**< \brief (DACC_MR) 8 periods of DACClock */
    00986 #define   DACC_MR_STARTUP_16 (0x2u << 24) /**< \brief (DACC_MR) 16 periods of DACClock */
    00987 #define   DACC_MR_STARTUP_24 (0x3u << 24) /**< \brief (DACC_MR) 24 periods of DACClock */
    00988 #define   DACC_MR_STARTUP_64 (0x4u << 24) /**< \brief (DACC_MR) 64 periods of DACClock */
    00989 #define   DACC_MR_STARTUP_80 (0x5u << 24) /**< \brief (DACC_MR) 80 periods of DACClock */
    00990 #define   DACC_MR_STARTUP_96 (0x6u << 24) /**< \brief (DACC_MR) 96 periods of DACClock */
    00991 #define   DACC_MR_STARTUP_112 (0x7u << 24) /**< \brief (DACC_MR) 112 periods of DACClock */
    00992 #define   DACC_MR_STARTUP_512 (0x8u << 24) /**< \brief (DACC_MR) 512 periods of DACClock */
    00993 #define   DACC_MR_STARTUP_576 (0x9u << 24) /**< \brief (DACC_MR) 576 periods of DACClock */
    00994 #define   DACC_MR_STARTUP_640 (0xAu << 24) /**< \brief (DACC_MR) 640 periods of DACClock */
    00995 #define   DACC_MR_STARTUP_704 (0xBu << 24) /**< \brief (DACC_MR) 704 periods of DACClock */
    00996 #define   DACC_MR_STARTUP_768 (0xCu << 24) /**< \brief (DACC_MR) 768 periods of DACClock */
    00997 #define   DACC_MR_STARTUP_832 (0xDu << 24) /**< \brief (DACC_MR) 832 periods of DACClock */
    00998 #define   DACC_MR_STARTUP_896 (0xEu << 24) /**< \brief (DACC_MR) 896 periods of DACClock */
    00999 #define   DACC_MR_STARTUP_960 (0xFu << 24) /**< \brief (DACC_MR) 960 periods of DACClock */
    01000 #define   DACC_MR_STARTUP_1024 (0x10u << 24) /**< \brief (DACC_MR) 1024 periods of DACClock */
    01001 #define   DACC_MR_STARTUP_1088 (0x11u << 24) /**< \brief (DACC_MR) 1088 periods of DACClock */
    01002 #define   DACC_MR_STARTUP_1152 (0x12u << 24) /**< \brief (DACC_MR) 1152 periods of DACClock */
    01003 #define   DACC_MR_STARTUP_1216 (0x13u << 24) /**< \brief (DACC_MR) 1216 periods of DACClock */
    01004 #define   DACC_MR_STARTUP_1280 (0x14u << 24) /**< \brief (DACC_MR) 1280 periods of DACClock */
    01005 #define   DACC_MR_STARTUP_1344 (0x15u << 24) /**< \brief (DACC_MR) 1344 periods of DACClock */
    01006 #define   DACC_MR_STARTUP_1408 (0x16u << 24) /**< \brief (DACC_MR) 1408 periods of DACClock */
    01007 #define   DACC_MR_STARTUP_1472 (0x17u << 24) /**< \brief (DACC_MR) 1472 periods of DACClock */
    01008 #define   DACC_MR_STARTUP_1536 (0x18u << 24) /**< \brief (DACC_MR) 1536 periods of DACClock */
    01009 #define   DACC_MR_STARTUP_1600 (0x19u << 24) /**< \brief (DACC_MR) 1600 periods of DACClock */
    01010 #define   DACC_MR_STARTUP_1664 (0x1Au << 24) /**< \brief (DACC_MR) 1664 periods of DACClock */
    01011 #define   DACC_MR_STARTUP_1728 (0x1Bu << 24) /**< \brief (DACC_MR) 1728 periods of DACClock */
    01012 #define   DACC_MR_STARTUP_1792 (0x1Cu << 24) /**< \brief (DACC_MR) 1792 periods of DACClock */
    01013 #define   DACC_MR_STARTUP_1856 (0x1Du << 24) /**< \brief (DACC_MR) 1856 periods of DACClock */
    01014 #define   DACC_MR_STARTUP_1920 (0x1Eu << 24) /**< \brief (DACC_MR) 1920 periods of DACClock */
    01015 #define   DACC_MR_STARTUP_1984 (0x1Fu << 24) /**< \brief (DACC_MR) 1984 periods of DACClock */
    01016 /* -------- DACC_CHER : (DACC Offset: 0x10) Channel Enable Register -------- */
    01017 #define DACC_CHER_CH0 (0x1u << 0) /**< \brief (DACC_CHER) Channel 0 Enable */
    01018 #define DACC_CHER_CH1 (0x1u << 1) /**< \brief (DACC_CHER) Channel 1 Enable */
    01019 /* -------- DACC_CHDR : (DACC Offset: 0x14) Channel Disable Register -------- */
    01020 #define DACC_CHDR_CH0 (0x1u << 0) /**< \brief (DACC_CHDR) Channel 0 Disable */
    01021 #define DACC_CHDR_CH1 (0x1u << 1) /**< \brief (DACC_CHDR) Channel 1 Disable */
    01022 /* -------- DACC_CHSR : (DACC Offset: 0x18) Channel Status Register -------- */
    01023 #define DACC_CHSR_CH0 (0x1u << 0) /**< \brief (DACC_CHSR) Channel 0 Status */
    01024 #define DACC_CHSR_CH1 (0x1u << 1) /**< \brief (DACC_CHSR) Channel 1 Status */
    01025 /* -------- DACC_CDR : (DACC Offset: 0x20) Conversion Data Register -------- */
    01026 #define DACC_CDR_DATA_Pos 0
    01027 #define DACC_CDR_DATA_Msk (0xffffffffu << DACC_CDR_DATA_Pos) /**< \brief (DACC_CDR) Data to Convert */
    01028 #define DACC_CDR_DATA(value) ((DACC_CDR_DATA_Msk & ((value) << DACC_CDR_DATA_Pos)))
    01029 /* -------- DACC_IER : (DACC Offset: 0x24) Interrupt Enable Register -------- */
    01030 #define DACC_IER_TXRDY (0x1u << 0) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable */
    01031 #define DACC_IER_EOC (0x1u << 1) /**< \brief (DACC_IER) End of Conversion Interrupt Enable */
    01032 #define DACC_IER_ENDTX (0x1u << 2) /**< \brief (DACC_IER) End of Transmit Buffer Interrupt Enable */
    01033 #define DACC_IER_TXBUFE (0x1u << 3) /**< \brief (DACC_IER) Transmit Buffer Empty Interrupt Enable */
    01034 /* -------- DACC_IDR : (DACC Offset: 0x28) Interrupt Disable Register -------- */
    01035 #define DACC_IDR_TXRDY (0x1u << 0) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable. */
    01036 #define DACC_IDR_EOC (0x1u << 1) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable */
    01037 #define DACC_IDR_ENDTX (0x1u << 2) /**< \brief (DACC_IDR) End of Transmit Buffer Interrupt Disable */
    01038 #define DACC_IDR_TXBUFE (0x1u << 3) /**< \brief (DACC_IDR) Transmit Buffer Empty Interrupt Disable */
    01039 /* -------- DACC_IMR : (DACC Offset: 0x2C) Interrupt Mask Register -------- */
    01040 #define DACC_IMR_TXRDY (0x1u << 0) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask */
    01041 #define DACC_IMR_EOC (0x1u << 1) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask */
    01042 #define DACC_IMR_ENDTX (0x1u << 2) /**< \brief (DACC_IMR) End of Transmit Buffer Interrupt Mask */
    01043 #define DACC_IMR_TXBUFE (0x1u << 3) /**< \brief (DACC_IMR) Transmit Buffer Empty Interrupt Mask */
    01044 /* -------- DACC_ISR : (DACC Offset: 0x30) Interrupt Status Register -------- */
    01045 #define DACC_ISR_TXRDY (0x1u << 0) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag */
    01046 #define DACC_ISR_EOC (0x1u << 1) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag */
    01047 #define DACC_ISR_ENDTX (0x1u << 2) /**< \brief (DACC_ISR) End of DMA Interrupt Flag */
    01048 #define DACC_ISR_TXBUFE (0x1u << 3) /**< \brief (DACC_ISR) Transmit Buffer Empty */
    01049 /* -------- DACC_ACR : (DACC Offset: 0x94) Analog Current Register -------- */
    01050 #define DACC_ACR_IBCTLCH0_Pos 0
    01051 #define DACC_ACR_IBCTLCH0_Msk (0x3u << DACC_ACR_IBCTLCH0_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */
    01052 #define DACC_ACR_IBCTLCH0(value) ((DACC_ACR_IBCTLCH0_Msk & ((value) << DACC_ACR_IBCTLCH0_Pos)))
    01053 #define DACC_ACR_IBCTLCH1_Pos 2
    01054 #define DACC_ACR_IBCTLCH1_Msk (0x3u << DACC_ACR_IBCTLCH1_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */
    01055 #define DACC_ACR_IBCTLCH1(value) ((DACC_ACR_IBCTLCH1_Msk & ((value) << DACC_ACR_IBCTLCH1_Pos)))
    01056 #define DACC_ACR_IBCTLDACCORE_Pos 8
    01057 #define DACC_ACR_IBCTLDACCORE_Msk (0x3u << DACC_ACR_IBCTLDACCORE_Pos) /**< \brief (DACC_ACR) Bias Current Control for DAC Core */
    01058 #define DACC_ACR_IBCTLDACCORE(value) ((DACC_ACR_IBCTLDACCORE_Msk & ((value) << DACC_ACR_IBCTLDACCORE_Pos)))
    01059 /* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protect Mode register -------- */
    01060 #define DACC_WPMR_WPEN (0x1u << 0) /**< \brief (DACC_WPMR) Write Protect Enable */
    01061 #define DACC_WPMR_WPKEY_Pos 8
    01062 #define DACC_WPMR_WPKEY_Msk (0xffffffu << DACC_WPMR_WPKEY_Pos) /**< \brief (DACC_WPMR) Write Protect KEY */
    01063 #define DACC_WPMR_WPKEY(value) ((DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos)))
    01064 /* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protect Status register -------- */
    01065 #define DACC_WPSR_WPROTERR (0x1u << 0) /**< \brief (DACC_WPSR) Write protection error */
    01066 #define DACC_WPSR_WPROTADDR_Pos 8
    01067 #define DACC_WPSR_WPROTADDR_Msk (0xffu << DACC_WPSR_WPROTADDR_Pos) /**< \brief (DACC_WPSR) Write protection error address */
    01068 /* -------- DACC_RPR : (DACC Offset: 0x100) Receive Pointer Register -------- */
    01069 #define DACC_RPR_RXPTR_Pos 0
    01070 #define DACC_RPR_RXPTR_Msk (0xffffffffu << DACC_RPR_RXPTR_Pos) /**< \brief (DACC_RPR) Receive Pointer Register */
    01071 #define DACC_RPR_RXPTR(value) ((DACC_RPR_RXPTR_Msk & ((value) << DACC_RPR_RXPTR_Pos)))
    01072 /* -------- DACC_RCR : (DACC Offset: 0x104) Receive Counter Register -------- */
    01073 #define DACC_RCR_RXCTR_Pos 0
    01074 #define DACC_RCR_RXCTR_Msk (0xffffu << DACC_RCR_RXCTR_Pos) /**< \brief (DACC_RCR) Receive Counter Register */
    01075 #define DACC_RCR_RXCTR(value) ((DACC_RCR_RXCTR_Msk & ((value) << DACC_RCR_RXCTR_Pos)))
    01076 /* -------- DACC_TPR : (DACC Offset: 0x108) Transmit Pointer Register -------- */
    01077 #define DACC_TPR_TXPTR_Pos 0
    01078 #define DACC_TPR_TXPTR_Msk (0xffffffffu << DACC_TPR_TXPTR_Pos) /**< \brief (DACC_TPR) Transmit Counter Register */
    01079 #define DACC_TPR_TXPTR(value) ((DACC_TPR_TXPTR_Msk & ((value) << DACC_TPR_TXPTR_Pos)))
    01080 /* -------- DACC_TCR : (DACC Offset: 0x10C) Transmit Counter Register -------- */
    01081 #define DACC_TCR_TXCTR_Pos 0
    01082 #define DACC_TCR_TXCTR_Msk (0xffffu << DACC_TCR_TXCTR_Pos) /**< \brief (DACC_TCR) Transmit Counter Register */
    01083 #define DACC_TCR_TXCTR(value) ((DACC_TCR_TXCTR_Msk & ((value) << DACC_TCR_TXCTR_Pos)))
    01084 /* -------- DACC_RNPR : (DACC Offset: 0x110) Receive Next Pointer Register -------- */
    01085 #define DACC_RNPR_RXNPTR_Pos 0
    01086 #define DACC_RNPR_RXNPTR_Msk (0xffffffffu << DACC_RNPR_RXNPTR_Pos) /**< \brief (DACC_RNPR) Receive Next Pointer */
    01087 #define DACC_RNPR_RXNPTR(value) ((DACC_RNPR_RXNPTR_Msk & ((value) << DACC_RNPR_RXNPTR_Pos)))
    01088 /* -------- DACC_RNCR : (DACC Offset: 0x114) Receive Next Counter Register -------- */
    01089 #define DACC_RNCR_RXNCTR_Pos 0
    01090 #define DACC_RNCR_RXNCTR_Msk (0xffffu << DACC_RNCR_RXNCTR_Pos) /**< \brief (DACC_RNCR) Receive Next Counter */
    01091 #define DACC_RNCR_RXNCTR(value) ((DACC_RNCR_RXNCTR_Msk & ((value) << DACC_RNCR_RXNCTR_Pos)))
    01092 /* -------- DACC_TNPR : (DACC Offset: 0x118) Transmit Next Pointer Register -------- */
    01093 #define DACC_TNPR_TXNPTR_Pos 0
    01094 #define DACC_TNPR_TXNPTR_Msk (0xffffffffu << DACC_TNPR_TXNPTR_Pos) /**< \brief (DACC_TNPR) Transmit Next Pointer */
    01095 #define DACC_TNPR_TXNPTR(value) ((DACC_TNPR_TXNPTR_Msk & ((value) << DACC_TNPR_TXNPTR_Pos)))
    01096 /* -------- DACC_TNCR : (DACC Offset: 0x11C) Transmit Next Counter Register -------- */
    01097 #define DACC_TNCR_TXNCTR_Pos 0
    01098 #define DACC_TNCR_TXNCTR_Msk (0xffffu << DACC_TNCR_TXNCTR_Pos) /**< \brief (DACC_TNCR) Transmit Counter Next */
    01099 #define DACC_TNCR_TXNCTR(value) ((DACC_TNCR_TXNCTR_Msk & ((value) << DACC_TNCR_TXNCTR_Pos)))
    01100 /* -------- DACC_PTCR : (DACC Offset: 0x120) Transfer Control Register -------- */
    01101 #define DACC_PTCR_RXTEN (0x1u << 0) /**< \brief (DACC_PTCR) Receiver Transfer Enable */
    01102 #define DACC_PTCR_RXTDIS (0x1u << 1) /**< \brief (DACC_PTCR) Receiver Transfer Disable */
    01103 #define DACC_PTCR_TXTEN (0x1u << 8) /**< \brief (DACC_PTCR) Transmitter Transfer Enable */
    01104 #define DACC_PTCR_TXTDIS (0x1u << 9) /**< \brief (DACC_PTCR) Transmitter Transfer Disable */
    01105 /* -------- DACC_PTSR : (DACC Offset: 0x124) Transfer Status Register -------- */
    01106 #define DACC_PTSR_RXTEN (0x1u << 0) /**< \brief (DACC_PTSR) Receiver Transfer Enable */
    01107 #define DACC_PTSR_TXTEN (0x1u << 8) /**< \brief (DACC_PTSR) Transmitter Transfer Enable */
    01108
    01109 /*@}*/
    01110
    01111 /* ============================================================================= */
    01112 /**  SOFTWARE API DEFINITION FOR Embedded Flash Controller */
    01113 /* ============================================================================= */
    01114 /** \addtogroup SAM3S8_EFC Embedded Flash Controller */
    01115 /*@{*/
    01116
    01117 #ifndef __ASSEMBLY__
    01118 /** \brief Efc hardware registers */
    01119 typedef struct {
    01120   RwReg EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */
    01121   WoReg EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */
    01122   RoReg EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */
    01123   RoReg EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */
    01124 } Efc;
    01125 #endif /* __ASSEMBLY__ */
    01126 /* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */
    01127 #define EEFC_FMR_FRDY (0x1u << 0) /**< \brief (EEFC_FMR) Ready Interrupt Enable */
    01128 #define EEFC_FMR_FWS_Pos 8
    01129 #define EEFC_FMR_FWS_Msk (0xfu << EEFC_FMR_FWS_Pos) /**< \brief (EEFC_FMR) Flash Wait State */
    01130 #define EEFC_FMR_FWS(value) ((EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos)))
    01131 #define EEFC_FMR_SCOD (0x1u << 16) /**< \brief (EEFC_FMR) Sequential Code Optimization Disable */
    01132 #define EEFC_FMR_FAM (0x1u << 24) /**< \brief (EEFC_FMR) Flash Access Mode */
    01133 /* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */
    01134 #define EEFC_FCR_FCMD_Pos 0
    01135 #define EEFC_FCR_FCMD_Msk (0xffu << EEFC_FCR_FCMD_Pos) /**< \brief (EEFC_FCR) Flash Command */
    01136 #define EEFC_FCR_FCMD(value) ((EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos)))
    01137 #define EEFC_FCR_FARG_Pos 8
    01138 #define EEFC_FCR_FARG_Msk (0xffffu << EEFC_FCR_FARG_Pos) /**< \brief (EEFC_FCR) Flash Command Argument */
    01139 #define EEFC_FCR_FARG(value) ((EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos)))
    01140 #define EEFC_FCR_FKEY_Pos 24
    01141 #define EEFC_FCR_FKEY_Msk (0xffu << EEFC_FCR_FKEY_Pos) /**< \brief (EEFC_FCR) Flash Writing Protection Key */
    01142 #define EEFC_FCR_FKEY(value) ((EEFC_FCR_FKEY_Msk & ((value) << EEFC_FCR_FKEY_Pos)))
    01143 /* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */
    01144 #define EEFC_FSR_FRDY (0x1u << 0) /**< \brief (EEFC_FSR) Flash Ready Status */
    01145 #define EEFC_FSR_FCMDE (0x1u << 1) /**< \brief (EEFC_FSR) Flash Command Error Status */
    01146 #define EEFC_FSR_FLOCKE (0x1u << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status */
    01147 /* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */
    01148 #define EEFC_FRR_FVALUE_Pos 0
    01149 #define EEFC_FRR_FVALUE_Msk (0xffffffffu << EEFC_FRR_FVALUE_Pos) /**< \brief (EEFC_FRR) Flash Result Value */
    01150
    01151 /*@}*/
    01152
    01153 /* ============================================================================= */
    01154 /**  SOFTWARE API DEFINITION FOR General Purpose Backup Register */
    01155 /* ============================================================================= */
    01156 /** \addtogroup SAM3S8_GPBR General Purpose Backup Register */
    01157 /*@{*/
    01158
    01159 #ifndef __ASSEMBLY__
    01160 /** \brief Gpbr hardware registers */
    01161 typedef struct {
    01162   RwReg SYS_GPBR0; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register 0 */
    01163   RwReg SYS_GPBR1; /**< \brief (Gpbr Offset: 0x4) General Purpose Backup Register 1 */
    01164   RwReg SYS_GPBR2; /**< \brief (Gpbr Offset: 0x8) General Purpose Backup Register 2 */
    01165   RwReg SYS_GPBR3; /**< \brief (Gpbr Offset: 0xC) General Purpose Backup Register 3 */
    01166   RwReg SYS_GPBR4; /**< \brief (Gpbr Offset: 0x10) General Purpose Backup Register 4 */
    01167   RwReg SYS_GPBR5; /**< \brief (Gpbr Offset: 0x14) General Purpose Backup Register 5 */
    01168   RwReg SYS_GPBR6; /**< \brief (Gpbr Offset: 0x18) General Purpose Backup Register 6 */
    01169   RwReg SYS_GPBR7; /**< \brief (Gpbr Offset: 0x1C) General Purpose Backup Register 7 */
    01170 } Gpbr;
    01171 #endif /* __ASSEMBLY__ */
    01172 /* -------- SYS_GPBR0 : (GPBR Offset: 0x0) General Purpose Backup Register 0 -------- */
    01173 #define SYS_GPBR0_GPBR_VALUE0_Pos 0
    01174 #define SYS_GPBR0_GPBR_VALUE0_Msk (0xffffffffu << SYS_GPBR0_GPBR_VALUE0_Pos) /**< \brief (SYS_GPBR0) Value of GPBR x */
    01175 #define SYS_GPBR0_GPBR_VALUE0(value) ((SYS_GPBR0_GPBR_VALUE0_Msk & ((value) << SYS_GPBR0_GPBR_VALUE0_Pos)))
    01176 /* -------- SYS_GPBR1 : (GPBR Offset: 0x4) General Purpose Backup Register 1 -------- */
    01177 #define SYS_GPBR1_GPBR_VALUE1_Pos 0
    01178 #define SYS_GPBR1_GPBR_VALUE1_Msk (0xffffffffu << SYS_GPBR1_GPBR_VALUE1_Pos) /**< \brief (SYS_GPBR1) Value of GPBR x */
    01179 #define SYS_GPBR1_GPBR_VALUE1(value) ((SYS_GPBR1_GPBR_VALUE1_Msk & ((value) << SYS_GPBR1_GPBR_VALUE1_Pos)))
    01180 /* -------- SYS_GPBR2 : (GPBR Offset: 0x8) General Purpose Backup Register 2 -------- */
    01181 #define SYS_GPBR2_GPBR_VALUE2_Pos 0
    01182 #define SYS_GPBR2_GPBR_VALUE2_Msk (0xffffffffu << SYS_GPBR2_GPBR_VALUE2_Pos) /**< \brief (SYS_GPBR2) Value of GPBR x */
    01183 #define SYS_GPBR2_GPBR_VALUE2(value) ((SYS_GPBR2_GPBR_VALUE2_Msk & ((value) << SYS_GPBR2_GPBR_VALUE2_Pos)))
    01184 /* -------- SYS_GPBR3 : (GPBR Offset: 0xC) General Purpose Backup Register 3 -------- */
    01185 #define SYS_GPBR3_GPBR_VALUE3_Pos 0
    01186 #define SYS_GPBR3_GPBR_VALUE3_Msk (0xffffffffu << SYS_GPBR3_GPBR_VALUE3_Pos) /**< \brief (SYS_GPBR3) Value of GPBR x */
    01187 #define SYS_GPBR3_GPBR_VALUE3(value) ((SYS_GPBR3_GPBR_VALUE3_Msk & ((value) << SYS_GPBR3_GPBR_VALUE3_Pos)))
    01188 /* -------- SYS_GPBR4 : (GPBR Offset: 0x10) General Purpose Backup Register 4 -------- */
    01189 #define SYS_GPBR4_GPBR_VALUE4_Pos 0
    01190 #define SYS_GPBR4_GPBR_VALUE4_Msk (0xffffffffu << SYS_GPBR4_GPBR_VALUE4_Pos) /**< \brief (SYS_GPBR4) Value of GPBR x */
    01191 #define SYS_GPBR4_GPBR_VALUE4(value) ((SYS_GPBR4_GPBR_VALUE4_Msk & ((value) << SYS_GPBR4_GPBR_VALUE4_Pos)))
    01192 /* -------- SYS_GPBR5 : (GPBR Offset: 0x14) General Purpose Backup Register 5 -------- */
    01193 #define SYS_GPBR5_GPBR_VALUE5_Pos 0
    01194 #define SYS_GPBR5_GPBR_VALUE5_Msk (0xffffffffu << SYS_GPBR5_GPBR_VALUE5_Pos) /**< \brief (SYS_GPBR5) Value of GPBR x */
    01195 #define SYS_GPBR5_GPBR_VALUE5(value) ((SYS_GPBR5_GPBR_VALUE5_Msk & ((value) << SYS_GPBR5_GPBR_VALUE5_Pos)))
    01196 /* -------- SYS_GPBR6 : (GPBR Offset: 0x18) General Purpose Backup Register 6 -------- */
    01197 #define SYS_GPBR6_GPBR_VALUE6_Pos 0
    01198 #define SYS_GPBR6_GPBR_VALUE6_Msk (0xffffffffu << SYS_GPBR6_GPBR_VALUE6_Pos) /**< \brief (SYS_GPBR6) Value of GPBR x */
    01199 #define SYS_GPBR6_GPBR_VALUE6(value) ((SYS_GPBR6_GPBR_VALUE6_Msk & ((value) << SYS_GPBR6_GPBR_VALUE6_Pos)))
    01200 /* -------- SYS_GPBR7 : (GPBR Offset: 0x1C) General Purpose Backup Register 7 -------- */
    01201 #define SYS_GPBR7_GPBR_VALUE7_Pos 0
    01202 #define SYS_GPBR7_GPBR_VALUE7_Msk (0xffffffffu << SYS_GPBR7_GPBR_VALUE7_Pos) /**< \brief (SYS_GPBR7) Value of GPBR x */
    01203 #define SYS_GPBR7_GPBR_VALUE7(value) ((SYS_GPBR7_GPBR_VALUE7_Msk & ((value) << SYS_GPBR7_GPBR_VALUE7_Pos)))
    01204
    01205 /*@}*/
    01206
    01207 /* ============================================================================= */
    01208 /**  SOFTWARE API DEFINITION FOR High Speed MultiMedia Card Interface */
    01209 /* ============================================================================= */
    01210 /** \addtogroup SAM3S8_HSMCI High Speed MultiMedia Card Interface */
    01211 /*@{*/
    01212
    01213 #ifndef __ASSEMBLY__
    01214 /** \brief Hsmci hardware registers */
    01215 typedef struct {
    01216   WoReg HSMCI_CR;        /**< \brief (Hsmci Offset: 0x00) Control Register */
    01217   RwReg HSMCI_MR;        /**< \brief (Hsmci Offset: 0x04) Mode Register */
    01218   RwReg HSMCI_DTOR;      /**< \brief (Hsmci Offset: 0x08) Data Timeout Register */
    01219   RwReg HSMCI_SDCR;      /**< \brief (Hsmci Offset: 0x0C) SD/SDIO Card Register */
    01220   RwReg HSMCI_ARGR;      /**< \brief (Hsmci Offset: 0x10) Argument Register */
    01221   WoReg HSMCI_CMDR;      /**< \brief (Hsmci Offset: 0x14) Command Register */
    01222   RwReg HSMCI_BLKR;      /**< \brief (Hsmci Offset: 0x18) Block Register */
    01223   RwReg HSMCI_CSTOR;     /**< \brief (Hsmci Offset: 0x1C) Completion Signal Timeout Register */
    01224   RoReg HSMCI_RSPR[4];   /**< \brief (Hsmci Offset: 0x20) Response Register */
    01225   RoReg HSMCI_RDR;       /**< \brief (Hsmci Offset: 0x30) Receive Data Register */
    01226   WoReg HSMCI_TDR;       /**< \brief (Hsmci Offset: 0x34) Transmit Data Register */
    01227   RoReg Reserved1[2];
    01228   RoReg HSMCI_SR;        /**< \brief (Hsmci Offset: 0x40) Status Register */
    01229   WoReg HSMCI_IER;       /**< \brief (Hsmci Offset: 0x44) Interrupt Enable Register */
    01230   WoReg HSMCI_IDR;       /**< \brief (Hsmci Offset: 0x48) Interrupt Disable Register */
    01231   RoReg HSMCI_IMR;       /**< \brief (Hsmci Offset: 0x4C) Interrupt Mask Register */
    01232   RoReg Reserved2[1];
    01233   RwReg HSMCI_CFG;       /**< \brief (Hsmci Offset: 0x54) Configuration Register */
    01234   RoReg Reserved3[35];
    01235   RwReg HSMCI_WPMR;      /**< \brief (Hsmci Offset: 0xE4) Write Protection Mode Register */
    01236   RoReg HSMCI_WPSR;      /**< \brief (Hsmci Offset: 0xE8) Write Protection Status Register */
    01237   RoReg Reserved4[5];
    01238   RwReg HSMCI_RPR;       /**< \brief (Hsmci Offset: 0x100) Receive Pointer Register */
    01239   RwReg HSMCI_RCR;       /**< \brief (Hsmci Offset: 0x104) Receive Counter Register */
    01240   RwReg HSMCI_TPR;       /**< \brief (Hsmci Offset: 0x108) Transmit Pointer Register */
    01241   RwReg HSMCI_TCR;       /**< \brief (Hsmci Offset: 0x10C) Transmit Counter Register */
    01242   RwReg HSMCI_RNPR;      /**< \brief (Hsmci Offset: 0x110) Receive Next Pointer Register */
    01243   RwReg HSMCI_RNCR;      /**< \brief (Hsmci Offset: 0x114) Receive Next Counter Register */
    01244   RwReg HSMCI_TNPR;      /**< \brief (Hsmci Offset: 0x118) Transmit Next Pointer Register */
    01245   RwReg HSMCI_TNCR;      /**< \brief (Hsmci Offset: 0x11C) Transmit Next Counter Register */
    01246   WoReg HSMCI_PTCR;      /**< \brief (Hsmci Offset: 0x120) Transfer Control Register */
    01247   RoReg HSMCI_PTSR;      /**< \brief (Hsmci Offset: 0x124) Transfer Status Register */
    01248   RoReg Reserved5[54];
    01249   RwReg HSMCI_FIFO[256]; /**< \brief (Hsmci Offset: 0x200) FIFO Memory Aperture0 */
    01250 } Hsmci;
    01251 #endif /* __ASSEMBLY__ */
    01252 /* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */
    01253 #define HSMCI_CR_MCIEN (0x1u << 0) /**< \brief (HSMCI_CR) Multi-Media Interface Enable */
    01254 #define HSMCI_CR_MCIDIS (0x1u << 1) /**< \brief (HSMCI_CR) Multi-Media Interface Disable */
    01255 #define HSMCI_CR_PWSEN (0x1u << 2) /**< \brief (HSMCI_CR) Power Save Mode Enable */
    01256 #define HSMCI_CR_PWSDIS (0x1u << 3) /**< \brief (HSMCI_CR) Power Save Mode Disable */
    01257 #define HSMCI_CR_SWRST (0x1u << 7) /**< \brief (HSMCI_CR) Software Reset */
    01258 /* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */
    01259 #define HSMCI_MR_CLKDIV_Pos 0
    01260 #define HSMCI_MR_CLKDIV_Msk (0xffu << HSMCI_MR_CLKDIV_Pos) /**< \brief (HSMCI_MR) Clock Divider */
    01261 #define HSMCI_MR_CLKDIV(value) ((HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos)))
    01262 #define HSMCI_MR_PWSDIV_Pos 8
    01263 #define HSMCI_MR_PWSDIV_Msk (0x7u << HSMCI_MR_PWSDIV_Pos) /**< \brief (HSMCI_MR) Power Saving Divider */
    01264 #define HSMCI_MR_PWSDIV(value) ((HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos)))
    01265 #define HSMCI_MR_RDPROOF (0x1u << 11) /**< \brief (HSMCI_MR)  */
    01266 #define HSMCI_MR_WRPROOF (0x1u << 12) /**< \brief (HSMCI_MR)  */
    01267 #define HSMCI_MR_FBYTE (0x1u << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */
    01268 #define HSMCI_MR_PADV (0x1u << 14) /**< \brief (HSMCI_MR) Padding Value */
    01269 #define HSMCI_MR_PDCMODE (0x1u << 15) /**< \brief (HSMCI_MR) PDC-oriented Mode */
    01270 #define HSMCI_MR_BLKLEN_Pos 16
    01271 #define HSMCI_MR_BLKLEN_Msk (0xffffu << HSMCI_MR_BLKLEN_Pos) /**< \brief (HSMCI_MR) Data Block Length */
    01272 #define HSMCI_MR_BLKLEN(value) ((HSMCI_MR_BLKLEN_Msk & ((value) << HSMCI_MR_BLKLEN_Pos)))
    01273 /* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */
    01274 #define HSMCI_DTOR_DTOCYC_Pos 0
    01275 #define HSMCI_DTOR_DTOCYC_Msk (0xfu << HSMCI_DTOR_DTOCYC_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */
    01276 #define HSMCI_DTOR_DTOCYC(value) ((HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos)))
    01277 #define HSMCI_DTOR_DTOMUL_Pos 4
    01278 #define HSMCI_DTOR_DTOMUL_Msk (0x7u << HSMCI_DTOR_DTOMUL_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Multiplier */
    01279 #define   HSMCI_DTOR_DTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_DTOR) DTOCYC */
    01280 #define   HSMCI_DTOR_DTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 16 */
    01281 #define   HSMCI_DTOR_DTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 128 */
    01282 #define   HSMCI_DTOR_DTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 256 */
    01283 #define   HSMCI_DTOR_DTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1024 */
    01284 #define   HSMCI_DTOR_DTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 4096 */
    01285 #define   HSMCI_DTOR_DTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 65536 */
    01286 #define   HSMCI_DTOR_DTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1048576 */
    01287 /* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */
    01288 #define HSMCI_SDCR_SDCSEL_Pos 0
    01289 #define HSMCI_SDCR_SDCSEL_Msk (0x3u << HSMCI_SDCR_SDCSEL_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Slot */
    01290 #define   HSMCI_SDCR_SDCSEL_SLOTA (0x0u << 0) /**< \brief (HSMCI_SDCR) Slot A is selected. */
    01291 #define   HSMCI_SDCR_SDCSEL_SLOTB (0x1u << 0) /**< \brief (HSMCI_SDCR) - */
    01292 #define   HSMCI_SDCR_SDCSEL_SLOTC (0x2u << 0) /**< \brief (HSMCI_SDCR) - */
    01293 #define   HSMCI_SDCR_SDCSEL_SLOTD (0x3u << 0) /**< \brief (HSMCI_SDCR) - */
    01294 #define HSMCI_SDCR_SDCBUS_Pos 6
    01295 #define HSMCI_SDCR_SDCBUS_Msk (0x3u << HSMCI_SDCR_SDCBUS_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Bus Width */
    01296 #define   HSMCI_SDCR_SDCBUS_1 (0x0u << 6) /**< \brief (HSMCI_SDCR) 1 bit */
    01297 #define   HSMCI_SDCR_SDCBUS_4 (0x2u << 6) /**< \brief (HSMCI_SDCR) 4 bit */
    01298 #define   HSMCI_SDCR_SDCBUS_8 (0x3u << 6) /**< \brief (HSMCI_SDCR) 8 bit */
    01299 /* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */
    01300 #define HSMCI_ARGR_ARG_Pos 0
    01301 #define HSMCI_ARGR_ARG_Msk (0xffffffffu << HSMCI_ARGR_ARG_Pos) /**< \brief (HSMCI_ARGR) Command Argument */
    01302 #define HSMCI_ARGR_ARG(value) ((HSMCI_ARGR_ARG_Msk & ((value) << HSMCI_ARGR_ARG_Pos)))
    01303 /* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */
    01304 #define HSMCI_CMDR_CMDNB_Pos 0
    01305 #define HSMCI_CMDR_CMDNB_Msk (0x3fu << HSMCI_CMDR_CMDNB_Pos) /**< \brief (HSMCI_CMDR) Command Number */
    01306 #define HSMCI_CMDR_CMDNB(value) ((HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos)))
    01307 #define HSMCI_CMDR_RSPTYP_Pos 6
    01308 #define HSMCI_CMDR_RSPTYP_Msk (0x3u << HSMCI_CMDR_RSPTYP_Pos) /**< \brief (HSMCI_CMDR) Response Type */
    01309 #define   HSMCI_CMDR_RSPTYP_NORESP (0x0u << 6) /**< \brief (HSMCI_CMDR) No response. */
    01310 #define   HSMCI_CMDR_RSPTYP_48_BIT (0x1u << 6) /**< \brief (HSMCI_CMDR) 48-bit response. */
    01311 #define   HSMCI_CMDR_RSPTYP_136_BIT (0x2u << 6) /**< \brief (HSMCI_CMDR) 136-bit response. */
    01312 #define   HSMCI_CMDR_RSPTYP_R1B (0x3u << 6) /**< \brief (HSMCI_CMDR) R1b response type */
    01313 #define HSMCI_CMDR_SPCMD_Pos 8
    01314 #define HSMCI_CMDR_SPCMD_Msk (0x7u << HSMCI_CMDR_SPCMD_Pos) /**< \brief (HSMCI_CMDR) Special Command */
    01315 #define   HSMCI_CMDR_SPCMD_STD (0x0u << 8) /**< \brief (HSMCI_CMDR) Not a special CMD. */
    01316 #define   HSMCI_CMDR_SPCMD_INIT (0x1u << 8) /**< \brief (HSMCI_CMDR) Initialization CMD: 74 clock cycles for initialization sequence. */
    01317 #define   HSMCI_CMDR_SPCMD_SYNC (0x2u << 8) /**< \brief (HSMCI_CMDR) Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. */
    01318 #define   HSMCI_CMDR_SPCMD_CE_ATA (0x3u << 8) /**< \brief (HSMCI_CMDR) CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. */
    01319 #define   HSMCI_CMDR_SPCMD_IT_CMD (0x4u << 8) /**< \brief (HSMCI_CMDR) Interrupt command: Corresponds to the Interrupt Mode (CMD40). */
    01320 #define   HSMCI_CMDR_SPCMD_IT_RESP (0x5u << 8) /**< \brief (HSMCI_CMDR) Interrupt response: Corresponds to the Interrupt Mode (CMD40). */
    01321 #define   HSMCI_CMDR_SPCMD_BOR (0x6u << 8) /**< \brief (HSMCI_CMDR) Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. */
    01322 #define   HSMCI_CMDR_SPCMD_EBO (0x7u << 8) /**< \brief (HSMCI_CMDR) End Boot Operation. This command allows the host processor to terminate the boot operation mode. */
    01323 #define HSMCI_CMDR_OPDCMD (0x1u << 11) /**< \brief (HSMCI_CMDR) Open Drain Command */
    01324 #define   HSMCI_CMDR_OPDCMD_PUSHPULL (0x0u << 11) /**< \brief (HSMCI_CMDR) Push pull command. */
    01325 #define   HSMCI_CMDR_OPDCMD_OPENDRAIN (0x1u << 11) /**< \brief (HSMCI_CMDR) Open drain command. */
    01326 #define HSMCI_CMDR_MAXLAT (0x1u << 12) /**< \brief (HSMCI_CMDR) Max Latency for Command to Response */
    01327 #define   HSMCI_CMDR_MAXLAT_5 (0x0u << 12) /**< \brief (HSMCI_CMDR) 5-cycle max latency. */
    01328 #define   HSMCI_CMDR_MAXLAT_64 (0x1u << 12) /**< \brief (HSMCI_CMDR) 64-cycle max latency. */
    01329 #define HSMCI_CMDR_TRCMD_Pos 16
    01330 #define HSMCI_CMDR_TRCMD_Msk (0x3u << HSMCI_CMDR_TRCMD_Pos) /**< \brief (HSMCI_CMDR) Transfer Command */
    01331 #define   HSMCI_CMDR_TRCMD_NO_DATA (0x0u << 16) /**< \brief (HSMCI_CMDR) No data transfer */
    01332 #define   HSMCI_CMDR_TRCMD_START_DATA (0x1u << 16) /**< \brief (HSMCI_CMDR) Start data transfer */
    01333 #define   HSMCI_CMDR_TRCMD_STOP_DATA (0x2u << 16) /**< \brief (HSMCI_CMDR) Stop data transfer */
    01334 #define HSMCI_CMDR_TRDIR (0x1u << 18) /**< \brief (HSMCI_CMDR) Transfer Direction */
    01335 #define   HSMCI_CMDR_TRDIR_WRITE (0x0u << 18) /**< \brief (HSMCI_CMDR) Write. */
    01336 #define   HSMCI_CMDR_TRDIR_READ (0x1u << 18) /**< \brief (HSMCI_CMDR) Read. */
    01337 #define HSMCI_CMDR_TRTYP_Pos 19
    01338 #define HSMCI_CMDR_TRTYP_Msk (0x7u << HSMCI_CMDR_TRTYP_Pos) /**< \brief (HSMCI_CMDR) Transfer Type */
    01339 #define   HSMCI_CMDR_TRTYP_SINGLE (0x0u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Single Block */
    01340 #define   HSMCI_CMDR_TRTYP_MULTIPLE (0x1u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Multiple Block */
    01341 #define   HSMCI_CMDR_TRTYP_STREAM (0x2u << 19) /**< \brief (HSMCI_CMDR) MMC Stream */
    01342 #define   HSMCI_CMDR_TRTYP_BYTE (0x4u << 19) /**< \brief (HSMCI_CMDR) SDIO Byte */
    01343 #define   HSMCI_CMDR_TRTYP_BLOCK (0x5u << 19) /**< \brief (HSMCI_CMDR) SDIO Block */
    01344 #define HSMCI_CMDR_IOSPCMD_Pos 24
    01345 #define HSMCI_CMDR_IOSPCMD_Msk (0x3u << HSMCI_CMDR_IOSPCMD_Pos) /**< \brief (HSMCI_CMDR) SDIO Special Command */
    01346 #define   HSMCI_CMDR_IOSPCMD_STD (0x0u << 24) /**< \brief (HSMCI_CMDR) Not an SDIO Special Command */
    01347 #define   HSMCI_CMDR_IOSPCMD_SUSPEND (0x1u << 24) /**< \brief (HSMCI_CMDR) SDIO Suspend Command */
    01348 #define   HSMCI_CMDR_IOSPCMD_RESUME (0x2u << 24) /**< \brief (HSMCI_CMDR) SDIO Resume Command */
    01349 #define HSMCI_CMDR_ATACS (0x1u << 26) /**< \brief (HSMCI_CMDR) ATA with Command Completion Signal */
    01350 #define   HSMCI_CMDR_ATACS_NORMAL (0x0u << 26) /**< \brief (HSMCI_CMDR) Normal operation mode. */
    01351 #define   HSMCI_CMDR_ATACS_COMPLETION (0x1u << 26) /**< \brief (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). */
    01352 #define HSMCI_CMDR_BOOT_ACK (0x1u << 27) /**< \brief (HSMCI_CMDR) Boot Operation Acknowledge. */
    01353 /* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */
    01354 #define HSMCI_BLKR_BCNT_Pos 0
    01355 #define HSMCI_BLKR_BCNT_Msk (0xffffu << HSMCI_BLKR_BCNT_Pos) /**< \brief (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count */
    01356 #define   HSMCI_BLKR_BCNT_MULTIPLE (0x0u << 0) /**< \brief (HSMCI_BLKR) MMC/SDCARD Multiple BlockFrom 1 to 65635: Value 0 corresponds to an infinite block transfer. */
    01357 #define   HSMCI_BLKR_BCNT_BYTE (0x4u << 0) /**< \brief (HSMCI_BLKR) SDIO ByteFrom 1 to 512 bytes: Value 0 corresponds to a 512-byte transfer.Values from 0x200 to 0xFFFF are forbidden. */
    01358 #define   HSMCI_BLKR_BCNT_BLOCK (0x5u << 0) /**< \brief (HSMCI_BLKR) SDIO BlockFrom 1 to 511 blocks: Value 0 corresponds to an infinite block transfer.Values from 0x200 to 0xFFFF are forbidden. */
    01359 #define HSMCI_BLKR_BLKLEN_Pos 16
    01360 #define HSMCI_BLKR_BLKLEN_Msk (0xffffu << HSMCI_BLKR_BLKLEN_Pos) /**< \brief (HSMCI_BLKR) Data Block Length */
    01361 #define HSMCI_BLKR_BLKLEN(value) ((HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos)))
    01362 /* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */
    01363 #define HSMCI_CSTOR_CSTOCYC_Pos 0
    01364 #define HSMCI_CSTOR_CSTOCYC_Msk (0xfu << HSMCI_CSTOR_CSTOCYC_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Cycle Number */
    01365 #define HSMCI_CSTOR_CSTOCYC(value) ((HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos)))
    01366 #define HSMCI_CSTOR_CSTOMUL_Pos 4
    01367 #define HSMCI_CSTOR_CSTOMUL_Msk (0x7u << HSMCI_CSTOR_CSTOMUL_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Multiplier */
    01368 #define   HSMCI_CSTOR_CSTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1 */
    01369 #define   HSMCI_CSTOR_CSTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 16 */
    01370 #define   HSMCI_CSTOR_CSTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 128 */
    01371 #define   HSMCI_CSTOR_CSTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 256 */
    01372 #define   HSMCI_CSTOR_CSTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1024 */
    01373 #define   HSMCI_CSTOR_CSTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 4096 */
    01374 #define   HSMCI_CSTOR_CSTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 65536 */
    01375 #define   HSMCI_CSTOR_CSTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1048576 */
    01376 /* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */
    01377 #define HSMCI_RSPR_RSP_Pos 0
    01378 #define HSMCI_RSPR_RSP_Msk (0xffffffffu << HSMCI_RSPR_RSP_Pos) /**< \brief (HSMCI_RSPR[4]) Response */
    01379 /* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */
    01380 #define HSMCI_RDR_DATA_Pos 0
    01381 #define HSMCI_RDR_DATA_Msk (0xffffffffu << HSMCI_RDR_DATA_Pos) /**< \brief (HSMCI_RDR) Data to Read */
    01382 /* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */
    01383 #define HSMCI_TDR_DATA_Pos 0
    01384 #define HSMCI_TDR_DATA_Msk (0xffffffffu << HSMCI_TDR_DATA_Pos) /**< \brief (HSMCI_TDR) Data to Write */
    01385 #define HSMCI_TDR_DATA(value) ((HSMCI_TDR_DATA_Msk & ((value) << HSMCI_TDR_DATA_Pos)))
    01386 /* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */
    01387 #define HSMCI_SR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_SR) Command Ready */
    01388 #define HSMCI_SR_RXRDY (0x1u << 1) /**< \brief (HSMCI_SR) Receiver Ready */
    01389 #define HSMCI_SR_TXRDY (0x1u << 2) /**< \brief (HSMCI_SR) Transmit Ready */
    01390 #define HSMCI_SR_BLKE (0x1u << 3) /**< \brief (HSMCI_SR) Data Block Ended */
    01391 #define HSMCI_SR_DTIP (0x1u << 4) /**< \brief (HSMCI_SR) Data Transfer in Progress */
    01392 #define HSMCI_SR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_SR) HSMCI Not Busy */
    01393 #define HSMCI_SR_ENDRX (0x1u << 6) /**< \brief (HSMCI_SR) End of RX Buffer */
    01394 #define HSMCI_SR_ENDTX (0x1u << 7) /**< \brief (HSMCI_SR) End of TX Buffer */
    01395 #define HSMCI_SR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_SR) SDIO Interrupt for Slot A */
    01396 #define HSMCI_SR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_SR) SDIO Read Wait Operation Status */
    01397 #define HSMCI_SR_CSRCV (0x1u << 13) /**< \brief (HSMCI_SR) CE-ATA Completion Signal Received */
    01398 #define HSMCI_SR_RXBUFF (0x1u << 14) /**< \brief (HSMCI_SR) RX Buffer Full */
    01399 #define HSMCI_SR_TXBUFE (0x1u << 15) /**< \brief (HSMCI_SR) TX Buffer Empty */
    01400 #define HSMCI_SR_RINDE (0x1u << 16) /**< \brief (HSMCI_SR) Response Index Error */
    01401 #define HSMCI_SR_RDIRE (0x1u << 17) /**< \brief (HSMCI_SR) Response Direction Error */
    01402 #define HSMCI_SR_RCRCE (0x1u << 18) /**< \brief (HSMCI_SR) Response CRC Error */
    01403 #define HSMCI_SR_RENDE (0x1u << 19) /**< \brief (HSMCI_SR) Response End Bit Error */
    01404 #define HSMCI_SR_RTOE (0x1u << 20) /**< \brief (HSMCI_SR) Response Time-out Error */
    01405 #define HSMCI_SR_DCRCE (0x1u << 21) /**< \brief (HSMCI_SR) Data CRC Error */
    01406 #define HSMCI_SR_DTOE (0x1u << 22) /**< \brief (HSMCI_SR) Data Time-out Error */
    01407 #define HSMCI_SR_CSTOE (0x1u << 23) /**< \brief (HSMCI_SR) Completion Signal Time-out Error */
    01408 #define HSMCI_SR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_SR) FIFO empty flag */
    01409 #define HSMCI_SR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_SR) Transfer Done flag */
    01410 #define HSMCI_SR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Received */
    01411 #define HSMCI_SR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Error */
    01412 #define HSMCI_SR_OVRE (0x1u << 30) /**< \brief (HSMCI_SR) Overrun */
    01413 #define HSMCI_SR_UNRE (0x1u << 31) /**< \brief (HSMCI_SR) Underrun */
    01414 /* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */
    01415 #define HSMCI_IER_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IER) Command Ready Interrupt Enable */
    01416 #define HSMCI_IER_RXRDY (0x1u << 1) /**< \brief (HSMCI_IER) Receiver Ready Interrupt Enable */
    01417 #define HSMCI_IER_TXRDY (0x1u << 2) /**< \brief (HSMCI_IER) Transmit Ready Interrupt Enable */
    01418 #define HSMCI_IER_BLKE (0x1u << 3) /**< \brief (HSMCI_IER) Data Block Ended Interrupt Enable */
    01419 #define HSMCI_IER_DTIP (0x1u << 4) /**< \brief (HSMCI_IER) Data Transfer in Progress Interrupt Enable */
    01420 #define HSMCI_IER_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IER) Data Not Busy Interrupt Enable */
    01421 #define HSMCI_IER_ENDRX (0x1u << 6) /**< \brief (HSMCI_IER) End of Receive Buffer Interrupt Enable */
    01422 #define HSMCI_IER_ENDTX (0x1u << 7) /**< \brief (HSMCI_IER) End of Transmit Buffer Interrupt Enable */
    01423 #define HSMCI_IER_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IER) SDIO Interrupt for Slot A Interrupt Enable */
    01424 #define HSMCI_IER_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable */
    01425 #define HSMCI_IER_CSRCV (0x1u << 13) /**< \brief (HSMCI_IER) Completion Signal Received Interrupt Enable */
    01426 #define HSMCI_IER_RXBUFF (0x1u << 14) /**< \brief (HSMCI_IER) Receive Buffer Full Interrupt Enable */
    01427 #define HSMCI_IER_TXBUFE (0x1u << 15) /**< \brief (HSMCI_IER) Transmit Buffer Empty Interrupt Enable */
    01428 #define HSMCI_IER_RINDE (0x1u << 16) /**< \brief (HSMCI_IER) Response Index Error Interrupt Enable */
    01429 #define HSMCI_IER_RDIRE (0x1u << 17) /**< \brief (HSMCI_IER) Response Direction Error Interrupt Enable */
    01430 #define HSMCI_IER_RCRCE (0x1u << 18) /**< \brief (HSMCI_IER) Response CRC Error Interrupt Enable */
    01431 #define HSMCI_IER_RENDE (0x1u << 19) /**< \brief (HSMCI_IER) Response End Bit Error Interrupt Enable */
    01432 #define HSMCI_IER_RTOE (0x1u << 20) /**< \brief (HSMCI_IER) Response Time-out Error Interrupt Enable */
    01433 #define HSMCI_IER_DCRCE (0x1u << 21) /**< \brief (HSMCI_IER) Data CRC Error Interrupt Enable */
    01434 #define HSMCI_IER_DTOE (0x1u << 22) /**< \brief (HSMCI_IER) Data Time-out Error Interrupt Enable */
    01435 #define HSMCI_IER_CSTOE (0x1u << 23) /**< \brief (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable */
    01436 #define HSMCI_IER_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IER) FIFO empty Interrupt enable */
    01437 #define HSMCI_IER_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IER) Transfer Done Interrupt enable */
    01438 #define HSMCI_IER_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IER) Boot Acknowledge Interrupt Enable */
    01439 #define HSMCI_IER_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IER) Boot Acknowledge Error Interrupt Enable */
    01440 #define HSMCI_IER_OVRE (0x1u << 30) /**< \brief (HSMCI_IER) Overrun Interrupt Enable */
    01441 #define HSMCI_IER_UNRE (0x1u << 31) /**< \brief (HSMCI_IER) Underrun Interrupt Enable */
    01442 /* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */
    01443 #define HSMCI_IDR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IDR) Command Ready Interrupt Disable */
    01444 #define HSMCI_IDR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IDR) Receiver Ready Interrupt Disable */
    01445 #define HSMCI_IDR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IDR) Transmit Ready Interrupt Disable */
    01446 #define HSMCI_IDR_BLKE (0x1u << 3) /**< \brief (HSMCI_IDR) Data Block Ended Interrupt Disable */
    01447 #define HSMCI_IDR_DTIP (0x1u << 4) /**< \brief (HSMCI_IDR) Data Transfer in Progress Interrupt Disable */
    01448 #define HSMCI_IDR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IDR) Data Not Busy Interrupt Disable */
    01449 #define HSMCI_IDR_ENDRX (0x1u << 6) /**< \brief (HSMCI_IDR) End of Receive Buffer Interrupt Disable */
    01450 #define HSMCI_IDR_ENDTX (0x1u << 7) /**< \brief (HSMCI_IDR) End of Transmit Buffer Interrupt Disable */
    01451 #define HSMCI_IDR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IDR) SDIO Interrupt for Slot A Interrupt Disable */
    01452 #define HSMCI_IDR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable */
    01453 #define HSMCI_IDR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IDR) Completion Signal received interrupt Disable */
    01454 #define HSMCI_IDR_RXBUFF (0x1u << 14) /**< \brief (HSMCI_IDR) Receive Buffer Full Interrupt Disable */
    01455 #define HSMCI_IDR_TXBUFE (0x1u << 15) /**< \brief (HSMCI_IDR) Transmit Buffer Empty Interrupt Disable */
    01456 #define HSMCI_IDR_RINDE (0x1u << 16) /**< \brief (HSMCI_IDR) Response Index Error Interrupt Disable */
    01457 #define HSMCI_IDR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IDR) Response Direction Error Interrupt Disable */
    01458 #define HSMCI_IDR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IDR) Response CRC Error Interrupt Disable */
    01459 #define HSMCI_IDR_RENDE (0x1u << 19) /**< \brief (HSMCI_IDR) Response End Bit Error Interrupt Disable */
    01460 #define HSMCI_IDR_RTOE (0x1u << 20) /**< \brief (HSMCI_IDR) Response Time-out Error Interrupt Disable */
    01461 #define HSMCI_IDR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IDR) Data CRC Error Interrupt Disable */
    01462 #define HSMCI_IDR_DTOE (0x1u << 22) /**< \brief (HSMCI_IDR) Data Time-out Error Interrupt Disable */
    01463 #define HSMCI_IDR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable */
    01464 #define HSMCI_IDR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IDR) FIFO empty Interrupt Disable */
    01465 #define HSMCI_IDR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IDR) Transfer Done Interrupt Disable */
    01466 #define HSMCI_IDR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IDR) Boot Acknowledge Interrupt Disable */
    01467 #define HSMCI_IDR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable */
    01468 #define HSMCI_IDR_OVRE (0x1u << 30) /**< \brief (HSMCI_IDR) Overrun Interrupt Disable */
    01469 #define HSMCI_IDR_UNRE (0x1u << 31) /**< \brief (HSMCI_IDR) Underrun Interrupt Disable */
    01470 /* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */
    01471 #define HSMCI_IMR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IMR) Command Ready Interrupt Mask */
    01472 #define HSMCI_IMR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IMR) Receiver Ready Interrupt Mask */
    01473 #define HSMCI_IMR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IMR) Transmit Ready Interrupt Mask */
    01474 #define HSMCI_IMR_BLKE (0x1u << 3) /**< \brief (HSMCI_IMR) Data Block Ended Interrupt Mask */
    01475 #define HSMCI_IMR_DTIP (0x1u << 4) /**< \brief (HSMCI_IMR) Data Transfer in Progress Interrupt Mask */
    01476 #define HSMCI_IMR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IMR) Data Not Busy Interrupt Mask */
    01477 #define HSMCI_IMR_ENDRX (0x1u << 6) /**< \brief (HSMCI_IMR) End of Receive Buffer Interrupt Mask */
    01478 #define HSMCI_IMR_ENDTX (0x1u << 7) /**< \brief (HSMCI_IMR) End of Transmit Buffer Interrupt Mask */
    01479 #define HSMCI_IMR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IMR) SDIO Interrupt for Slot A Interrupt Mask */
    01480 #define HSMCI_IMR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask */
    01481 #define HSMCI_IMR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IMR) Completion Signal Received Interrupt Mask */
    01482 #define HSMCI_IMR_RXBUFF (0x1u << 14) /**< \brief (HSMCI_IMR) Receive Buffer Full Interrupt Mask */
    01483 #define HSMCI_IMR_TXBUFE (0x1u << 15) /**< \brief (HSMCI_IMR) Transmit Buffer Empty Interrupt Mask */
    01484 #define HSMCI_IMR_RINDE (0x1u << 16) /**< \brief (HSMCI_IMR) Response Index Error Interrupt Mask */
    01485 #define HSMCI_IMR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IMR) Response Direction Error Interrupt Mask */
    01486 #define HSMCI_IMR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IMR) Response CRC Error Interrupt Mask */
    01487 #define HSMCI_IMR_RENDE (0x1u << 19) /**< \brief (HSMCI_IMR) Response End Bit Error Interrupt Mask */
    01488 #define HSMCI_IMR_RTOE (0x1u << 20) /**< \brief (HSMCI_IMR) Response Time-out Error Interrupt Mask */
    01489 #define HSMCI_IMR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IMR) Data CRC Error Interrupt Mask */
    01490 #define HSMCI_IMR_DTOE (0x1u << 22) /**< \brief (HSMCI_IMR) Data Time-out Error Interrupt Mask */
    01491 #define HSMCI_IMR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask */
    01492 #define HSMCI_IMR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IMR) FIFO Empty Interrupt Mask */
    01493 #define HSMCI_IMR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IMR) Transfer Done Interrupt Mask */
    01494 #define HSMCI_IMR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask */
    01495 #define HSMCI_IMR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask */
    01496 #define HSMCI_IMR_OVRE (0x1u << 30) /**< \brief (HSMCI_IMR) Overrun Interrupt Mask */
    01497 #define HSMCI_IMR_UNRE (0x1u << 31) /**< \brief (HSMCI_IMR) Underrun Interrupt Mask */
    01498 /* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */
    01499 #define HSMCI_CFG_FIFOMODE (0x1u << 0) /**< \brief (HSMCI_CFG) HSMCI Internal FIFO control mode */
    01500 #define HSMCI_CFG_FERRCTRL (0x1u << 4) /**< \brief (HSMCI_CFG) Flow Error flag reset control mode */
    01501 #define HSMCI_CFG_HSMODE (0x1u << 8) /**< \brief (HSMCI_CFG) High Speed Mode */
    01502 #define HSMCI_CFG_LSYNC (0x1u << 12) /**< \brief (HSMCI_CFG) Synchronize on the last block */
    01503 /* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */
    01504 #define HSMCI_WPMR_WP_EN (0x1u << 0) /**< \brief (HSMCI_WPMR) Write Protection Enable */
    01505 #define HSMCI_WPMR_WP_KEY_Pos 8
    01506 #define HSMCI_WPMR_WP_KEY_Msk (0xffffffu << HSMCI_WPMR_WP_KEY_Pos) /**< \brief (HSMCI_WPMR) Write Protection Key password */
    01507 #define HSMCI_WPMR_WP_KEY(value) ((HSMCI_WPMR_WP_KEY_Msk & ((value) << HSMCI_WPMR_WP_KEY_Pos)))
    01508 /* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */
    01509 #define HSMCI_WPSR_WP_VS_Pos 0
    01510 #define HSMCI_WPSR_WP_VS_Msk (0xfu << HSMCI_WPSR_WP_VS_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation Status */
    01511 #define   HSMCI_WPSR_WP_VS_NONE (0x0u << 0) /**< \brief (HSMCI_WPSR) No Write Protection Violation occurred since the last read of this register (WP_SR) */
    01512 #define   HSMCI_WPSR_WP_VS_WRITE (0x1u << 0) /**< \brief (HSMCI_WPSR) Write Protection detected unauthorized attempt to write a control register had occurred (since the last read.) */
    01513 #define   HSMCI_WPSR_WP_VS_RESET (0x2u << 0) /**< \brief (HSMCI_WPSR) Software reset had been performed while Write Protection was enabled (since the last read). */
    01514 #define   HSMCI_WPSR_WP_VS_BOTH (0x3u << 0) /**< \brief (HSMCI_WPSR) Both Write Protection violation and software reset with Write Protection enabled have occurred since the last read. */
    01515 #define HSMCI_WPSR_WP_VSRC_Pos 8
    01516 #define HSMCI_WPSR_WP_VSRC_Msk (0xffffu << HSMCI_WPSR_WP_VSRC_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation SouRCe */
    01517 /* -------- HSMCI_RPR : (HSMCI Offset: 0x100) Receive Pointer Register -------- */
    01518 #define HSMCI_RPR_RXPTR_Pos 0
    01519 #define HSMCI_RPR_RXPTR_Msk (0xffffffffu << HSMCI_RPR_RXPTR_Pos) /**< \brief (HSMCI_RPR) Receive Pointer Register */
    01520 #define HSMCI_RPR_RXPTR(value) ((HSMCI_RPR_RXPTR_Msk & ((value) << HSMCI_RPR_RXPTR_Pos)))
    01521 /* -------- HSMCI_RCR : (HSMCI Offset: 0x104) Receive Counter Register -------- */
    01522 #define HSMCI_RCR_RXCTR_Pos 0
    01523 #define HSMCI_RCR_RXCTR_Msk (0xffffu << HSMCI_RCR_RXCTR_Pos) /**< \brief (HSMCI_RCR) Receive Counter Register */
    01524 #define HSMCI_RCR_RXCTR(value) ((HSMCI_RCR_RXCTR_Msk & ((value) << HSMCI_RCR_RXCTR_Pos)))
    01525 /* -------- HSMCI_TPR : (HSMCI Offset: 0x108) Transmit Pointer Register -------- */
    01526 #define HSMCI_TPR_TXPTR_Pos 0
    01527 #define HSMCI_TPR_TXPTR_Msk (0xffffffffu << HSMCI_TPR_TXPTR_Pos) /**< \brief (HSMCI_TPR) Transmit Counter Register */
    01528 #define HSMCI_TPR_TXPTR(value) ((HSMCI_TPR_TXPTR_Msk & ((value) << HSMCI_TPR_TXPTR_Pos)))
    01529 /* -------- HSMCI_TCR : (HSMCI Offset: 0x10C) Transmit Counter Register -------- */
    01530 #define HSMCI_TCR_TXCTR_Pos 0
    01531 #define HSMCI_TCR_TXCTR_Msk (0xffffu << HSMCI_TCR_TXCTR_Pos) /**< \brief (HSMCI_TCR) Transmit Counter Register */
    01532 #define HSMCI_TCR_TXCTR(value) ((HSMCI_TCR_TXCTR_Msk & ((value) << HSMCI_TCR_TXCTR_Pos)))
    01533 /* -------- HSMCI_RNPR : (HSMCI Offset: 0x110) Receive Next Pointer Register -------- */
    01534 #define HSMCI_RNPR_RXNPTR_Pos 0
    01535 #define HSMCI_RNPR_RXNPTR_Msk (0xffffffffu << HSMCI_RNPR_RXNPTR_Pos) /**< \brief (HSMCI_RNPR) Receive Next Pointer */
    01536 #define HSMCI_RNPR_RXNPTR(value) ((HSMCI_RNPR_RXNPTR_Msk & ((value) << HSMCI_RNPR_RXNPTR_Pos)))
    01537 /* -------- HSMCI_RNCR : (HSMCI Offset: 0x114) Receive Next Counter Register -------- */
    01538 #define HSMCI_RNCR_RXNCTR_Pos 0
    01539 #define HSMCI_RNCR_RXNCTR_Msk (0xffffu << HSMCI_RNCR_RXNCTR_Pos) /**< \brief (HSMCI_RNCR) Receive Next Counter */
    01540 #define HSMCI_RNCR_RXNCTR(value) ((HSMCI_RNCR_RXNCTR_Msk & ((value) << HSMCI_RNCR_RXNCTR_Pos)))
    01541 /* -------- HSMCI_TNPR : (HSMCI Offset: 0x118) Transmit Next Pointer Register -------- */
    01542 #define HSMCI_TNPR_TXNPTR_Pos 0
    01543 #define HSMCI_TNPR_TXNPTR_Msk (0xffffffffu << HSMCI_TNPR_TXNPTR_Pos) /**< \brief (HSMCI_TNPR) Transmit Next Pointer */
    01544 #define HSMCI_TNPR_TXNPTR(value) ((HSMCI_TNPR_TXNPTR_Msk & ((value) << HSMCI_TNPR_TXNPTR_Pos)))
    01545 /* -------- HSMCI_TNCR : (HSMCI Offset: 0x11C) Transmit Next Counter Register -------- */
    01546 #define HSMCI_TNCR_TXNCTR_Pos 0
    01547 #define HSMCI_TNCR_TXNCTR_Msk (0xffffu << HSMCI_TNCR_TXNCTR_Pos) /**< \brief (HSMCI_TNCR) Transmit Counter Next */
    01548 #define HSMCI_TNCR_TXNCTR(value) ((HSMCI_TNCR_TXNCTR_Msk & ((value) << HSMCI_TNCR_TXNCTR_Pos)))
    01549 /* -------- HSMCI_PTCR : (HSMCI Offset: 0x120) Transfer Control Register -------- */
    01550 #define HSMCI_PTCR_RXTEN (0x1u << 0) /**< \brief (HSMCI_PTCR) Receiver Transfer Enable */
    01551 #define HSMCI_PTCR_RXTDIS (0x1u << 1) /**< \brief (HSMCI_PTCR) Receiver Transfer Disable */
    01552 #define HSMCI_PTCR_TXTEN (0x1u << 8) /**< \brief (HSMCI_PTCR) Transmitter Transfer Enable */
    01553 #define HSMCI_PTCR_TXTDIS (0x1u << 9) /**< \brief (HSMCI_PTCR) Transmitter Transfer Disable */
    01554 /* -------- HSMCI_PTSR : (HSMCI Offset: 0x124) Transfer Status Register -------- */
    01555 #define HSMCI_PTSR_RXTEN (0x1u << 0) /**< \brief (HSMCI_PTSR) Receiver Transfer Enable */
    01556 #define HSMCI_PTSR_TXTEN (0x1u << 8) /**< \brief (HSMCI_PTSR) Transmitter Transfer Enable */
    01557 /* -------- HSMCI_FIFO[256] : (HSMCI Offset: 0x200) FIFO Memory Aperture0 -------- */
    01558
    01559 /*@}*/
    01560
    01561 /* ============================================================================= */
    01562 /**  SOFTWARE API DEFINITION FOR AHB Bus Matrix */
    01563 /* ============================================================================= */
    01564 /** \addtogroup SAM3S8_MATRIX AHB Bus Matrix */
    01565 /*@{*/
    01566
    01567 #ifndef __ASSEMBLY__
    01568 /** \brief Matrix hardware registers */
    01569 typedef struct {
    01570   RwReg MATRIX_MCFG[4]; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register */
    01571   RoReg Reserved1[12];
    01572   RwReg MATRIX_SCFG[5]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */
    01573   RoReg Reserved2[11];
    01574   RwReg MATRIX_PRAS0;   /**< \brief (Matrix Offset: 0x0080) Priority Register A for Slave 0 */
    01575   RoReg Reserved3[1];
    01576   RwReg MATRIX_PRAS1;   /**< \brief (Matrix Offset: 0x0088) Priority Register A for Slave 1 */
    01577   RoReg Reserved4[1];
    01578   RwReg MATRIX_PRAS2;   /**< \brief (Matrix Offset: 0x0090) Priority Register A for Slave 2 */
    01579   RoReg Reserved5[1];
    01580   RwReg MATRIX_PRAS3;   /**< \brief (Matrix Offset: 0x0098) Priority Register A for Slave 3 */
    01581   RoReg Reserved6[1];
    01582   RwReg MATRIX_PRAS4;   /**< \brief (Matrix Offset: 0x00A0) Priority Register A for Slave 4 */
    01583   RoReg Reserved7[1];
    01584   RoReg Reserved8[27];
    01585   RwReg CCFG_SYSIO;     /**< \brief (Matrix Offset: 0x0114) System I/O Configuration register */
    01586   RoReg Reserved9[1];
    01587   RwReg CCFG_SMCNFCS;   /**< \brief (Matrix Offset: 0x011C) SMC Chip Select NAND Flash Assignment Register */
    01588   RoReg Reserved10[49];
    01589   RwReg MATRIX_WPMR;    /**< \brief (Matrix Offset: 0x1E4) Write Protect Mode Register */
    01590   RoReg MATRIX_WPSR;    /**< \brief (Matrix Offset: 0x1E8) Write Protect Status Register */
    01591 } Matrix;
    01592 #endif /* __ASSEMBLY__ */
    01593 /* -------- MATRIX_MCFG[4] : (MATRIX Offset: 0x0000) Master Configuration Register -------- */
    01594 #define MATRIX_MCFG_ULBT_Pos 0
    01595 #define MATRIX_MCFG_ULBT_Msk (0x7u << MATRIX_MCFG_ULBT_Pos) /**< \brief (MATRIX_MCFG[4]) Undefined Length Burst Type */
    01596 #define MATRIX_MCFG_ULBT(value) ((MATRIX_MCFG_ULBT_Msk & ((value) << MATRIX_MCFG_ULBT_Pos)))
    01597 /* -------- MATRIX_SCFG[5] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */
    01598 #define MATRIX_SCFG_SLOT_CYCLE_Pos 0
    01599 #define MATRIX_SCFG_SLOT_CYCLE_Msk (0xffu << MATRIX_SCFG_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG[5]) Maximum Number of Allowed Cycles for a Burst */
    01600 #define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos)))
    01601 #define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16
    01602 #define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG[5]) Default Master Type */
    01603 #define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos)))
    01604 #define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18
    01605 #define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0x7u << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG[5]) Fixed Default Master */
    01606 #define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos)))
    01607 #define MATRIX_SCFG_ARBT_Pos 24
    01608 #define MATRIX_SCFG_ARBT_Msk (0x3u << MATRIX_SCFG_ARBT_Pos) /**< \brief (MATRIX_SCFG[5]) Arbitration Type */
    01609 #define MATRIX_SCFG_ARBT(value) ((MATRIX_SCFG_ARBT_Msk & ((value) << MATRIX_SCFG_ARBT_Pos)))
    01610 /* -------- MATRIX_PRAS0 : (MATRIX Offset: 0x0080) Priority Register A for Slave 0 -------- */
    01611 #define MATRIX_PRAS0_M0PR_Pos 0
    01612 #define MATRIX_PRAS0_M0PR_Msk (0x3u << MATRIX_PRAS0_M0PR_Pos) /**< \brief (MATRIX_PRAS0) Master 0 Priority */
    01613 #define MATRIX_PRAS0_M0PR(value) ((MATRIX_PRAS0_M0PR_Msk & ((value) << MATRIX_PRAS0_M0PR_Pos)))
    01614 #define MATRIX_PRAS0_M1PR_Pos 4
    01615 #define MATRIX_PRAS0_M1PR_Msk (0x3u << MATRIX_PRAS0_M1PR_Pos) /**< \brief (MATRIX_PRAS0) Master 1 Priority */
    01616 #define MATRIX_PRAS0_M1PR(value) ((MATRIX_PRAS0_M1PR_Msk & ((value) << MATRIX_PRAS0_M1PR_Pos)))
    01617 #define MATRIX_PRAS0_M2PR_Pos 8
    01618 #define MATRIX_PRAS0_M2PR_Msk (0x3u << MATRIX_PRAS0_M2PR_Pos) /**< \brief (MATRIX_PRAS0) Master 2 Priority */
    01619 #define MATRIX_PRAS0_M2PR(value) ((MATRIX_PRAS0_M2PR_Msk & ((value) << MATRIX_PRAS0_M2PR_Pos)))
    01620 #define MATRIX_PRAS0_M3PR_Pos 12
    01621 #define MATRIX_PRAS0_M3PR_Msk (0x3u << MATRIX_PRAS0_M3PR_Pos) /**< \brief (MATRIX_PRAS0) Master 3 Priority */
    01622 #define MATRIX_PRAS0_M3PR(value) ((MATRIX_PRAS0_M3PR_Msk & ((value) << MATRIX_PRAS0_M3PR_Pos)))
    01623 #define MATRIX_PRAS0_M4PR_Pos 16
    01624 #define MATRIX_PRAS0_M4PR_Msk (0x3u << MATRIX_PRAS0_M4PR_Pos) /**< \brief (MATRIX_PRAS0) Master 4 Priority */
    01625 #define MATRIX_PRAS0_M4PR(value) ((MATRIX_PRAS0_M4PR_Msk & ((value) << MATRIX_PRAS0_M4PR_Pos)))
    01626 /* -------- MATRIX_PRAS1 : (MATRIX Offset: 0x0088) Priority Register A for Slave 1 -------- */
    01627 #define MATRIX_PRAS1_M0PR_Pos 0
    01628 #define MATRIX_PRAS1_M0PR_Msk (0x3u << MATRIX_PRAS1_M0PR_Pos) /**< \brief (MATRIX_PRAS1) Master 0 Priority */
    01629 #define MATRIX_PRAS1_M0PR(value) ((MATRIX_PRAS1_M0PR_Msk & ((value) << MATRIX_PRAS1_M0PR_Pos)))
    01630 #define MATRIX_PRAS1_M1PR_Pos 4
    01631 #define MATRIX_PRAS1_M1PR_Msk (0x3u << MATRIX_PRAS1_M1PR_Pos) /**< \brief (MATRIX_PRAS1) Master 1 Priority */
    01632 #define MATRIX_PRAS1_M1PR(value) ((MATRIX_PRAS1_M1PR_Msk & ((value) << MATRIX_PRAS1_M1PR_Pos)))
    01633 #define MATRIX_PRAS1_M2PR_Pos 8
    01634 #define MATRIX_PRAS1_M2PR_Msk (0x3u << MATRIX_PRAS1_M2PR_Pos) /**< \brief (MATRIX_PRAS1) Master 2 Priority */
    01635 #define MATRIX_PRAS1_M2PR(value) ((MATRIX_PRAS1_M2PR_Msk & ((value) << MATRIX_PRAS1_M2PR_Pos)))
    01636 #define MATRIX_PRAS1_M3PR_Pos 12
    01637 #define MATRIX_PRAS1_M3PR_Msk (0x3u << MATRIX_PRAS1_M3PR_Pos) /**< \brief (MATRIX_PRAS1) Master 3 Priority */
    01638 #define MATRIX_PRAS1_M3PR(value) ((MATRIX_PRAS1_M3PR_Msk & ((value) << MATRIX_PRAS1_M3PR_Pos)))
    01639 #define MATRIX_PRAS1_M4PR_Pos 16
    01640 #define MATRIX_PRAS1_M4PR_Msk (0x3u << MATRIX_PRAS1_M4PR_Pos) /**< \brief (MATRIX_PRAS1) Master 4 Priority */
    01641 #define MATRIX_PRAS1_M4PR(value) ((MATRIX_PRAS1_M4PR_Msk & ((value) << MATRIX_PRAS1_M4PR_Pos)))
    01642 /* -------- MATRIX_PRAS2 : (MATRIX Offset: 0x0090) Priority Register A for Slave 2 -------- */
    01643 #define MATRIX_PRAS2_M0PR_Pos 0
    01644 #define MATRIX_PRAS2_M0PR_Msk (0x3u << MATRIX_PRAS2_M0PR_Pos) /**< \brief (MATRIX_PRAS2) Master 0 Priority */
    01645 #define MATRIX_PRAS2_M0PR(value) ((MATRIX_PRAS2_M0PR_Msk & ((value) << MATRIX_PRAS2_M0PR_Pos)))
    01646 #define MATRIX_PRAS2_M1PR_Pos 4
    01647 #define MATRIX_PRAS2_M1PR_Msk (0x3u << MATRIX_PRAS2_M1PR_Pos) /**< \brief (MATRIX_PRAS2) Master 1 Priority */
    01648 #define MATRIX_PRAS2_M1PR(value) ((MATRIX_PRAS2_M1PR_Msk & ((value) << MATRIX_PRAS2_M1PR_Pos)))
    01649 #define MATRIX_PRAS2_M2PR_Pos 8
    01650 #define MATRIX_PRAS2_M2PR_Msk (0x3u << MATRIX_PRAS2_M2PR_Pos) /**< \brief (MATRIX_PRAS2) Master 2 Priority */
    01651 #define MATRIX_PRAS2_M2PR(value) ((MATRIX_PRAS2_M2PR_Msk & ((value) << MATRIX_PRAS2_M2PR_Pos)))
    01652 #define MATRIX_PRAS2_M3PR_Pos 12
    01653 #define MATRIX_PRAS2_M3PR_Msk (0x3u << MATRIX_PRAS2_M3PR_Pos) /**< \brief (MATRIX_PRAS2) Master 3 Priority */
    01654 #define MATRIX_PRAS2_M3PR(value) ((MATRIX_PRAS2_M3PR_Msk & ((value) << MATRIX_PRAS2_M3PR_Pos)))
    01655 #define MATRIX_PRAS2_M4PR_Pos 16
    01656 #define MATRIX_PRAS2_M4PR_Msk (0x3u << MATRIX_PRAS2_M4PR_Pos) /**< \brief (MATRIX_PRAS2) Master 4 Priority */
    01657 #define MATRIX_PRAS2_M4PR(value) ((MATRIX_PRAS2_M4PR_Msk & ((value) << MATRIX_PRAS2_M4PR_Pos)))
    01658 /* -------- MATRIX_PRAS3 : (MATRIX Offset: 0x0098) Priority Register A for Slave 3 -------- */
    01659 #define MATRIX_PRAS3_M0PR_Pos 0
    01660 #define MATRIX_PRAS3_M0PR_Msk (0x3u << MATRIX_PRAS3_M0PR_Pos) /**< \brief (MATRIX_PRAS3) Master 0 Priority */
    01661 #define MATRIX_PRAS3_M0PR(value) ((MATRIX_PRAS3_M0PR_Msk & ((value) << MATRIX_PRAS3_M0PR_Pos)))
    01662 #define MATRIX_PRAS3_M1PR_Pos 4
    01663 #define MATRIX_PRAS3_M1PR_Msk (0x3u << MATRIX_PRAS3_M1PR_Pos) /**< \brief (MATRIX_PRAS3) Master 1 Priority */
    01664 #define MATRIX_PRAS3_M1PR(value) ((MATRIX_PRAS3_M1PR_Msk & ((value) << MATRIX_PRAS3_M1PR_Pos)))
    01665 #define MATRIX_PRAS3_M2PR_Pos 8
    01666 #define MATRIX_PRAS3_M2PR_Msk (0x3u << MATRIX_PRAS3_M2PR_Pos) /**< \brief (MATRIX_PRAS3) Master 2 Priority */
    01667 #define MATRIX_PRAS3_M2PR(value) ((MATRIX_PRAS3_M2PR_Msk & ((value) << MATRIX_PRAS3_M2PR_Pos)))
    01668 #define MATRIX_PRAS3_M3PR_Pos 12
    01669 #define MATRIX_PRAS3_M3PR_Msk (0x3u << MATRIX_PRAS3_M3PR_Pos) /**< \brief (MATRIX_PRAS3) Master 3 Priority */
    01670 #define MATRIX_PRAS3_M3PR(value) ((MATRIX_PRAS3_M3PR_Msk & ((value) << MATRIX_PRAS3_M3PR_Pos)))
    01671 #define MATRIX_PRAS3_M4PR_Pos 16
    01672 #define MATRIX_PRAS3_M4PR_Msk (0x3u << MATRIX_PRAS3_M4PR_Pos) /**< \brief (MATRIX_PRAS3) Master 4 Priority */
    01673 #define MATRIX_PRAS3_M4PR(value) ((MATRIX_PRAS3_M4PR_Msk & ((value) << MATRIX_PRAS3_M4PR_Pos)))
    01674 /* -------- MATRIX_PRAS4 : (MATRIX Offset: 0x00A0) Priority Register A for Slave 4 -------- */
    01675 #define MATRIX_PRAS4_M0PR_Pos 0
    01676 #define MATRIX_PRAS4_M0PR_Msk (0x3u << MATRIX_PRAS4_M0PR_Pos) /**< \brief (MATRIX_PRAS4) Master 0 Priority */
    01677 #define MATRIX_PRAS4_M0PR(value) ((MATRIX_PRAS4_M0PR_Msk & ((value) << MATRIX_PRAS4_M0PR_Pos)))
    01678 #define MATRIX_PRAS4_M1PR_Pos 4
    01679 #define MATRIX_PRAS4_M1PR_Msk (0x3u << MATRIX_PRAS4_M1PR_Pos) /**< \brief (MATRIX_PRAS4) Master 1 Priority */
    01680 #define MATRIX_PRAS4_M1PR(value) ((MATRIX_PRAS4_M1PR_Msk & ((value) << MATRIX_PRAS4_M1PR_Pos)))
    01681 #define MATRIX_PRAS4_M2PR_Pos 8
    01682 #define MATRIX_PRAS4_M2PR_Msk (0x3u << MATRIX_PRAS4_M2PR_Pos) /**< \brief (MATRIX_PRAS4) Master 2 Priority */
    01683 #define MATRIX_PRAS4_M2PR(value) ((MATRIX_PRAS4_M2PR_Msk & ((value) << MATRIX_PRAS4_M2PR_Pos)))
    01684 #define MATRIX_PRAS4_M3PR_Pos 12
    01685 #define MATRIX_PRAS4_M3PR_Msk (0x3u << MATRIX_PRAS4_M3PR_Pos) /**< \brief (MATRIX_PRAS4) Master 3 Priority */
    01686 #define MATRIX_PRAS4_M3PR(value) ((MATRIX_PRAS4_M3PR_Msk & ((value) << MATRIX_PRAS4_M3PR_Pos)))
    01687 #define MATRIX_PRAS4_M4PR_Pos 16
    01688 #define MATRIX_PRAS4_M4PR_Msk (0x3u << MATRIX_PRAS4_M4PR_Pos) /**< \brief (MATRIX_PRAS4) Master 4 Priority */
    01689 #define MATRIX_PRAS4_M4PR(value) ((MATRIX_PRAS4_M4PR_Msk & ((value) << MATRIX_PRAS4_M4PR_Pos)))
    01690 /* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System I/O Configuration register -------- */
    01691 #define CCFG_SYSIO_SYSIO4 (0x1u << 4) /**< \brief (CCFG_SYSIO) PB4 or TDI Assignment */
    01692 #define CCFG_SYSIO_SYSIO5 (0x1u << 5) /**< \brief (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment */
    01693 #define CCFG_SYSIO_SYSIO6 (0x1u << 6) /**< \brief (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment */
    01694 #define CCFG_SYSIO_SYSIO7 (0x1u << 7) /**< \brief (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment */
    01695 #define CCFG_SYSIO_SYSIO10 (0x1u << 10) /**< \brief (CCFG_SYSIO) PB10 or DDM Assignment */
    01696 #define CCFG_SYSIO_SYSIO11 (0x1u << 11) /**< \brief (CCFG_SYSIO) PB11 or DDP Assignment */
    01697 #define CCFG_SYSIO_SYSIO12 (0x1u << 12) /**< \brief (CCFG_SYSIO) PB12 or ERASE Assignment */
    01698 /* -------- CCFG_SMCNFCS : (MATRIX Offset: 0x011C) SMC Chip Select NAND Flash Assignment Register -------- */
    01699 #define CCFG_SMCNFCS_SMC_NFCS0 (0x1u << 0) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 0 Assignment */
    01700 #define CCFG_SMCNFCS_SMC_NFCS1 (0x1u << 1) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 1 Assignment */
    01701 #define CCFG_SMCNFCS_SMC_NFCS2 (0x1u << 2) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 2 Assignment */
    01702 #define CCFG_SMCNFCS_SMC_NFCS3 (0x1u << 3) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 3 Assignment */
    01703 /* -------- MATRIX_WPMR : (MATRIX Offset: 0x1E4) Write Protect Mode Register -------- */
    01704 #define MATRIX_WPMR_WPEN (0x1u << 0) /**< \brief (MATRIX_WPMR) Write Protect ENable */
    01705 #define MATRIX_WPMR_WPKEY_Pos 8
    01706 #define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos) /**< \brief (MATRIX_WPMR) Write Protect KEY (Write-only) */
    01707 #define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos)))
    01708 /* -------- MATRIX_WPSR : (MATRIX Offset: 0x1E8) Write Protect Status Register -------- */
    01709 #define MATRIX_WPSR_WPVS (0x1u << 0) /**< \brief (MATRIX_WPSR) Write Protect Violation Status */
    01710 #define MATRIX_WPSR_WPVSRC_Pos 8
    01711 #define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos) /**< \brief (MATRIX_WPSR) Write Protect Violation Source */
    01712
    01713 /*@}*/
    01714
    01715 /* ============================================================================= */
    01716 /**  SOFTWARE API DEFINITION FOR Peripheral DMA Controller */
    01717 /* ============================================================================= */
    01718 /** \addtogroup SAM3S8_PDC Peripheral DMA Controller */
    01719 /*@{*/
    01720
    01721 #ifndef __ASSEMBLY__
    01722 /** \brief Pdc hardware registers */
    01723 typedef struct {
    01724   RoReg Reserved1[64];
    01725   RwReg PERIPH_RPR;    /**< \brief (Pdc Offset: 0x100) Receive Pointer Register */
    01726   RwReg PERIPH_RCR;    /**< \brief (Pdc Offset: 0x104) Receive Counter Register */
    01727   RwReg PERIPH_TPR;    /**< \brief (Pdc Offset: 0x108) Transmit Pointer Register */
    01728   RwReg PERIPH_TCR;    /**< \brief (Pdc Offset: 0x10C) Transmit Counter Register */
    01729   RwReg PERIPH_RNPR;   /**< \brief (Pdc Offset: 0x110) Receive Next Pointer Register */
    01730   RwReg PERIPH_RNCR;   /**< \brief (Pdc Offset: 0x114) Receive Next Counter Register */
    01731   RwReg PERIPH_TNPR;   /**< \brief (Pdc Offset: 0x118) Transmit Next Pointer Register */
    01732   RwReg PERIPH_TNCR;   /**< \brief (Pdc Offset: 0x11C) Transmit Next Counter Register */
    01733   WoReg PERIPH_PTCR;   /**< \brief (Pdc Offset: 0x120) Transfer Control Register */
    01734   RoReg PERIPH_PTSR;   /**< \brief (Pdc Offset: 0x124) Transfer Status Register */
    01735 } Pdc;
    01736 #endif /* __ASSEMBLY__ */
    01737 /* -------- PERIPH_RPR : (PDC Offset: 0x100) Receive Pointer Register -------- */
    01738 #define PERIPH_RPR_RXPTR_Pos 0
    01739 #define PERIPH_RPR_RXPTR_Msk (0xffffffffu << PERIPH_RPR_RXPTR_Pos) /**< \brief (PERIPH_RPR) Receive Pointer Register */
    01740 #define PERIPH_RPR_RXPTR(value) ((PERIPH_RPR_RXPTR_Msk & ((value) << PERIPH_RPR_RXPTR_Pos)))
    01741 /* -------- PERIPH_RCR : (PDC Offset: 0x104) Receive Counter Register -------- */
    01742 #define PERIPH_RCR_RXCTR_Pos 0
    01743 #define PERIPH_RCR_RXCTR_Msk (0xffffu << PERIPH_RCR_RXCTR_Pos) /**< \brief (PERIPH_RCR) Receive Counter Register */
    01744 #define PERIPH_RCR_RXCTR(value) ((PERIPH_RCR_RXCTR_Msk & ((value) << PERIPH_RCR_RXCTR_Pos)))
    01745 /* -------- PERIPH_TPR : (PDC Offset: 0x108) Transmit Pointer Register -------- */
    01746 #define PERIPH_TPR_TXPTR_Pos 0
    01747 #define PERIPH_TPR_TXPTR_Msk (0xffffffffu << PERIPH_TPR_TXPTR_Pos) /**< \brief (PERIPH_TPR) Transmit Counter Register */
    01748 #define PERIPH_TPR_TXPTR(value) ((PERIPH_TPR_TXPTR_Msk & ((value) << PERIPH_TPR_TXPTR_Pos)))
    01749 /* -------- PERIPH_TCR : (PDC Offset: 0x10C) Transmit Counter Register -------- */
    01750 #define PERIPH_TCR_TXCTR_Pos 0
    01751 #define PERIPH_TCR_TXCTR_Msk (0xffffu << PERIPH_TCR_TXCTR_Pos) /**< \brief (PERIPH_TCR) Transmit Counter Register */
    01752 #define PERIPH_TCR_TXCTR(value) ((PERIPH_TCR_TXCTR_Msk & ((value) << PERIPH_TCR_TXCTR_Pos)))
    01753 /* -------- PERIPH_RNPR : (PDC Offset: 0x110) Receive Next Pointer Register -------- */
    01754 #define PERIPH_RNPR_RXNPTR_Pos 0
    01755 #define PERIPH_RNPR_RXNPTR_Msk (0xffffffffu << PERIPH_RNPR_RXNPTR_Pos) /**< \brief (PERIPH_RNPR) Receive Next Pointer */
    01756 #define PERIPH_RNPR_RXNPTR(value) ((PERIPH_RNPR_RXNPTR_Msk & ((value) << PERIPH_RNPR_RXNPTR_Pos)))
    01757 /* -------- PERIPH_RNCR : (PDC Offset: 0x114) Receive Next Counter Register -------- */
    01758 #define PERIPH_RNCR_RXNCTR_Pos 0
    01759 #define PERIPH_RNCR_RXNCTR_Msk (0xffffu << PERIPH_RNCR_RXNCTR_Pos) /**< \brief (PERIPH_RNCR) Receive Next Counter */
    01760 #define PERIPH_RNCR_RXNCTR(value) ((PERIPH_RNCR_RXNCTR_Msk & ((value) << PERIPH_RNCR_RXNCTR_Pos)))
    01761 /* -------- PERIPH_TNPR : (PDC Offset: 0x118) Transmit Next Pointer Register -------- */
    01762 #define PERIPH_TNPR_TXNPTR_Pos 0
    01763 #define PERIPH_TNPR_TXNPTR_Msk (0xffffffffu << PERIPH_TNPR_TXNPTR_Pos) /**< \brief (PERIPH_TNPR) Transmit Next Pointer */
    01764 #define PERIPH_TNPR_TXNPTR(value) ((PERIPH_TNPR_TXNPTR_Msk & ((value) << PERIPH_TNPR_TXNPTR_Pos)))
    01765 /* -------- PERIPH_TNCR : (PDC Offset: 0x11C) Transmit Next Counter Register -------- */
    01766 #define PERIPH_TNCR_TXNCTR_Pos 0
    01767 #define PERIPH_TNCR_TXNCTR_Msk (0xffffu << PERIPH_TNCR_TXNCTR_Pos) /**< \brief (PERIPH_TNCR) Transmit Counter Next */
    01768 #define PERIPH_TNCR_TXNCTR(value) ((PERIPH_TNCR_TXNCTR_Msk & ((value) << PERIPH_TNCR_TXNCTR_Pos)))
    01769 /* -------- PERIPH_PTCR : (PDC Offset: 0x120) Transfer Control Register -------- */
    01770 #define PERIPH_PTCR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTCR) Receiver Transfer Enable */
    01771 #define PERIPH_PTCR_RXTDIS (0x1u << 1) /**< \brief (PERIPH_PTCR) Receiver Transfer Disable */
    01772 #define PERIPH_PTCR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTCR) Transmitter Transfer Enable */
    01773 #define PERIPH_PTCR_TXTDIS (0x1u << 9) /**< \brief (PERIPH_PTCR) Transmitter Transfer Disable */
    01774 /* -------- PERIPH_PTSR : (PDC Offset: 0x124) Transfer Status Register -------- */
    01775 #define PERIPH_PTSR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTSR) Receiver Transfer Enable */
    01776 #define PERIPH_PTSR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTSR) Transmitter Transfer Enable */
    01777
    01778 /*@}*/
    01779
    01780 /* ============================================================================= */
    01781 /**  SOFTWARE API DEFINITION FOR Parallel Input/Output Controller */
    01782 /* ============================================================================= */
    01783 /** \addtogroup SAM3S8_PIO Parallel Input/Output Controller */
    01784 /*@{*/
    01785
    01786 #ifndef __ASSEMBLY__
    01787 /** \brief Pio hardware registers */
    01788 typedef struct {
    01789   WoReg PIO_PER;        /**< \brief (Pio Offset: 0x0000) PIO Enable Register */
    01790   WoReg PIO_PDR;        /**< \brief (Pio Offset: 0x0004) PIO Disable Register */
    01791   RoReg PIO_PSR;        /**< \brief (Pio Offset: 0x0008) PIO Status Register */
    01792   RoReg Reserved1[1];
    01793   WoReg PIO_OER;        /**< \brief (Pio Offset: 0x0010) Output Enable Register */
    01794   WoReg PIO_ODR;        /**< \brief (Pio Offset: 0x0014) Output Disable Register */
    01795   RoReg PIO_OSR;        /**< \brief (Pio Offset: 0x0018) Output Status Register */
    01796   RoReg Reserved2[1];
    01797   WoReg PIO_IFER;       /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */
    01798   WoReg PIO_IFDR;       /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */
    01799   RoReg PIO_IFSR;       /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */
    01800   RoReg Reserved3[1];
    01801   WoReg PIO_SODR;       /**< \brief (Pio Offset: 0x0030) Set Output Data Register */
    01802   WoReg PIO_CODR;       /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */
    01803   RwReg PIO_ODSR;       /**< \brief (Pio Offset: 0x0038) Output Data Status Register */
    01804   RoReg PIO_PDSR;       /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */
    01805   WoReg PIO_IER;        /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */
    01806   WoReg PIO_IDR;        /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */
    01807   RoReg PIO_IMR;        /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */
    01808   RoReg PIO_ISR;        /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */
    01809   WoReg PIO_MDER;       /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */
    01810   WoReg PIO_MDDR;       /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */
    01811   RoReg PIO_MDSR;       /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */
    01812   RoReg Reserved4[1];
    01813   WoReg PIO_PUDR;       /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */
    01814   WoReg PIO_PUER;       /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */
    01815   RoReg PIO_PUSR;       /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */
    01816   RoReg Reserved5[1];
    01817   RwReg PIO_ABCDSR[2];  /**< \brief (Pio Offset: 0x0070) Peripheral Select Register */
    01818   RoReg Reserved6[2];
    01819   WoReg PIO_IFSCDR;     /**< \brief (Pio Offset: 0x0080) Input Filter Slow Clock Disable Register */
    01820   WoReg PIO_IFSCER;     /**< \brief (Pio Offset: 0x0084) Input Filter Slow Clock Enable Register */
    01821   RoReg PIO_IFSCSR;     /**< \brief (Pio Offset: 0x0088) Input Filter Slow Clock Status Register */
    01822   RwReg PIO_SCDR;       /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */
    01823   WoReg PIO_PPDDR;      /**< \brief (Pio Offset: 0x0090) Pad Pull-down Disable Register */
    01824   WoReg PIO_PPDER;      /**< \brief (Pio Offset: 0x0094) Pad Pull-down Enable Register */
    01825   RoReg PIO_PPDSR;      /**< \brief (Pio Offset: 0x0098) Pad Pull-down Status Register */
    01826   RoReg Reserved7[1];
    01827   WoReg PIO_OWER;       /**< \brief (Pio Offset: 0x00A0) Output Write Enable */
    01828   WoReg PIO_OWDR;       /**< \brief (Pio Offset: 0x00A4) Output Write Disable */
    01829   RoReg PIO_OWSR;       /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */
    01830   RoReg Reserved8[1];
    01831   WoReg PIO_AIMER;      /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */
    01832   WoReg PIO_AIMDR;      /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disables Register */
    01833   RoReg PIO_AIMMR;      /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */
    01834   RoReg Reserved9[1];
    01835   WoReg PIO_ESR;        /**< \brief (Pio Offset: 0x00C0) Edge Select Register */
    01836   WoReg PIO_LSR;        /**< \brief (Pio Offset: 0x00C4) Level Select Register */
    01837   RoReg PIO_ELSR;       /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */
    01838   RoReg Reserved10[1];
    01839   WoReg PIO_FELLSR;     /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low Level Select Register */
    01840   WoReg PIO_REHLSR;     /**< \brief (Pio Offset: 0x00D4) Rising Edge/ High Level Select Register */
    01841   RoReg PIO_FRLHSR;     /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */
    01842   RoReg Reserved11[1];
    01843   RoReg PIO_LOCKSR;     /**< \brief (Pio Offset: 0x00E0) Lock Status */
    01844   RwReg PIO_WPMR;       /**< \brief (Pio Offset: 0x00E4) Write Protect Mode Register */
    01845   RoReg PIO_WPSR;       /**< \brief (Pio Offset: 0x00E8) Write Protect Status Register */
    01846   RoReg Reserved12[5];
    01847   RwReg PIO_SCHMITT;    /**< \brief (Pio Offset: 0x0100) Schmitt Trigger Register */
    01848   RoReg Reserved13[19];
    01849   RwReg PIO_PCMR;       /**< \brief (Pio Offset: 0x150) Parallel Capture Mode Register */
    01850   WoReg PIO_PCIER;      /**< \brief (Pio Offset: 0x154) Parallel Capture Interrupt Enable Register */
    01851   WoReg PIO_PCIDR;      /**< \brief (Pio Offset: 0x158) Parallel Capture Interrupt Disable Register */
    01852   RoReg PIO_PCIMR;      /**< \brief (Pio Offset: 0x15C) Parallel Capture Interrupt Mask Register */
    01853   RoReg PIO_PCISR;      /**< \brief (Pio Offset: 0x160) Parallel Capture Interrupt Status Register */
    01854   RoReg PIO_PCRHR;      /**< \brief (Pio Offset: 0x164) Parallel Capture Reception Holding Register */
    01855   RwReg PIO_RPR;        /**< \brief (Pio Offset: 0x168) Receive Pointer Register */
    01856   RwReg PIO_RCR;        /**< \brief (Pio Offset: 0x16C) Receive Counter Register */
    01857   RwReg PIO_TPR;        /**< \brief (Pio Offset: 0x170) Transmit Pointer Register */
    01858   RwReg PIO_TCR;        /**< \brief (Pio Offset: 0x174) Transmit Counter Register */
    01859   RwReg PIO_RNPR;       /**< \brief (Pio Offset: 0x178) Receive Next Pointer Register */
    01860   RwReg PIO_RNCR;       /**< \brief (Pio Offset: 0x17C) Receive Next Counter Register */
    01861   RwReg PIO_TNPR;       /**< \brief (Pio Offset: 0x180) Transmit Next Pointer Register */
    01862   RwReg PIO_TNCR;       /**< \brief (Pio Offset: 0x184) Transmit Next Counter Register */
    01863   WoReg PIO_PTCR;       /**< \brief (Pio Offset: 0x188) Transfer Control Register */
    01864   RoReg PIO_PTSR;       /**< \brief (Pio Offset: 0x18C) Transfer Status Register */
    01865 } Pio;
    01866 #endif /* __ASSEMBLY__ */
    01867 /* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */
    01868 #define PIO_PER_P0 (0x1u << 0) /**< \brief (PIO_PER) PIO Enable */
    01869 #define PIO_PER_P1 (0x1u << 1) /**< \brief (PIO_PER) PIO Enable */
    01870 #define PIO_PER_P2 (0x1u << 2) /**< \brief (PIO_PER) PIO Enable */
    01871 #define PIO_PER_P3 (0x1u << 3) /**< \brief (PIO_PER) PIO Enable */
    01872 #define PIO_PER_P4 (0x1u << 4) /**< \brief (PIO_PER) PIO Enable */
    01873 #define PIO_PER_P5 (0x1u << 5) /**< \brief (PIO_PER) PIO Enable */
    01874 #define PIO_PER_P6 (0x1u << 6) /**< \brief (PIO_PER) PIO Enable */
    01875 #define PIO_PER_P7 (0x1u << 7) /**< \brief (PIO_PER) PIO Enable */
    01876 #define PIO_PER_P8 (0x1u << 8) /**< \brief (PIO_PER) PIO Enable */
    01877 #define PIO_PER_P9 (0x1u << 9) /**< \brief (PIO_PER) PIO Enable */
    01878 #define PIO_PER_P10 (0x1u << 10) /**< \brief (PIO_PER) PIO Enable */
    01879 #define PIO_PER_P11 (0x1u << 11) /**< \brief (PIO_PER) PIO Enable */
    01880 #define PIO_PER_P12 (0x1u << 12) /**< \brief (PIO_PER) PIO Enable */
    01881 #define PIO_PER_P13 (0x1u << 13) /**< \brief (PIO_PER) PIO Enable */
    01882 #define PIO_PER_P14 (0x1u << 14) /**< \brief (PIO_PER) PIO Enable */
    01883 #define PIO_PER_P15 (0x1u << 15) /**< \brief (PIO_PER) PIO Enable */
    01884 #define PIO_PER_P16 (0x1u << 16) /**< \brief (PIO_PER) PIO Enable */
    01885 #define PIO_PER_P17 (0x1u << 17) /**< \brief (PIO_PER) PIO Enable */
    01886 #define PIO_PER_P18 (0x1u << 18) /**< \brief (PIO_PER) PIO Enable */
    01887 #define PIO_PER_P19 (0x1u << 19) /**< \brief (PIO_PER) PIO Enable */
    01888 #define PIO_PER_P20 (0x1u << 20) /**< \brief (PIO_PER) PIO Enable */
    01889 #define PIO_PER_P21 (0x1u << 21) /**< \brief (PIO_PER) PIO Enable */
    01890 #define PIO_PER_P22 (0x1u << 22) /**< \brief (PIO_PER) PIO Enable */
    01891 #define PIO_PER_P23 (0x1u << 23) /**< \brief (PIO_PER) PIO Enable */
    01892 #define PIO_PER_P24 (0x1u << 24) /**< \brief (PIO_PER) PIO Enable */
    01893 #define PIO_PER_P25 (0x1u << 25) /**< \brief (PIO_PER) PIO Enable */
    01894 #define PIO_PER_P26 (0x1u << 26) /**< \brief (PIO_PER) PIO Enable */
    01895 #define PIO_PER_P27 (0x1u << 27) /**< \brief (PIO_PER) PIO Enable */
    01896 #define PIO_PER_P28 (0x1u << 28) /**< \brief (PIO_PER) PIO Enable */
    01897 #define PIO_PER_P29 (0x1u << 29) /**< \brief (PIO_PER) PIO Enable */
    01898 #define PIO_PER_P30 (0x1u << 30) /**< \brief (PIO_PER) PIO Enable */
    01899 #define PIO_PER_P31 (0x1u << 31) /**< \brief (PIO_PER) PIO Enable */
    01900 /* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */
    01901 #define PIO_PDR_P0 (0x1u << 0) /**< \brief (PIO_PDR) PIO Disable */
    01902 #define PIO_PDR_P1 (0x1u << 1) /**< \brief (PIO_PDR) PIO Disable */
    01903 #define PIO_PDR_P2 (0x1u << 2) /**< \brief (PIO_PDR) PIO Disable */
    01904 #define PIO_PDR_P3 (0x1u << 3) /**< \brief (PIO_PDR) PIO Disable */
    01905 #define PIO_PDR_P4 (0x1u << 4) /**< \brief (PIO_PDR) PIO Disable */
    01906 #define PIO_PDR_P5 (0x1u << 5) /**< \brief (PIO_PDR) PIO Disable */
    01907 #define PIO_PDR_P6 (0x1u << 6) /**< \brief (PIO_PDR) PIO Disable */
    01908 #define PIO_PDR_P7 (0x1u << 7) /**< \brief (PIO_PDR) PIO Disable */
    01909 #define PIO_PDR_P8 (0x1u << 8) /**< \brief (PIO_PDR) PIO Disable */
    01910 #define PIO_PDR_P9 (0x1u << 9) /**< \brief (PIO_PDR) PIO Disable */
    01911 #define PIO_PDR_P10 (0x1u << 10) /**< \brief (PIO_PDR) PIO Disable */
    01912 #define PIO_PDR_P11 (0x1u << 11) /**< \brief (PIO_PDR) PIO Disable */
    01913 #define PIO_PDR_P12 (0x1u << 12) /**< \brief (PIO_PDR) PIO Disable */
    01914 #define PIO_PDR_P13 (0x1u << 13) /**< \brief (PIO_PDR) PIO Disable */
    01915 #define PIO_PDR_P14 (0x1u << 14) /**< \brief (PIO_PDR) PIO Disable */
    01916 #define PIO_PDR_P15 (0x1u << 15) /**< \brief (PIO_PDR) PIO Disable */
    01917 #define PIO_PDR_P16 (0x1u << 16) /**< \brief (PIO_PDR) PIO Disable */
    01918 #define PIO_PDR_P17 (0x1u << 17) /**< \brief (PIO_PDR) PIO Disable */
    01919 #define PIO_PDR_P18 (0x1u << 18) /**< \brief (PIO_PDR) PIO Disable */
    01920 #define PIO_PDR_P19 (0x1u << 19) /**< \brief (PIO_PDR) PIO Disable */
    01921 #define PIO_PDR_P20 (0x1u << 20) /**< \brief (PIO_PDR) PIO Disable */
    01922 #define PIO_PDR_P21 (0x1u << 21) /**< \brief (PIO_PDR) PIO Disable */
    01923 #define PIO_PDR_P22 (0x1u << 22) /**< \brief (PIO_PDR) PIO Disable */
    01924 #define PIO_PDR_P23 (0x1u << 23) /**< \brief (PIO_PDR) PIO Disable */
    01925 #define PIO_PDR_P24 (0x1u << 24) /**< \brief (PIO_PDR) PIO Disable */
    01926 #define PIO_PDR_P25 (0x1u << 25) /**< \brief (PIO_PDR) PIO Disable */
    01927 #define PIO_PDR_P26 (0x1u << 26) /**< \brief (PIO_PDR) PIO Disable */
    01928 #define PIO_PDR_P27 (0x1u << 27) /**< \brief (PIO_PDR) PIO Disable */
    01929 #define PIO_PDR_P28 (0x1u << 28) /**< \brief (PIO_PDR) PIO Disable */
    01930 #define PIO_PDR_P29 (0x1u << 29) /**< \brief (PIO_PDR) PIO Disable */
    01931 #define PIO_PDR_P30 (0x1u << 30) /**< \brief (PIO_PDR) PIO Disable */
    01932 #define PIO_PDR_P31 (0x1u << 31) /**< \brief (PIO_PDR) PIO Disable */
    01933 /* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */
    01934 #define PIO_PSR_P0 (0x1u << 0) /**< \brief (PIO_PSR) PIO Status */
    01935 #define PIO_PSR_P1 (0x1u << 1) /**< \brief (PIO_PSR) PIO Status */
    01936 #define PIO_PSR_P2 (0x1u << 2) /**< \brief (PIO_PSR) PIO Status */
    01937 #define PIO_PSR_P3 (0x1u << 3) /**< \brief (PIO_PSR) PIO Status */
    01938 #define PIO_PSR_P4 (0x1u << 4) /**< \brief (PIO_PSR) PIO Status */
    01939 #define PIO_PSR_P5 (0x1u << 5) /**< \brief (PIO_PSR) PIO Status */
    01940 #define PIO_PSR_P6 (0x1u << 6) /**< \brief (PIO_PSR) PIO Status */
    01941 #define PIO_PSR_P7 (0x1u << 7) /**< \brief (PIO_PSR) PIO Status */
    01942 #define PIO_PSR_P8 (0x1u << 8) /**< \brief (PIO_PSR) PIO Status */
    01943 #define PIO_PSR_P9 (0x1u << 9) /**< \brief (PIO_PSR) PIO Status */
    01944 #define PIO_PSR_P10 (0x1u << 10) /**< \brief (PIO_PSR) PIO Status */
    01945 #define PIO_PSR_P11 (0x1u << 11) /**< \brief (PIO_PSR) PIO Status */
    01946 #define PIO_PSR_P12 (0x1u << 12) /**< \brief (PIO_PSR) PIO Status */
    01947 #define PIO_PSR_P13 (0x1u << 13) /**< \brief (PIO_PSR) PIO Status */
    01948 #define PIO_PSR_P14 (0x1u << 14) /**< \brief (PIO_PSR) PIO Status */
    01949 #define PIO_PSR_P15 (0x1u << 15) /**< \brief (PIO_PSR) PIO Status */
    01950 #define PIO_PSR_P16 (0x1u << 16) /**< \brief (PIO_PSR) PIO Status */
    01951 #define PIO_PSR_P17 (0x1u << 17) /**< \brief (PIO_PSR) PIO Status */
    01952 #define PIO_PSR_P18 (0x1u << 18) /**< \brief (PIO_PSR) PIO Status */
    01953 #define PIO_PSR_P19 (0x1u << 19) /**< \brief (PIO_PSR) PIO Status */
    01954 #define PIO_PSR_P20 (0x1u << 20) /**< \brief (PIO_PSR) PIO Status */
    01955 #define PIO_PSR_P21 (0x1u << 21) /**< \brief (PIO_PSR) PIO Status */
    01956 #define PIO_PSR_P22 (0x1u << 22) /**< \brief (PIO_PSR) PIO Status */
    01957 #define PIO_PSR_P23 (0x1u << 23) /**< \brief (PIO_PSR) PIO Status */
    01958 #define PIO_PSR_P24 (0x1u << 24) /**< \brief (PIO_PSR) PIO Status */
    01959 #define PIO_PSR_P25 (0x1u << 25) /**< \brief (PIO_PSR) PIO Status */
    01960 #define PIO_PSR_P26 (0x1u << 26) /**< \brief (PIO_PSR) PIO Status */
    01961 #define PIO_PSR_P27 (0x1u << 27) /**< \brief (PIO_PSR) PIO Status */
    01962 #define PIO_PSR_P28 (0x1u << 28) /**< \brief (PIO_PSR) PIO Status */
    01963 #define PIO_PSR_P29 (0x1u << 29) /**< \brief (PIO_PSR) PIO Status */
    01964 #define PIO_PSR_P30 (0x1u << 30) /**< \brief (PIO_PSR) PIO Status */
    01965 #define PIO_PSR_P31 (0x1u << 31) /**< \brief (PIO_PSR) PIO Status */
    01966 /* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */
    01967 #define PIO_OER_P0 (0x1u << 0) /**< \brief (PIO_OER) Output Enable */
    01968 #define PIO_OER_P1 (0x1u << 1) /**< \brief (PIO_OER) Output Enable */
    01969 #define PIO_OER_P2 (0x1u << 2) /**< \brief (PIO_OER) Output Enable */
    01970 #define PIO_OER_P3 (0x1u << 3) /**< \brief (PIO_OER) Output Enable */
    01971 #define PIO_OER_P4 (0x1u << 4) /**< \brief (PIO_OER) Output Enable */
    01972 #define PIO_OER_P5 (0x1u << 5) /**< \brief (PIO_OER) Output Enable */
    01973 #define PIO_OER_P6 (0x1u << 6) /**< \brief (PIO_OER) Output Enable */
    01974 #define PIO_OER_P7 (0x1u << 7) /**< \brief (PIO_OER) Output Enable */
    01975 #define PIO_OER_P8 (0x1u << 8) /**< \brief (PIO_OER) Output Enable */
    01976 #define PIO_OER_P9 (0x1u << 9) /**< \brief (PIO_OER) Output Enable */
    01977 #define PIO_OER_P10 (0x1u << 10) /**< \brief (PIO_OER) Output Enable */
    01978 #define PIO_OER_P11 (0x1u << 11) /**< \brief (PIO_OER) Output Enable */
    01979 #define PIO_OER_P12 (0x1u << 12) /**< \brief (PIO_OER) Output Enable */
    01980 #define PIO_OER_P13 (0x1u << 13) /**< \brief (PIO_OER) Output Enable */
    01981 #define PIO_OER_P14 (0x1u << 14) /**< \brief (PIO_OER) Output Enable */
    01982 #define PIO_OER_P15 (0x1u << 15) /**< \brief (PIO_OER) Output Enable */
    01983 #define PIO_OER_P16 (0x1u << 16) /**< \brief (PIO_OER) Output Enable */
    01984 #define PIO_OER_P17 (0x1u << 17) /**< \brief (PIO_OER) Output Enable */
    01985 #define PIO_OER_P18 (0x1u << 18) /**< \brief (PIO_OER) Output Enable */
    01986 #define PIO_OER_P19 (0x1u << 19) /**< \brief (PIO_OER) Output Enable */
    01987 #define PIO_OER_P20 (0x1u << 20) /**< \brief (PIO_OER) Output Enable */
    01988 #define PIO_OER_P21 (0x1u << 21) /**< \brief (PIO_OER) Output Enable */
    01989 #define PIO_OER_P22 (0x1u << 22) /**< \brief (PIO_OER) Output Enable */
    01990 #define PIO_OER_P23 (0x1u << 23) /**< \brief (PIO_OER) Output Enable */
    01991 #define PIO_OER_P24 (0x1u << 24) /**< \brief (PIO_OER) Output Enable */
    01992 #define PIO_OER_P25 (0x1u << 25) /**< \brief (PIO_OER) Output Enable */
    01993 #define PIO_OER_P26 (0x1u << 26) /**< \brief (PIO_OER) Output Enable */
    01994 #define PIO_OER_P27 (0x1u << 27) /**< \brief (PIO_OER) Output Enable */
    01995 #define PIO_OER_P28 (0x1u << 28) /**< \brief (PIO_OER) Output Enable */
    01996 #define PIO_OER_P29 (0x1u << 29) /**< \brief (PIO_OER) Output Enable */
    01997 #define PIO_OER_P30 (0x1u << 30) /**< \brief (PIO_OER) Output Enable */
    01998 #define PIO_OER_P31 (0x1u << 31) /**< \brief (PIO_OER) Output Enable */
    01999 /* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */
    02000 #define PIO_ODR_P0 (0x1u << 0) /**< \brief (PIO_ODR) Output Disable */
    02001 #define PIO_ODR_P1 (0x1u << 1) /**< \brief (PIO_ODR) Output Disable */
    02002 #define PIO_ODR_P2 (0x1u << 2) /**< \brief (PIO_ODR) Output Disable */
    02003 #define PIO_ODR_P3 (0x1u << 3) /**< \brief (PIO_ODR) Output Disable */
    02004 #define PIO_ODR_P4 (0x1u << 4) /**< \brief (PIO_ODR) Output Disable */
    02005 #define PIO_ODR_P5 (0x1u << 5) /**< \brief (PIO_ODR) Output Disable */
    02006 #define PIO_ODR_P6 (0x1u << 6) /**< \brief (PIO_ODR) Output Disable */
    02007 #define PIO_ODR_P7 (0x1u << 7) /**< \brief (PIO_ODR) Output Disable */
    02008 #define PIO_ODR_P8 (0x1u << 8) /**< \brief (PIO_ODR) Output Disable */
    02009 #define PIO_ODR_P9 (0x1u << 9) /**< \brief (PIO_ODR) Output Disable */
    02010 #define PIO_ODR_P10 (0x1u << 10) /**< \brief (PIO_ODR) Output Disable */
    02011 #define PIO_ODR_P11 (0x1u << 11) /**< \brief (PIO_ODR) Output Disable */
    02012 #define PIO_ODR_P12 (0x1u << 12) /**< \brief (PIO_ODR) Output Disable */
    02013 #define PIO_ODR_P13 (0x1u << 13) /**< \brief (PIO_ODR) Output Disable */
    02014 #define PIO_ODR_P14 (0x1u << 14) /**< \brief (PIO_ODR) Output Disable */
    02015 #define PIO_ODR_P15 (0x1u << 15) /**< \brief (PIO_ODR) Output Disable */
    02016 #define PIO_ODR_P16 (0x1u << 16) /**< \brief (PIO_ODR) Output Disable */
    02017 #define PIO_ODR_P17 (0x1u << 17) /**< \brief (PIO_ODR) Output Disable */
    02018 #define PIO_ODR_P18 (0x1u << 18) /**< \brief (PIO_ODR) Output Disable */
    02019 #define PIO_ODR_P19 (0x1u << 19) /**< \brief (PIO_ODR) Output Disable */
    02020 #define PIO_ODR_P20 (0x1u << 20) /**< \brief (PIO_ODR) Output Disable */
    02021 #define PIO_ODR_P21 (0x1u << 21) /**< \brief (PIO_ODR) Output Disable */
    02022 #define PIO_ODR_P22 (0x1u << 22) /**< \brief (PIO_ODR) Output Disable */
    02023 #define PIO_ODR_P23 (0x1u << 23) /**< \brief (PIO_ODR) Output Disable */
    02024 #define PIO_ODR_P24 (0x1u << 24) /**< \brief (PIO_ODR) Output Disable */
    02025 #define PIO_ODR_P25 (0x1u << 25) /**< \brief (PIO_ODR) Output Disable */
    02026 #define PIO_ODR_P26 (0x1u << 26) /**< \brief (PIO_ODR) Output Disable */
    02027 #define PIO_ODR_P27 (0x1u << 27) /**< \brief (PIO_ODR) Output Disable */
    02028 #define PIO_ODR_P28 (0x1u << 28) /**< \brief (PIO_ODR) Output Disable */
    02029 #define PIO_ODR_P29 (0x1u << 29) /**< \brief (PIO_ODR) Output Disable */
    02030 #define PIO_ODR_P30 (0x1u << 30) /**< \brief (PIO_ODR) Output Disable */
    02031 #define PIO_ODR_P31 (0x1u << 31) /**< \brief (PIO_ODR) Output Disable */
    02032 /* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */
    02033 #define PIO_OSR_P0 (0x1u << 0) /**< \brief (PIO_OSR) Output Status */
    02034 #define PIO_OSR_P1 (0x1u << 1) /**< \brief (PIO_OSR) Output Status */
    02035 #define PIO_OSR_P2 (0x1u << 2) /**< \brief (PIO_OSR) Output Status */
    02036 #define PIO_OSR_P3 (0x1u << 3) /**< \brief (PIO_OSR) Output Status */
    02037 #define PIO_OSR_P4 (0x1u << 4) /**< \brief (PIO_OSR) Output Status */
    02038 #define PIO_OSR_P5 (0x1u << 5) /**< \brief (PIO_OSR) Output Status */
    02039 #define PIO_OSR_P6 (0x1u << 6) /**< \brief (PIO_OSR) Output Status */
    02040 #define PIO_OSR_P7 (0x1u << 7) /**< \brief (PIO_OSR) Output Status */
    02041 #define PIO_OSR_P8 (0x1u << 8) /**< \brief (PIO_OSR) Output Status */
    02042 #define PIO_OSR_P9 (0x1u << 9) /**< \brief (PIO_OSR) Output Status */
    02043 #define PIO_OSR_P10 (0x1u << 10) /**< \brief (PIO_OSR) Output Status */
    02044 #define PIO_OSR_P11 (0x1u << 11) /**< \brief (PIO_OSR) Output Status */
    02045 #define PIO_OSR_P12 (0x1u << 12) /**< \brief (PIO_OSR) Output Status */
    02046 #define PIO_OSR_P13 (0x1u << 13) /**< \brief (PIO_OSR) Output Status */
    02047 #define PIO_OSR_P14 (0x1u << 14) /**< \brief (PIO_OSR) Output Status */
    02048 #define PIO_OSR_P15 (0x1u << 15) /**< \brief (PIO_OSR) Output Status */
    02049 #define PIO_OSR_P16 (0x1u << 16) /**< \brief (PIO_OSR) Output Status */
    02050 #define PIO_OSR_P17 (0x1u << 17) /**< \brief (PIO_OSR) Output Status */
    02051 #define PIO_OSR_P18 (0x1u << 18) /**< \brief (PIO_OSR) Output Status */
    02052 #define PIO_OSR_P19 (0x1u << 19) /**< \brief (PIO_OSR) Output Status */
    02053 #define PIO_OSR_P20 (0x1u << 20) /**< \brief (PIO_OSR) Output Status */
    02054 #define PIO_OSR_P21 (0x1u << 21) /**< \brief (PIO_OSR) Output Status */
    02055 #define PIO_OSR_P22 (0x1u << 22) /**< \brief (PIO_OSR) Output Status */
    02056 #define PIO_OSR_P23 (0x1u << 23) /**< \brief (PIO_OSR) Output Status */
    02057 #define PIO_OSR_P24 (0x1u << 24) /**< \brief (PIO_OSR) Output Status */
    02058 #define PIO_OSR_P25 (0x1u << 25) /**< \brief (PIO_OSR) Output Status */
    02059 #define PIO_OSR_P26 (0x1u << 26) /**< \brief (PIO_OSR) Output Status */
    02060 #define PIO_OSR_P27 (0x1u << 27) /**< \brief (PIO_OSR) Output Status */
    02061 #define PIO_OSR_P28 (0x1u << 28) /**< \brief (PIO_OSR) Output Status */
    02062 #define PIO_OSR_P29 (0x1u << 29) /**< \brief (PIO_OSR) Output Status */
    02063 #define PIO_OSR_P30 (0x1u << 30) /**< \brief (PIO_OSR) Output Status */
    02064 #define PIO_OSR_P31 (0x1u << 31) /**< \brief (PIO_OSR) Output Status */
    02065 /* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */
    02066 #define PIO_IFER_P0 (0x1u << 0) /**< \brief (PIO_IFER) Input Filter Enable */
    02067 #define PIO_IFER_P1 (0x1u << 1) /**< \brief (PIO_IFER) Input Filter Enable */
    02068 #define PIO_IFER_P2 (0x1u << 2) /**< \brief (PIO_IFER) Input Filter Enable */
    02069 #define PIO_IFER_P3 (0x1u << 3) /**< \brief (PIO_IFER) Input Filter Enable */
    02070 #define PIO_IFER_P4 (0x1u << 4) /**< \brief (PIO_IFER) Input Filter Enable */
    02071 #define PIO_IFER_P5 (0x1u << 5) /**< \brief (PIO_IFER) Input Filter Enable */
    02072 #define PIO_IFER_P6 (0x1u << 6) /**< \brief (PIO_IFER) Input Filter Enable */
    02073 #define PIO_IFER_P7 (0x1u << 7) /**< \brief (PIO_IFER) Input Filter Enable */
    02074 #define PIO_IFER_P8 (0x1u << 8) /**< \brief (PIO_IFER) Input Filter Enable */
    02075 #define PIO_IFER_P9 (0x1u << 9) /**< \brief (PIO_IFER) Input Filter Enable */
    02076 #define PIO_IFER_P10 (0x1u << 10) /**< \brief (PIO_IFER) Input Filter Enable */
    02077 #define PIO_IFER_P11 (0x1u << 11) /**< \brief (PIO_IFER) Input Filter Enable */
    02078 #define PIO_IFER_P12 (0x1u << 12) /**< \brief (PIO_IFER) Input Filter Enable */
    02079 #define PIO_IFER_P13 (0x1u << 13) /**< \brief (PIO_IFER) Input Filter Enable */
    02080 #define PIO_IFER_P14 (0x1u << 14) /**< \brief (PIO_IFER) Input Filter Enable */
    02081 #define PIO_IFER_P15 (0x1u << 15) /**< \brief (PIO_IFER) Input Filter Enable */
    02082 #define PIO_IFER_P16 (0x1u << 16) /**< \brief (PIO_IFER) Input Filter Enable */
    02083 #define PIO_IFER_P17 (0x1u << 17) /**< \brief (PIO_IFER) Input Filter Enable */
    02084 #define PIO_IFER_P18 (0x1u << 18) /**< \brief (PIO_IFER) Input Filter Enable */
    02085 #define PIO_IFER_P19 (0x1u << 19) /**< \brief (PIO_IFER) Input Filter Enable */
    02086 #define PIO_IFER_P20 (0x1u << 20) /**< \brief (PIO_IFER) Input Filter Enable */
    02087 #define PIO_IFER_P21 (0x1u << 21) /**< \brief (PIO_IFER) Input Filter Enable */
    02088 #define PIO_IFER_P22 (0x1u << 22) /**< \brief (PIO_IFER) Input Filter Enable */
    02089 #define PIO_IFER_P23 (0x1u << 23) /**< \brief (PIO_IFER) Input Filter Enable */
    02090 #define PIO_IFER_P24 (0x1u << 24) /**< \brief (PIO_IFER) Input Filter Enable */
    02091 #define PIO_IFER_P25 (0x1u << 25) /**< \brief (PIO_IFER) Input Filter Enable */
    02092 #define PIO_IFER_P26 (0x1u << 26) /**< \brief (PIO_IFER) Input Filter Enable */
    02093 #define PIO_IFER_P27 (0x1u << 27) /**< \brief (PIO_IFER) Input Filter Enable */
    02094 #define PIO_IFER_P28 (0x1u << 28) /**< \brief (PIO_IFER) Input Filter Enable */
    02095 #define PIO_IFER_P29 (0x1u << 29) /**< \brief (PIO_IFER) Input Filter Enable */
    02096 #define PIO_IFER_P30 (0x1u << 30) /**< \brief (PIO_IFER) Input Filter Enable */
    02097 #define PIO_IFER_P31 (0x1u << 31) /**< \brief (PIO_IFER) Input Filter Enable */
    02098 /* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */
    02099 #define PIO_IFDR_P0 (0x1u << 0) /**< \brief (PIO_IFDR) Input Filter Disable */
    02100 #define PIO_IFDR_P1 (0x1u << 1) /**< \brief (PIO_IFDR) Input Filter Disable */
    02101 #define PIO_IFDR_P2 (0x1u << 2) /**< \brief (PIO_IFDR) Input Filter Disable */
    02102 #define PIO_IFDR_P3 (0x1u << 3) /**< \brief (PIO_IFDR) Input Filter Disable */
    02103 #define PIO_IFDR_P4 (0x1u << 4) /**< \brief (PIO_IFDR) Input Filter Disable */
    02104 #define PIO_IFDR_P5 (0x1u << 5) /**< \brief (PIO_IFDR) Input Filter Disable */
    02105 #define PIO_IFDR_P6 (0x1u << 6) /**< \brief (PIO_IFDR) Input Filter Disable */
    02106 #define PIO_IFDR_P7 (0x1u << 7) /**< \brief (PIO_IFDR) Input Filter Disable */
    02107 #define PIO_IFDR_P8 (0x1u << 8) /**< \brief (PIO_IFDR) Input Filter Disable */
    02108 #define PIO_IFDR_P9 (0x1u << 9) /**< \brief (PIO_IFDR) Input Filter Disable */
    02109 #define PIO_IFDR_P10 (0x1u << 10) /**< \brief (PIO_IFDR) Input Filter Disable */
    02110 #define PIO_IFDR_P11 (0x1u << 11) /**< \brief (PIO_IFDR) Input Filter Disable */
    02111 #define PIO_IFDR_P12 (0x1u << 12) /**< \brief (PIO_IFDR) Input Filter Disable */
    02112 #define PIO_IFDR_P13 (0x1u << 13) /**< \brief (PIO_IFDR) Input Filter Disable */
    02113 #define PIO_IFDR_P14 (0x1u << 14) /**< \brief (PIO_IFDR) Input Filter Disable */
    02114 #define PIO_IFDR_P15 (0x1u << 15) /**< \brief (PIO_IFDR) Input Filter Disable */
    02115 #define PIO_IFDR_P16 (0x1u << 16) /**< \brief (PIO_IFDR) Input Filter Disable */
    02116 #define PIO_IFDR_P17 (0x1u << 17) /**< \brief (PIO_IFDR) Input Filter Disable */
    02117 #define PIO_IFDR_P18 (0x1u << 18) /**< \brief (PIO_IFDR) Input Filter Disable */
    02118 #define PIO_IFDR_P19 (0x1u << 19) /**< \brief (PIO_IFDR) Input Filter Disable */
    02119 #define PIO_IFDR_P20 (0x1u << 20) /**< \brief (PIO_IFDR) Input Filter Disable */
    02120 #define PIO_IFDR_P21 (0x1u << 21) /**< \brief (PIO_IFDR) Input Filter Disable */
    02121 #define PIO_IFDR_P22 (0x1u << 22) /**< \brief (PIO_IFDR) Input Filter Disable */
    02122 #define PIO_IFDR_P23 (0x1u << 23) /**< \brief (PIO_IFDR) Input Filter Disable */
    02123 #define PIO_IFDR_P24 (0x1u << 24) /**< \brief (PIO_IFDR) Input Filter Disable */
    02124 #define PIO_IFDR_P25 (0x1u << 25) /**< \brief (PIO_IFDR) Input Filter Disable */
    02125 #define PIO_IFDR_P26 (0x1u << 26) /**< \brief (PIO_IFDR) Input Filter Disable */
    02126 #define PIO_IFDR_P27 (0x1u << 27) /**< \brief (PIO_IFDR) Input Filter Disable */
    02127 #define PIO_IFDR_P28 (0x1u << 28) /**< \brief (PIO_IFDR) Input Filter Disable */
    02128 #define PIO_IFDR_P29 (0x1u << 29) /**< \brief (PIO_IFDR) Input Filter Disable */
    02129 #define PIO_IFDR_P30 (0x1u << 30) /**< \brief (PIO_IFDR) Input Filter Disable */
    02130 #define PIO_IFDR_P31 (0x1u << 31) /**< \brief (PIO_IFDR) Input Filter Disable */
    02131 /* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */
    02132 #define PIO_IFSR_P0 (0x1u << 0) /**< \brief (PIO_IFSR) Input Filer Status */
    02133 #define PIO_IFSR_P1 (0x1u << 1) /**< \brief (PIO_IFSR) Input Filer Status */
    02134 #define PIO_IFSR_P2 (0x1u << 2) /**< \brief (PIO_IFSR) Input Filer Status */
    02135 #define PIO_IFSR_P3 (0x1u << 3) /**< \brief (PIO_IFSR) Input Filer Status */
    02136 #define PIO_IFSR_P4 (0x1u << 4) /**< \brief (PIO_IFSR) Input Filer Status */
    02137 #define PIO_IFSR_P5 (0x1u << 5) /**< \brief (PIO_IFSR) Input Filer Status */
    02138 #define PIO_IFSR_P6 (0x1u << 6) /**< \brief (PIO_IFSR) Input Filer Status */
    02139 #define PIO_IFSR_P7 (0x1u << 7) /**< \brief (PIO_IFSR) Input Filer Status */
    02140 #define PIO_IFSR_P8 (0x1u << 8) /**< \brief (PIO_IFSR) Input Filer Status */
    02141 #define PIO_IFSR_P9 (0x1u << 9) /**< \brief (PIO_IFSR) Input Filer Status */
    02142 #define PIO_IFSR_P10 (0x1u << 10) /**< \brief (PIO_IFSR) Input Filer Status */
    02143 #define PIO_IFSR_P11 (0x1u << 11) /**< \brief (PIO_IFSR) Input Filer Status */
    02144 #define PIO_IFSR_P12 (0x1u << 12) /**< \brief (PIO_IFSR) Input Filer Status */
    02145 #define PIO_IFSR_P13 (0x1u << 13) /**< \brief (PIO_IFSR) Input Filer Status */
    02146 #define PIO_IFSR_P14 (0x1u << 14) /**< \brief (PIO_IFSR) Input Filer Status */
    02147 #define PIO_IFSR_P15 (0x1u << 15) /**< \brief (PIO_IFSR) Input Filer Status */
    02148 #define PIO_IFSR_P16 (0x1u << 16) /**< \brief (PIO_IFSR) Input Filer Status */
    02149 #define PIO_IFSR_P17 (0x1u << 17) /**< \brief (PIO_IFSR) Input Filer Status */
    02150 #define PIO_IFSR_P18 (0x1u << 18) /**< \brief (PIO_IFSR) Input Filer Status */
    02151 #define PIO_IFSR_P19 (0x1u << 19) /**< \brief (PIO_IFSR) Input Filer Status */
    02152 #define PIO_IFSR_P20 (0x1u << 20) /**< \brief (PIO_IFSR) Input Filer Status */
    02153 #define PIO_IFSR_P21 (0x1u << 21) /**< \brief (PIO_IFSR) Input Filer Status */
    02154 #define PIO_IFSR_P22 (0x1u << 22) /**< \brief (PIO_IFSR) Input Filer Status */
    02155 #define PIO_IFSR_P23 (0x1u << 23) /**< \brief (PIO_IFSR) Input Filer Status */
    02156 #define PIO_IFSR_P24 (0x1u << 24) /**< \brief (PIO_IFSR) Input Filer Status */
    02157 #define PIO_IFSR_P25 (0x1u << 25) /**< \brief (PIO_IFSR) Input Filer Status */
    02158 #define PIO_IFSR_P26 (0x1u << 26) /**< \brief (PIO_IFSR) Input Filer Status */
    02159 #define PIO_IFSR_P27 (0x1u << 27) /**< \brief (PIO_IFSR) Input Filer Status */
    02160 #define PIO_IFSR_P28 (0x1u << 28) /**< \brief (PIO_IFSR) Input Filer Status */
    02161 #define PIO_IFSR_P29 (0x1u << 29) /**< \brief (PIO_IFSR) Input Filer Status */
    02162 #define PIO_IFSR_P30 (0x1u << 30) /**< \brief (PIO_IFSR) Input Filer Status */
    02163 #define PIO_IFSR_P31 (0x1u << 31) /**< \brief (PIO_IFSR) Input Filer Status */
    02164 /* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */
    02165 #define PIO_SODR_P0 (0x1u << 0) /**< \brief (PIO_SODR) Set Output Data */
    02166 #define PIO_SODR_P1 (0x1u << 1) /**< \brief (PIO_SODR) Set Output Data */
    02167 #define PIO_SODR_P2 (0x1u << 2) /**< \brief (PIO_SODR) Set Output Data */
    02168 #define PIO_SODR_P3 (0x1u << 3) /**< \brief (PIO_SODR) Set Output Data */
    02169 #define PIO_SODR_P4 (0x1u << 4) /**< \brief (PIO_SODR) Set Output Data */
    02170 #define PIO_SODR_P5 (0x1u << 5) /**< \brief (PIO_SODR) Set Output Data */
    02171 #define PIO_SODR_P6 (0x1u << 6) /**< \brief (PIO_SODR) Set Output Data */
    02172 #define PIO_SODR_P7 (0x1u << 7) /**< \brief (PIO_SODR) Set Output Data */
    02173 #define PIO_SODR_P8 (0x1u << 8) /**< \brief (PIO_SODR) Set Output Data */
    02174 #define PIO_SODR_P9 (0x1u << 9) /**< \brief (PIO_SODR) Set Output Data */
    02175 #define PIO_SODR_P10 (0x1u << 10) /**< \brief (PIO_SODR) Set Output Data */
    02176 #define PIO_SODR_P11 (0x1u << 11) /**< \brief (PIO_SODR) Set Output Data */
    02177 #define PIO_SODR_P12 (0x1u << 12) /**< \brief (PIO_SODR) Set Output Data */
    02178 #define PIO_SODR_P13 (0x1u << 13) /**< \brief (PIO_SODR) Set Output Data */
    02179 #define PIO_SODR_P14 (0x1u << 14) /**< \brief (PIO_SODR) Set Output Data */
    02180 #define PIO_SODR_P15 (0x1u << 15) /**< \brief (PIO_SODR) Set Output Data */
    02181 #define PIO_SODR_P16 (0x1u << 16) /**< \brief (PIO_SODR) Set Output Data */
    02182 #define PIO_SODR_P17 (0x1u << 17) /**< \brief (PIO_SODR) Set Output Data */
    02183 #define PIO_SODR_P18 (0x1u << 18) /**< \brief (PIO_SODR) Set Output Data */
    02184 #define PIO_SODR_P19 (0x1u << 19) /**< \brief (PIO_SODR) Set Output Data */
    02185 #define PIO_SODR_P20 (0x1u << 20) /**< \brief (PIO_SODR) Set Output Data */
    02186 #define PIO_SODR_P21 (0x1u << 21) /**< \brief (PIO_SODR) Set Output Data */
    02187 #define PIO_SODR_P22 (0x1u << 22) /**< \brief (PIO_SODR) Set Output Data */
    02188 #define PIO_SODR_P23 (0x1u << 23) /**< \brief (PIO_SODR) Set Output Data */
    02189 #define PIO_SODR_P24 (0x1u << 24) /**< \brief (PIO_SODR) Set Output Data */
    02190 #define PIO_SODR_P25 (0x1u << 25) /**< \brief (PIO_SODR) Set Output Data */
    02191 #define PIO_SODR_P26 (0x1u << 26) /**< \brief (PIO_SODR) Set Output Data */
    02192 #define PIO_SODR_P27 (0x1u << 27) /**< \brief (PIO_SODR) Set Output Data */
    02193 #define PIO_SODR_P28 (0x1u << 28) /**< \brief (PIO_SODR) Set Output Data */
    02194 #define PIO_SODR_P29 (0x1u << 29) /**< \brief (PIO_SODR) Set Output Data */
    02195 #define PIO_SODR_P30 (0x1u << 30) /**< \brief (PIO_SODR) Set Output Data */
    02196 #define PIO_SODR_P31 (0x1u << 31) /**< \brief (PIO_SODR) Set Output Data */
    02197 /* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */
    02198 #define PIO_CODR_P0 (0x1u << 0) /**< \brief (PIO_CODR) Clear Output Data */
    02199 #define PIO_CODR_P1 (0x1u << 1) /**< \brief (PIO_CODR) Clear Output Data */
    02200 #define PIO_CODR_P2 (0x1u << 2) /**< \brief (PIO_CODR) Clear Output Data */
    02201 #define PIO_CODR_P3 (0x1u << 3) /**< \brief (PIO_CODR) Clear Output Data */
    02202 #define PIO_CODR_P4 (0x1u << 4) /**< \brief (PIO_CODR) Clear Output Data */
    02203 #define PIO_CODR_P5 (0x1u << 5) /**< \brief (PIO_CODR) Clear Output Data */
    02204 #define PIO_CODR_P6 (0x1u << 6) /**< \brief (PIO_CODR) Clear Output Data */
    02205 #define PIO_CODR_P7 (0x1u << 7) /**< \brief (PIO_CODR) Clear Output Data */
    02206 #define PIO_CODR_P8 (0x1u << 8) /**< \brief (PIO_CODR) Clear Output Data */
    02207 #define PIO_CODR_P9 (0x1u << 9) /**< \brief (PIO_CODR) Clear Output Data */
    02208 #define PIO_CODR_P10 (0x1u << 10) /**< \brief (PIO_CODR) Clear Output Data */
    02209 #define PIO_CODR_P11 (0x1u << 11) /**< \brief (PIO_CODR) Clear Output Data */
    02210 #define PIO_CODR_P12 (0x1u << 12) /**< \brief (PIO_CODR) Clear Output Data */
    02211 #define PIO_CODR_P13 (0x1u << 13) /**< \brief (PIO_CODR) Clear Output Data */
    02212 #define PIO_CODR_P14 (0x1u << 14) /**< \brief (PIO_CODR) Clear Output Data */
    02213 #define PIO_CODR_P15 (0x1u << 15) /**< \brief (PIO_CODR) Clear Output Data */
    02214 #define PIO_CODR_P16 (0x1u << 16) /**< \brief (PIO_CODR) Clear Output Data */
    02215 #define PIO_CODR_P17 (0x1u << 17) /**< \brief (PIO_CODR) Clear Output Data */
    02216 #define PIO_CODR_P18 (0x1u << 18) /**< \brief (PIO_CODR) Clear Output Data */
    02217 #define PIO_CODR_P19 (0x1u << 19) /**< \brief (PIO_CODR) Clear Output Data */
    02218 #define PIO_CODR_P20 (0x1u << 20) /**< \brief (PIO_CODR) Clear Output Data */
    02219 #define PIO_CODR_P21 (0x1u << 21) /**< \brief (PIO_CODR) Clear Output Data */
    02220 #define PIO_CODR_P22 (0x1u << 22) /**< \brief (PIO_CODR) Clear Output Data */
    02221 #define PIO_CODR_P23 (0x1u << 23) /**< \brief (PIO_CODR) Clear Output Data */
    02222 #define PIO_CODR_P24 (0x1u << 24) /**< \brief (PIO_CODR) Clear Output Data */
    02223 #define PIO_CODR_P25 (0x1u << 25) /**< \brief (PIO_CODR) Clear Output Data */
    02224 #define PIO_CODR_P26 (0x1u << 26) /**< \brief (PIO_CODR) Clear Output Data */
    02225 #define PIO_CODR_P27 (0x1u << 27) /**< \brief (PIO_CODR) Clear Output Data */
    02226 #define PIO_CODR_P28 (0x1u << 28) /**< \brief (PIO_CODR) Clear Output Data */
    02227 #define PIO_CODR_P29 (0x1u << 29) /**< \brief (PIO_CODR) Clear Output Data */
    02228 #define PIO_CODR_P30 (0x1u << 30) /**< \brief (PIO_CODR) Clear Output Data */
    02229 #define PIO_CODR_P31 (0x1u << 31) /**< \brief (PIO_CODR) Clear Output Data */
    02230 /* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */
    02231 #define PIO_ODSR_P0 (0x1u << 0) /**< \brief (PIO_ODSR) Output Data Status */
    02232 #define PIO_ODSR_P1 (0x1u << 1) /**< \brief (PIO_ODSR) Output Data Status */
    02233 #define PIO_ODSR_P2 (0x1u << 2) /**< \brief (PIO_ODSR) Output Data Status */
    02234 #define PIO_ODSR_P3 (0x1u << 3) /**< \brief (PIO_ODSR) Output Data Status */
    02235 #define PIO_ODSR_P4 (0x1u << 4) /**< \brief (PIO_ODSR) Output Data Status */
    02236 #define PIO_ODSR_P5 (0x1u << 5) /**< \brief (PIO_ODSR) Output Data Status */
    02237 #define PIO_ODSR_P6 (0x1u << 6) /**< \brief (PIO_ODSR) Output Data Status */
    02238 #define PIO_ODSR_P7 (0x1u << 7) /**< \brief (PIO_ODSR) Output Data Status */
    02239 #define PIO_ODSR_P8 (0x1u << 8) /**< \brief (PIO_ODSR) Output Data Status */
    02240 #define PIO_ODSR_P9 (0x1u << 9) /**< \brief (PIO_ODSR) Output Data Status */
    02241 #define PIO_ODSR_P10 (0x1u << 10) /**< \brief (PIO_ODSR) Output Data Status */
    02242 #define PIO_ODSR_P11 (0x1u << 11) /**< \brief (PIO_ODSR) Output Data Status */
    02243 #define PIO_ODSR_P12 (0x1u << 12) /**< \brief (PIO_ODSR) Output Data Status */
    02244 #define PIO_ODSR_P13 (0x1u << 13) /**< \brief (PIO_ODSR) Output Data Status */
    02245 #define PIO_ODSR_P14 (0x1u << 14) /**< \brief (PIO_ODSR) Output Data Status */
    02246 #define PIO_ODSR_P15 (0x1u << 15) /**< \brief (PIO_ODSR) Output Data Status */
    02247 #define PIO_ODSR_P16 (0x1u << 16) /**< \brief (PIO_ODSR) Output Data Status */
    02248 #define PIO_ODSR_P17 (0x1u << 17) /**< \brief (PIO_ODSR) Output Data Status */
    02249 #define PIO_ODSR_P18 (0x1u << 18) /**< \brief (PIO_ODSR) Output Data Status */
    02250 #define PIO_ODSR_P19 (0x1u << 19) /**< \brief (PIO_ODSR) Output Data Status */
    02251 #define PIO_ODSR_P20 (0x1u << 20) /**< \brief (PIO_ODSR) Output Data Status */
    02252 #define PIO_ODSR_P21 (0x1u << 21) /**< \brief (PIO_ODSR) Output Data Status */
    02253 #define PIO_ODSR_P22 (0x1u << 22) /**< \brief (PIO_ODSR) Output Data Status */
    02254 #define PIO_ODSR_P23 (0x1u << 23) /**< \brief (PIO_ODSR) Output Data Status */
    02255 #define PIO_ODSR_P24 (0x1u << 24) /**< \brief (PIO_ODSR) Output Data Status */
    02256 #define PIO_ODSR_P25 (0x1u << 25) /**< \brief (PIO_ODSR) Output Data Status */
    02257 #define PIO_ODSR_P26 (0x1u << 26) /**< \brief (PIO_ODSR) Output Data Status */
    02258 #define PIO_ODSR_P27 (0x1u << 27) /**< \brief (PIO_ODSR) Output Data Status */
    02259 #define PIO_ODSR_P28 (0x1u << 28) /**< \brief (PIO_ODSR) Output Data Status */
    02260 #define PIO_ODSR_P29 (0x1u << 29) /**< \brief (PIO_ODSR) Output Data Status */
    02261 #define PIO_ODSR_P30 (0x1u << 30) /**< \brief (PIO_ODSR) Output Data Status */
    02262 #define PIO_ODSR_P31 (0x1u << 31) /**< \brief (PIO_ODSR) Output Data Status */
    02263 /* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */
    02264 #define PIO_PDSR_P0 (0x1u << 0) /**< \brief (PIO_PDSR) Output Data Status */
    02265 #define PIO_PDSR_P1 (0x1u << 1) /**< \brief (PIO_PDSR) Output Data Status */
    02266 #define PIO_PDSR_P2 (0x1u << 2) /**< \brief (PIO_PDSR) Output Data Status */
    02267 #define PIO_PDSR_P3 (0x1u << 3) /**< \brief (PIO_PDSR) Output Data Status */
    02268 #define PIO_PDSR_P4 (0x1u << 4) /**< \brief (PIO_PDSR) Output Data Status */
    02269 #define PIO_PDSR_P5 (0x1u << 5) /**< \brief (PIO_PDSR) Output Data Status */
    02270 #define PIO_PDSR_P6 (0x1u << 6) /**< \brief (PIO_PDSR) Output Data Status */
    02271 #define PIO_PDSR_P7 (0x1u << 7) /**< \brief (PIO_PDSR) Output Data Status */
    02272 #define PIO_PDSR_P8 (0x1u << 8) /**< \brief (PIO_PDSR) Output Data Status */
    02273 #define PIO_PDSR_P9 (0x1u << 9) /**< \brief (PIO_PDSR) Output Data Status */
    02274 #define PIO_PDSR_P10 (0x1u << 10) /**< \brief (PIO_PDSR) Output Data Status */
    02275 #define PIO_PDSR_P11 (0x1u << 11) /**< \brief (PIO_PDSR) Output Data Status */
    02276 #define PIO_PDSR_P12 (0x1u << 12) /**< \brief (PIO_PDSR) Output Data Status */
    02277 #define PIO_PDSR_P13 (0x1u << 13) /**< \brief (PIO_PDSR) Output Data Status */
    02278 #define PIO_PDSR_P14 (0x1u << 14) /**< \brief (PIO_PDSR) Output Data Status */
    02279 #define PIO_PDSR_P15 (0x1u << 15) /**< \brief (PIO_PDSR) Output Data Status */
    02280 #define PIO_PDSR_P16 (0x1u << 16) /**< \brief (PIO_PDSR) Output Data Status */
    02281 #define PIO_PDSR_P17 (0x1u << 17) /**< \brief (PIO_PDSR) Output Data Status */
    02282 #define PIO_PDSR_P18 (0x1u << 18) /**< \brief (PIO_PDSR) Output Data Status */
    02283 #define PIO_PDSR_P19 (0x1u << 19) /**< \brief (PIO_PDSR) Output Data Status */
    02284 #define PIO_PDSR_P20 (0x1u << 20) /**< \brief (PIO_PDSR) Output Data Status */
    02285 #define PIO_PDSR_P21 (0x1u << 21) /**< \brief (PIO_PDSR) Output Data Status */
    02286 #define PIO_PDSR_P22 (0x1u << 22) /**< \brief (PIO_PDSR) Output Data Status */
    02287 #define PIO_PDSR_P23 (0x1u << 23) /**< \brief (PIO_PDSR) Output Data Status */
    02288 #define PIO_PDSR_P24 (0x1u << 24) /**< \brief (PIO_PDSR) Output Data Status */
    02289 #define PIO_PDSR_P25 (0x1u << 25) /**< \brief (PIO_PDSR) Output Data Status */
    02290 #define PIO_PDSR_P26 (0x1u << 26) /**< \brief (PIO_PDSR) Output Data Status */
    02291 #define PIO_PDSR_P27 (0x1u << 27) /**< \brief (PIO_PDSR) Output Data Status */
    02292 #define PIO_PDSR_P28 (0x1u << 28) /**< \brief (PIO_PDSR) Output Data Status */
    02293 #define PIO_PDSR_P29 (0x1u << 29) /**< \brief (PIO_PDSR) Output Data Status */
    02294 #define PIO_PDSR_P30 (0x1u << 30) /**< \brief (PIO_PDSR) Output Data Status */
    02295 #define PIO_PDSR_P31 (0x1u << 31) /**< \brief (PIO_PDSR) Output Data Status */
    02296 /* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */
    02297 #define PIO_IER_P0 (0x1u << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */
    02298 #define PIO_IER_P1 (0x1u << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */
    02299 #define PIO_IER_P2 (0x1u << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */
    02300 #define PIO_IER_P3 (0x1u << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */
    02301 #define PIO_IER_P4 (0x1u << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */
    02302 #define PIO_IER_P5 (0x1u << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */
    02303 #define PIO_IER_P6 (0x1u << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */
    02304 #define PIO_IER_P7 (0x1u << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */
    02305 #define PIO_IER_P8 (0x1u << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */
    02306 #define PIO_IER_P9 (0x1u << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */
    02307 #define PIO_IER_P10 (0x1u << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */
    02308 #define PIO_IER_P11 (0x1u << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */
    02309 #define PIO_IER_P12 (0x1u << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */
    02310 #define PIO_IER_P13 (0x1u << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */
    02311 #define PIO_IER_P14 (0x1u << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */
    02312 #define PIO_IER_P15 (0x1u << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */
    02313 #define PIO_IER_P16 (0x1u << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */
    02314 #define PIO_IER_P17 (0x1u << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */
    02315 #define PIO_IER_P18 (0x1u << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */
    02316 #define PIO_IER_P19 (0x1u << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */
    02317 #define PIO_IER_P20 (0x1u << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */
    02318 #define PIO_IER_P21 (0x1u << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */
    02319 #define PIO_IER_P22 (0x1u << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */
    02320 #define PIO_IER_P23 (0x1u << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */
    02321 #define PIO_IER_P24 (0x1u << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */
    02322 #define PIO_IER_P25 (0x1u << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */
    02323 #define PIO_IER_P26 (0x1u << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */
    02324 #define PIO_IER_P27 (0x1u << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */
    02325 #define PIO_IER_P28 (0x1u << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */
    02326 #define PIO_IER_P29 (0x1u << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */
    02327 #define PIO_IER_P30 (0x1u << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */
    02328 #define PIO_IER_P31 (0x1u << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */
    02329 /* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */
    02330 #define PIO_IDR_P0 (0x1u << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
    02331 #define PIO_IDR_P1 (0x1u << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
    02332 #define PIO_IDR_P2 (0x1u << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
    02333 #define PIO_IDR_P3 (0x1u << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
    02334 #define PIO_IDR_P4 (0x1u << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
    02335 #define PIO_IDR_P5 (0x1u << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
    02336 #define PIO_IDR_P6 (0x1u << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
    02337 #define PIO_IDR_P7 (0x1u << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
    02338 #define PIO_IDR_P8 (0x1u << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
    02339 #define PIO_IDR_P9 (0x1u << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
    02340 #define PIO_IDR_P10 (0x1u << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
    02341 #define PIO_IDR_P11 (0x1u << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
    02342 #define PIO_IDR_P12 (0x1u << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
    02343 #define PIO_IDR_P13 (0x1u << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
    02344 #define PIO_IDR_P14 (0x1u << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
    02345 #define PIO_IDR_P15 (0x1u << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
    02346 #define PIO_IDR_P16 (0x1u << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
    02347 #define PIO_IDR_P17 (0x1u << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
    02348 #define PIO_IDR_P18 (0x1u << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
    02349 #define PIO_IDR_P19 (0x1u << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
    02350 #define PIO_IDR_P20 (0x1u << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
    02351 #define PIO_IDR_P21 (0x1u << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
    02352 #define PIO_IDR_P22 (0x1u << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
    02353 #define PIO_IDR_P23 (0x1u << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
    02354 #define PIO_IDR_P24 (0x1u << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
    02355 #define PIO_IDR_P25 (0x1u << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
    02356 #define PIO_IDR_P26 (0x1u << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
    02357 #define PIO_IDR_P27 (0x1u << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
    02358 #define PIO_IDR_P28 (0x1u << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
    02359 #define PIO_IDR_P29 (0x1u << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
    02360 #define PIO_IDR_P30 (0x1u << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
    02361 #define PIO_IDR_P31 (0x1u << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
    02362 /* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */
    02363 #define PIO_IMR_P0 (0x1u << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
    02364 #define PIO_IMR_P1 (0x1u << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
    02365 #define PIO_IMR_P2 (0x1u << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
    02366 #define PIO_IMR_P3 (0x1u << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
    02367 #define PIO_IMR_P4 (0x1u << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
    02368 #define PIO_IMR_P5 (0x1u << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
    02369 #define PIO_IMR_P6 (0x1u << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
    02370 #define PIO_IMR_P7 (0x1u << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
    02371 #define PIO_IMR_P8 (0x1u << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
    02372 #define PIO_IMR_P9 (0x1u << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
    02373 #define PIO_IMR_P10 (0x1u << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
    02374 #define PIO_IMR_P11 (0x1u << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
    02375 #define PIO_IMR_P12 (0x1u << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
    02376 #define PIO_IMR_P13 (0x1u << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
    02377 #define PIO_IMR_P14 (0x1u << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
    02378 #define PIO_IMR_P15 (0x1u << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
    02379 #define PIO_IMR_P16 (0x1u << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
    02380 #define PIO_IMR_P17 (0x1u << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
    02381 #define PIO_IMR_P18 (0x1u << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
    02382 #define PIO_IMR_P19 (0x1u << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
    02383 #define PIO_IMR_P20 (0x1u << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
    02384 #define PIO_IMR_P21 (0x1u << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
    02385 #define PIO_IMR_P22 (0x1u << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
    02386 #define PIO_IMR_P23 (0x1u << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
    02387 #define PIO_IMR_P24 (0x1u << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
    02388 #define PIO_IMR_P25 (0x1u << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
    02389 #define PIO_IMR_P26 (0x1u << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
    02390 #define PIO_IMR_P27 (0x1u << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
    02391 #define PIO_IMR_P28 (0x1u << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
    02392 #define PIO_IMR_P29 (0x1u << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
    02393 #define PIO_IMR_P30 (0x1u << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
    02394 #define PIO_IMR_P31 (0x1u << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
    02395 /* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */
    02396 #define PIO_ISR_P0 (0x1u << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */
    02397 #define PIO_ISR_P1 (0x1u << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */
    02398 #define PIO_ISR_P2 (0x1u << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */
    02399 #define PIO_ISR_P3 (0x1u << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */
    02400 #define PIO_ISR_P4 (0x1u << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */
    02401 #define PIO_ISR_P5 (0x1u << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */
    02402 #define PIO_ISR_P6 (0x1u << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */
    02403 #define PIO_ISR_P7 (0x1u << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */
    02404 #define PIO_ISR_P8 (0x1u << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */
    02405 #define PIO_ISR_P9 (0x1u << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */
    02406 #define PIO_ISR_P10 (0x1u << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */
    02407 #define PIO_ISR_P11 (0x1u << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */
    02408 #define PIO_ISR_P12 (0x1u << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */
    02409 #define PIO_ISR_P13 (0x1u << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */
    02410 #define PIO_ISR_P14 (0x1u << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */
    02411 #define PIO_ISR_P15 (0x1u << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */
    02412 #define PIO_ISR_P16 (0x1u << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */
    02413 #define PIO_ISR_P17 (0x1u << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */
    02414 #define PIO_ISR_P18 (0x1u << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */
    02415 #define PIO_ISR_P19 (0x1u << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */
    02416 #define PIO_ISR_P20 (0x1u << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */
    02417 #define PIO_ISR_P21 (0x1u << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */
    02418 #define PIO_ISR_P22 (0x1u << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */
    02419 #define PIO_ISR_P23 (0x1u << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */
    02420 #define PIO_ISR_P24 (0x1u << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */
    02421 #define PIO_ISR_P25 (0x1u << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */
    02422 #define PIO_ISR_P26 (0x1u << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */
    02423 #define PIO_ISR_P27 (0x1u << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */
    02424 #define PIO_ISR_P28 (0x1u << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */
    02425 #define PIO_ISR_P29 (0x1u << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */
    02426 #define PIO_ISR_P30 (0x1u << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */
    02427 #define PIO_ISR_P31 (0x1u << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */
    02428 /* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */
    02429 #define PIO_MDER_P0 (0x1u << 0) /**< \brief (PIO_MDER) Multi Drive Enable. */
    02430 #define PIO_MDER_P1 (0x1u << 1) /**< \brief (PIO_MDER) Multi Drive Enable. */
    02431 #define PIO_MDER_P2 (0x1u << 2) /**< \brief (PIO_MDER) Multi Drive Enable. */
    02432 #define PIO_MDER_P3 (0x1u << 3) /**< \brief (PIO_MDER) Multi Drive Enable. */
    02433 #define PIO_MDER_P4 (0x1u << 4) /**< \brief (PIO_MDER) Multi Drive Enable. */
    02434 #define PIO_MDER_P5 (0x1u << 5) /**< \brief (PIO_MDER) Multi Drive Enable. */
    02435 #define PIO_MDER_P6 (0x1u << 6) /**< \brief (PIO_MDER) Multi Drive Enable. */
    02436 #define PIO_MDER_P7 (0x1u << 7) /**< \brief (PIO_MDER) Multi Drive Enable. */
    02437 #define PIO_MDER_P8 (0x1u << 8) /**< \brief (PIO_MDER) Multi Drive Enable. */
    02438 #define PIO_MDER_P9 (0x1u << 9) /**< \brief (PIO_MDER) Multi Drive Enable. */
    02439 #define PIO_MDER_P10 (0x1u << 10) /**< \brief (PIO_MDER) Multi Drive Enable. */
    02440 #define PIO_MDER_P11 (0x1u << 11) /**< \brief (PIO_MDER) Multi Drive Enable. */
    02441 #define PIO_MDER_P12 (0x1u << 12) /**< \brief (PIO_MDER) Multi Drive Enable. */
    02442 #define PIO_MDER_P13 (0x1u << 13) /**< \brief (PIO_MDER) Multi Drive Enable. */
    02443 #define PIO_MDER_P14 (0x1u << 14) /**< \brief (PIO_MDER) Multi Drive Enable. */
    02444 #define PIO_MDER_P15 (0x1u << 15) /**< \brief (PIO_MDER) Multi Drive Enable. */
    02445 #define PIO_MDER_P16 (0x1u << 16) /**< \brief (PIO_MDER) Multi Drive Enable. */
    02446 #define PIO_MDER_P17 (0x1u << 17) /**< \brief (PIO_MDER) Multi Drive Enable. */
    02447 #define PIO_MDER_P18 (0x1u << 18) /**< \brief (PIO_MDER) Multi Drive Enable. */
    02448 #define PIO_MDER_P19 (0x1u << 19) /**< \brief (PIO_MDER) Multi Drive Enable. */
    02449 #define PIO_MDER_P20 (0x1u << 20) /**< \brief (PIO_MDER) Multi Drive Enable. */
    02450 #define PIO_MDER_P21 (0x1u << 21) /**< \brief (PIO_MDER) Multi Drive Enable. */
    02451 #define PIO_MDER_P22 (0x1u << 22) /**< \brief (PIO_MDER) Multi Drive Enable. */
    02452 #define PIO_MDER_P23 (0x1u << 23) /**< \brief (PIO_MDER) Multi Drive Enable. */
    02453 #define PIO_MDER_P24 (0x1u << 24) /**< \brief (PIO_MDER) Multi Drive Enable. */
    02454 #define PIO_MDER_P25 (0x1u << 25) /**< \brief (PIO_MDER) Multi Drive Enable. */
    02455 #define PIO_MDER_P26 (0x1u << 26) /**< \brief (PIO_MDER) Multi Drive Enable. */
    02456 #define PIO_MDER_P27 (0x1u << 27) /**< \brief (PIO_MDER) Multi Drive Enable. */
    02457 #define PIO_MDER_P28 (0x1u << 28) /**< \brief (PIO_MDER) Multi Drive Enable. */
    02458 #define PIO_MDER_P29 (0x1u << 29) /**< \brief (PIO_MDER) Multi Drive Enable. */
    02459 #define PIO_MDER_P30 (0x1u << 30) /**< \brief (PIO_MDER) Multi Drive Enable. */
    02460 #define PIO_MDER_P31 (0x1u << 31) /**< \brief (PIO_MDER) Multi Drive Enable. */
    02461 /* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */
    02462 #define PIO_MDDR_P0 (0x1u << 0) /**< \brief (PIO_MDDR) Multi Drive Disable. */
    02463 #define PIO_MDDR_P1 (0x1u << 1) /**< \brief (PIO_MDDR) Multi Drive Disable. */
    02464 #define PIO_MDDR_P2 (0x1u << 2) /**< \brief (PIO_MDDR) Multi Drive Disable. */
    02465 #define PIO_MDDR_P3 (0x1u << 3) /**< \brief (PIO_MDDR) Multi Drive Disable. */
    02466 #define PIO_MDDR_P4 (0x1u << 4) /**< \brief (PIO_MDDR) Multi Drive Disable. */
    02467 #define PIO_MDDR_P5 (0x1u << 5) /**< \brief (PIO_MDDR) Multi Drive Disable. */
    02468 #define PIO_MDDR_P6 (0x1u << 6) /**< \brief (PIO_MDDR) Multi Drive Disable. */
    02469 #define PIO_MDDR_P7 (0x1u << 7) /**< \brief (PIO_MDDR) Multi Drive Disable. */
    02470 #define PIO_MDDR_P8 (0x1u << 8) /**< \brief (PIO_MDDR) Multi Drive Disable. */
    02471 #define PIO_MDDR_P9 (0x1u << 9) /**< \brief (PIO_MDDR) Multi Drive Disable. */
    02472 #define PIO_MDDR_P10 (0x1u << 10) /**< \brief (PIO_MDDR) Multi Drive Disable. */
    02473 #define PIO_MDDR_P11 (0x1u << 11) /**< \brief (PIO_MDDR) Multi Drive Disable. */
    02474 #define PIO_MDDR_P12 (0x1u << 12) /**< \brief (PIO_MDDR) Multi Drive Disable. */
    02475 #define PIO_MDDR_P13 (0x1u << 13) /**< \brief (PIO_MDDR) Multi Drive Disable. */
    02476 #define PIO_MDDR_P14 (0x1u << 14) /**< \brief (PIO_MDDR) Multi Drive Disable. */
    02477 #define PIO_MDDR_P15 (0x1u << 15) /**< \brief (PIO_MDDR) Multi Drive Disable. */
    02478 #define PIO_MDDR_P16 (0x1u << 16) /**< \brief (PIO_MDDR) Multi Drive Disable. */
    02479 #define PIO_MDDR_P17 (0x1u << 17) /**< \brief (PIO_MDDR) Multi Drive Disable. */
    02480 #define PIO_MDDR_P18 (0x1u << 18) /**< \brief (PIO_MDDR) Multi Drive Disable. */
    02481 #define PIO_MDDR_P19 (0x1u << 19) /**< \brief (PIO_MDDR) Multi Drive Disable. */
    02482 #define PIO_MDDR_P20 (0x1u << 20) /**< \brief (PIO_MDDR) Multi Drive Disable. */
    02483 #define PIO_MDDR_P21 (0x1u << 21) /**< \brief (PIO_MDDR) Multi Drive Disable. */
    02484 #define PIO_MDDR_P22 (0x1u << 22) /**< \brief (PIO_MDDR) Multi Drive Disable. */
    02485 #define PIO_MDDR_P23 (0x1u << 23) /**< \brief (PIO_MDDR) Multi Drive Disable. */
    02486 #define PIO_MDDR_P24 (0x1u << 24) /**< \brief (PIO_MDDR) Multi Drive Disable. */
    02487 #define PIO_MDDR_P25 (0x1u << 25) /**< \brief (PIO_MDDR) Multi Drive Disable. */
    02488 #define PIO_MDDR_P26 (0x1u << 26) /**< \brief (PIO_MDDR) Multi Drive Disable. */
    02489 #define PIO_MDDR_P27 (0x1u << 27) /**< \brief (PIO_MDDR) Multi Drive Disable. */
    02490 #define PIO_MDDR_P28 (0x1u << 28) /**< \brief (PIO_MDDR) Multi Drive Disable. */
    02491 #define PIO_MDDR_P29 (0x1u << 29) /**< \brief (PIO_MDDR) Multi Drive Disable. */
    02492 #define PIO_MDDR_P30 (0x1u << 30) /**< \brief (PIO_MDDR) Multi Drive Disable. */
    02493 #define PIO_MDDR_P31 (0x1u << 31) /**< \brief (PIO_MDDR) Multi Drive Disable. */
    02494 /* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */
    02495 #define PIO_MDSR_P0 (0x1u << 0) /**< \brief (PIO_MDSR) Multi Drive Status. */
    02496 #define PIO_MDSR_P1 (0x1u << 1) /**< \brief (PIO_MDSR) Multi Drive Status. */
    02497 #define PIO_MDSR_P2 (0x1u << 2) /**< \brief (PIO_MDSR) Multi Drive Status. */
    02498 #define PIO_MDSR_P3 (0x1u << 3) /**< \brief (PIO_MDSR) Multi Drive Status. */
    02499 #define PIO_MDSR_P4 (0x1u << 4) /**< \brief (PIO_MDSR) Multi Drive Status. */
    02500 #define PIO_MDSR_P5 (0x1u << 5) /**< \brief (PIO_MDSR) Multi Drive Status. */
    02501 #define PIO_MDSR_P6 (0x1u << 6) /**< \brief (PIO_MDSR) Multi Drive Status. */
    02502 #define PIO_MDSR_P7 (0x1u << 7) /**< \brief (PIO_MDSR) Multi Drive Status. */
    02503 #define PIO_MDSR_P8 (0x1u << 8) /**< \brief (PIO_MDSR) Multi Drive Status. */
    02504 #define PIO_MDSR_P9 (0x1u << 9) /**< \brief (PIO_MDSR) Multi Drive Status. */
    02505 #define PIO_MDSR_P10 (0x1u << 10) /**< \brief (PIO_MDSR) Multi Drive Status. */
    02506 #define PIO_MDSR_P11 (0x1u << 11) /**< \brief (PIO_MDSR) Multi Drive Status. */
    02507 #define PIO_MDSR_P12 (0x1u << 12) /**< \brief (PIO_MDSR) Multi Drive Status. */
    02508 #define PIO_MDSR_P13 (0x1u << 13) /**< \brief (PIO_MDSR) Multi Drive Status. */
    02509 #define PIO_MDSR_P14 (0x1u << 14) /**< \brief (PIO_MDSR) Multi Drive Status. */
    02510 #define PIO_MDSR_P15 (0x1u << 15) /**< \brief (PIO_MDSR) Multi Drive Status. */
    02511 #define PIO_MDSR_P16 (0x1u << 16) /**< \brief (PIO_MDSR) Multi Drive Status. */
    02512 #define PIO_MDSR_P17 (0x1u << 17) /**< \brief (PIO_MDSR) Multi Drive Status. */
    02513 #define PIO_MDSR_P18 (0x1u << 18) /**< \brief (PIO_MDSR) Multi Drive Status. */
    02514 #define PIO_MDSR_P19 (0x1u << 19) /**< \brief (PIO_MDSR) Multi Drive Status. */
    02515 #define PIO_MDSR_P20 (0x1u << 20) /**< \brief (PIO_MDSR) Multi Drive Status. */
    02516 #define PIO_MDSR_P21 (0x1u << 21) /**< \brief (PIO_MDSR) Multi Drive Status. */
    02517 #define PIO_MDSR_P22 (0x1u << 22) /**< \brief (PIO_MDSR) Multi Drive Status. */
    02518 #define PIO_MDSR_P23 (0x1u << 23) /**< \brief (PIO_MDSR) Multi Drive Status. */
    02519 #define PIO_MDSR_P24 (0x1u << 24) /**< \brief (PIO_MDSR) Multi Drive Status. */
    02520 #define PIO_MDSR_P25 (0x1u << 25) /**< \brief (PIO_MDSR) Multi Drive Status. */
    02521 #define PIO_MDSR_P26 (0x1u << 26) /**< \brief (PIO_MDSR) Multi Drive Status. */
    02522 #define PIO_MDSR_P27 (0x1u << 27) /**< \brief (PIO_MDSR) Multi Drive Status. */
    02523 #define PIO_MDSR_P28 (0x1u << 28) /**< \brief (PIO_MDSR) Multi Drive Status. */
    02524 #define PIO_MDSR_P29 (0x1u << 29) /**< \brief (PIO_MDSR) Multi Drive Status. */
    02525 #define PIO_MDSR_P30 (0x1u << 30) /**< \brief (PIO_MDSR) Multi Drive Status. */
    02526 #define PIO_MDSR_P31 (0x1u << 31) /**< \brief (PIO_MDSR) Multi Drive Status. */
    02527 /* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */
    02528 #define PIO_PUDR_P0 (0x1u << 0) /**< \brief (PIO_PUDR) Pull Up Disable. */
    02529 #define PIO_PUDR_P1 (0x1u << 1) /**< \brief (PIO_PUDR) Pull Up Disable. */
    02530 #define PIO_PUDR_P2 (0x1u << 2) /**< \brief (PIO_PUDR) Pull Up Disable. */
    02531 #define PIO_PUDR_P3 (0x1u << 3) /**< \brief (PIO_PUDR) Pull Up Disable. */
    02532 #define PIO_PUDR_P4 (0x1u << 4) /**< \brief (PIO_PUDR) Pull Up Disable. */
    02533 #define PIO_PUDR_P5 (0x1u << 5) /**< \brief (PIO_PUDR) Pull Up Disable. */
    02534 #define PIO_PUDR_P6 (0x1u << 6) /**< \brief (PIO_PUDR) Pull Up Disable. */
    02535 #define PIO_PUDR_P7 (0x1u << 7) /**< \brief (PIO_PUDR) Pull Up Disable. */
    02536 #define PIO_PUDR_P8 (0x1u << 8) /**< \brief (PIO_PUDR) Pull Up Disable. */
    02537 #define PIO_PUDR_P9 (0x1u << 9) /**< \brief (PIO_PUDR) Pull Up Disable. */
    02538 #define PIO_PUDR_P10 (0x1u << 10) /**< \brief (PIO_PUDR) Pull Up Disable. */
    02539 #define PIO_PUDR_P11 (0x1u << 11) /**< \brief (PIO_PUDR) Pull Up Disable. */
    02540 #define PIO_PUDR_P12 (0x1u << 12) /**< \brief (PIO_PUDR) Pull Up Disable. */
    02541 #define PIO_PUDR_P13 (0x1u << 13) /**< \brief (PIO_PUDR) Pull Up Disable. */
    02542 #define PIO_PUDR_P14 (0x1u << 14) /**< \brief (PIO_PUDR) Pull Up Disable. */
    02543 #define PIO_PUDR_P15 (0x1u << 15) /**< \brief (PIO_PUDR) Pull Up Disable. */
    02544 #define PIO_PUDR_P16 (0x1u << 16) /**< \brief (PIO_PUDR) Pull Up Disable. */
    02545 #define PIO_PUDR_P17 (0x1u << 17) /**< \brief (PIO_PUDR) Pull Up Disable. */
    02546 #define PIO_PUDR_P18 (0x1u << 18) /**< \brief (PIO_PUDR) Pull Up Disable. */
    02547 #define PIO_PUDR_P19 (0x1u << 19) /**< \brief (PIO_PUDR) Pull Up Disable. */
    02548 #define PIO_PUDR_P20 (0x1u << 20) /**< \brief (PIO_PUDR) Pull Up Disable. */
    02549 #define PIO_PUDR_P21 (0x1u << 21) /**< \brief (PIO_PUDR) Pull Up Disable. */
    02550 #define PIO_PUDR_P22 (0x1u << 22) /**< \brief (PIO_PUDR) Pull Up Disable. */
    02551 #define PIO_PUDR_P23 (0x1u << 23) /**< \brief (PIO_PUDR) Pull Up Disable. */
    02552 #define PIO_PUDR_P24 (0x1u << 24) /**< \brief (PIO_PUDR) Pull Up Disable. */
    02553 #define PIO_PUDR_P25 (0x1u << 25) /**< \brief (PIO_PUDR) Pull Up Disable. */
    02554 #define PIO_PUDR_P26 (0x1u << 26) /**< \brief (PIO_PUDR) Pull Up Disable. */
    02555 #define PIO_PUDR_P27 (0x1u << 27) /**< \brief (PIO_PUDR) Pull Up Disable. */
    02556 #define PIO_PUDR_P28 (0x1u << 28) /**< \brief (PIO_PUDR) Pull Up Disable. */
    02557 #define PIO_PUDR_P29 (0x1u << 29) /**< \brief (PIO_PUDR) Pull Up Disable. */
    02558 #define PIO_PUDR_P30 (0x1u << 30) /**< \brief (PIO_PUDR) Pull Up Disable. */
    02559 #define PIO_PUDR_P31 (0x1u << 31) /**< \brief (PIO_PUDR) Pull Up Disable. */
    02560 /* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */
    02561 #define PIO_PUER_P0 (0x1u << 0) /**< \brief (PIO_PUER) Pull Up Enable. */
    02562 #define PIO_PUER_P1 (0x1u << 1) /**< \brief (PIO_PUER) Pull Up Enable. */
    02563 #define PIO_PUER_P2 (0x1u << 2) /**< \brief (PIO_PUER) Pull Up Enable. */
    02564 #define PIO_PUER_P3 (0x1u << 3) /**< \brief (PIO_PUER) Pull Up Enable. */
    02565 #define PIO_PUER_P4 (0x1u << 4) /**< \brief (PIO_PUER) Pull Up Enable. */
    02566 #define PIO_PUER_P5 (0x1u << 5) /**< \brief (PIO_PUER) Pull Up Enable. */
    02567 #define PIO_PUER_P6 (0x1u << 6) /**< \brief (PIO_PUER) Pull Up Enable. */
    02568 #define PIO_PUER_P7 (0x1u << 7) /**< \brief (PIO_PUER) Pull Up Enable. */
    02569 #define PIO_PUER_P8 (0x1u << 8) /**< \brief (PIO_PUER) Pull Up Enable. */
    02570 #define PIO_PUER_P9 (0x1u << 9) /**< \brief (PIO_PUER) Pull Up Enable. */
    02571 #define PIO_PUER_P10 (0x1u << 10) /**< \brief (PIO_PUER) Pull Up Enable. */
    02572 #define PIO_PUER_P11 (0x1u << 11) /**< \brief (PIO_PUER) Pull Up Enable. */
    02573 #define PIO_PUER_P12 (0x1u << 12) /**< \brief (PIO_PUER) Pull Up Enable. */
    02574 #define PIO_PUER_P13 (0x1u << 13) /**< \brief (PIO_PUER) Pull Up Enable. */
    02575 #define PIO_PUER_P14 (0x1u << 14) /**< \brief (PIO_PUER) Pull Up Enable. */
    02576 #define PIO_PUER_P15 (0x1u << 15) /**< \brief (PIO_PUER) Pull Up Enable. */
    02577 #define PIO_PUER_P16 (0x1u << 16) /**< \brief (PIO_PUER) Pull Up Enable. */
    02578 #define PIO_PUER_P17 (0x1u << 17) /**< \brief (PIO_PUER) Pull Up Enable. */
    02579 #define PIO_PUER_P18 (0x1u << 18) /**< \brief (PIO_PUER) Pull Up Enable. */
    02580 #define PIO_PUER_P19 (0x1u << 19) /**< \brief (PIO_PUER) Pull Up Enable. */
    02581 #define PIO_PUER_P20 (0x1u << 20) /**< \brief (PIO_PUER) Pull Up Enable. */
    02582 #define PIO_PUER_P21 (0x1u << 21) /**< \brief (PIO_PUER) Pull Up Enable. */
    02583 #define PIO_PUER_P22 (0x1u << 22) /**< \brief (PIO_PUER) Pull Up Enable. */
    02584 #define PIO_PUER_P23 (0x1u << 23) /**< \brief (PIO_PUER) Pull Up Enable. */
    02585 #define PIO_PUER_P24 (0x1u << 24) /**< \brief (PIO_PUER) Pull Up Enable. */
    02586 #define PIO_PUER_P25 (0x1u << 25) /**< \brief (PIO_PUER) Pull Up Enable. */
    02587 #define PIO_PUER_P26 (0x1u << 26) /**< \brief (PIO_PUER) Pull Up Enable. */
    02588 #define PIO_PUER_P27 (0x1u << 27) /**< \brief (PIO_PUER) Pull Up Enable. */
    02589 #define PIO_PUER_P28 (0x1u << 28) /**< \brief (PIO_PUER) Pull Up Enable. */
    02590 #define PIO_PUER_P29 (0x1u << 29) /**< \brief (PIO_PUER) Pull Up Enable. */
    02591 #define PIO_PUER_P30 (0x1u << 30) /**< \brief (PIO_PUER) Pull Up Enable. */
    02592 #define PIO_PUER_P31 (0x1u << 31) /**< \brief (PIO_PUER) Pull Up Enable. */
    02593 /* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */
    02594 #define PIO_PUSR_P0 (0x1u << 0) /**< \brief (PIO_PUSR) Pull Up Status. */
    02595 #define PIO_PUSR_P1 (0x1u << 1) /**< \brief (PIO_PUSR) Pull Up Status. */
    02596 #define PIO_PUSR_P2 (0x1u << 2) /**< \brief (PIO_PUSR) Pull Up Status. */
    02597 #define PIO_PUSR_P3 (0x1u << 3) /**< \brief (PIO_PUSR) Pull Up Status. */
    02598 #define PIO_PUSR_P4 (0x1u << 4) /**< \brief (PIO_PUSR) Pull Up Status. */
    02599 #define PIO_PUSR_P5 (0x1u << 5) /**< \brief (PIO_PUSR) Pull Up Status. */
    02600 #define PIO_PUSR_P6 (0x1u << 6) /**< \brief (PIO_PUSR) Pull Up Status. */
    02601 #define PIO_PUSR_P7 (0x1u << 7) /**< \brief (PIO_PUSR) Pull Up Status. */
    02602 #define PIO_PUSR_P8 (0x1u << 8) /**< \brief (PIO_PUSR) Pull Up Status. */
    02603 #define PIO_PUSR_P9 (0x1u << 9) /**< \brief (PIO_PUSR) Pull Up Status. */
    02604 #define PIO_PUSR_P10 (0x1u << 10) /**< \brief (PIO_PUSR) Pull Up Status. */
    02605 #define PIO_PUSR_P11 (0x1u << 11) /**< \brief (PIO_PUSR) Pull Up Status. */
    02606 #define PIO_PUSR_P12 (0x1u << 12) /**< \brief (PIO_PUSR) Pull Up Status. */
    02607 #define PIO_PUSR_P13 (0x1u << 13) /**< \brief (PIO_PUSR) Pull Up Status. */
    02608 #define PIO_PUSR_P14 (0x1u << 14) /**< \brief (PIO_PUSR) Pull Up Status. */
    02609 #define PIO_PUSR_P15 (0x1u << 15) /**< \brief (PIO_PUSR) Pull Up Status. */
    02610 #define PIO_PUSR_P16 (0x1u << 16) /**< \brief (PIO_PUSR) Pull Up Status. */
    02611 #define PIO_PUSR_P17 (0x1u << 17) /**< \brief (PIO_PUSR) Pull Up Status. */
    02612 #define PIO_PUSR_P18 (0x1u << 18) /**< \brief (PIO_PUSR) Pull Up Status. */
    02613 #define PIO_PUSR_P19 (0x1u << 19) /**< \brief (PIO_PUSR) Pull Up Status. */
    02614 #define PIO_PUSR_P20 (0x1u << 20) /**< \brief (PIO_PUSR) Pull Up Status. */
    02615 #define PIO_PUSR_P21 (0x1u << 21) /**< \brief (PIO_PUSR) Pull Up Status. */
    02616 #define PIO_PUSR_P22 (0x1u << 22) /**< \brief (PIO_PUSR) Pull Up Status. */
    02617 #define PIO_PUSR_P23 (0x1u << 23) /**< \brief (PIO_PUSR) Pull Up Status. */
    02618 #define PIO_PUSR_P24 (0x1u << 24) /**< \brief (PIO_PUSR) Pull Up Status. */
    02619 #define PIO_PUSR_P25 (0x1u << 25) /**< \brief (PIO_PUSR) Pull Up Status. */
    02620 #define PIO_PUSR_P26 (0x1u << 26) /**< \brief (PIO_PUSR) Pull Up Status. */
    02621 #define PIO_PUSR_P27 (0x1u << 27) /**< \brief (PIO_PUSR) Pull Up Status. */
    02622 #define PIO_PUSR_P28 (0x1u << 28) /**< \brief (PIO_PUSR) Pull Up Status. */
    02623 #define PIO_PUSR_P29 (0x1u << 29) /**< \brief (PIO_PUSR) Pull Up Status. */
    02624 #define PIO_PUSR_P30 (0x1u << 30) /**< \brief (PIO_PUSR) Pull Up Status. */
    02625 #define PIO_PUSR_P31 (0x1u << 31) /**< \brief (PIO_PUSR) Pull Up Status. */
    02626 /* -------- PIO_ABCDSR[2] : (PIO Offset: 0x0070) Peripheral Select Register -------- */
    02627 #define PIO_ABCDSR_P0 (0x1u << 0) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
    02628 #define PIO_ABCDSR_P1 (0x1u << 1) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
    02629 #define PIO_ABCDSR_P2 (0x1u << 2) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
    02630 #define PIO_ABCDSR_P3 (0x1u << 3) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
    02631 #define PIO_ABCDSR_P4 (0x1u << 4) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
    02632 #define PIO_ABCDSR_P5 (0x1u << 5) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
    02633 #define PIO_ABCDSR_P6 (0x1u << 6) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
    02634 #define PIO_ABCDSR_P7 (0x1u << 7) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
    02635 #define PIO_ABCDSR_P8 (0x1u << 8) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
    02636 #define PIO_ABCDSR_P9 (0x1u << 9) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
    02637 #define PIO_ABCDSR_P10 (0x1u << 10) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
    02638 #define PIO_ABCDSR_P11 (0x1u << 11) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
    02639 #define PIO_ABCDSR_P12 (0x1u << 12) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
    02640 #define PIO_ABCDSR_P13 (0x1u << 13) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
    02641 #define PIO_ABCDSR_P14 (0x1u << 14) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
    02642 #define PIO_ABCDSR_P15 (0x1u << 15) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
    02643 #define PIO_ABCDSR_P16 (0x1u << 16) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
    02644 #define PIO_ABCDSR_P17 (0x1u << 17) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
    02645 #define PIO_ABCDSR_P18 (0x1u << 18) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
    02646 #define PIO_ABCDSR_P19 (0x1u << 19) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
    02647 #define PIO_ABCDSR_P20 (0x1u << 20) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
    02648 #define PIO_ABCDSR_P21 (0x1u << 21) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
    02649 #define PIO_ABCDSR_P22 (0x1u << 22) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
    02650 #define PIO_ABCDSR_P23 (0x1u << 23) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
    02651 #define PIO_ABCDSR_P24 (0x1u << 24) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
    02652 #define PIO_ABCDSR_P25 (0x1u << 25) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
    02653 #define PIO_ABCDSR_P26 (0x1u << 26) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
    02654 #define PIO_ABCDSR_P27 (0x1u << 27) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
    02655 #define PIO_ABCDSR_P28 (0x1u << 28) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
    02656 #define PIO_ABCDSR_P29 (0x1u << 29) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
    02657 #define PIO_ABCDSR_P30 (0x1u << 30) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
    02658 #define PIO_ABCDSR_P31 (0x1u << 31) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
    02659 /* -------- PIO_IFSCDR : (PIO Offset: 0x0080) Input Filter Slow Clock Disable Register -------- */
    02660 #define PIO_IFSCDR_P0 (0x1u << 0) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
    02661 #define PIO_IFSCDR_P1 (0x1u << 1) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
    02662 #define PIO_IFSCDR_P2 (0x1u << 2) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
    02663 #define PIO_IFSCDR_P3 (0x1u << 3) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
    02664 #define PIO_IFSCDR_P4 (0x1u << 4) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
    02665 #define PIO_IFSCDR_P5 (0x1u << 5) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
    02666 #define PIO_IFSCDR_P6 (0x1u << 6) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
    02667 #define PIO_IFSCDR_P7 (0x1u << 7) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
    02668 #define PIO_IFSCDR_P8 (0x1u << 8) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
    02669 #define PIO_IFSCDR_P9 (0x1u << 9) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
    02670 #define PIO_IFSCDR_P10 (0x1u << 10) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
    02671 #define PIO_IFSCDR_P11 (0x1u << 11) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
    02672 #define PIO_IFSCDR_P12 (0x1u << 12) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
    02673 #define PIO_IFSCDR_P13 (0x1u << 13) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
    02674 #define PIO_IFSCDR_P14 (0x1u << 14) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
    02675 #define PIO_IFSCDR_P15 (0x1u << 15) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
    02676 #define PIO_IFSCDR_P16 (0x1u << 16) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
    02677 #define PIO_IFSCDR_P17 (0x1u << 17) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
    02678 #define PIO_IFSCDR_P18 (0x1u << 18) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
    02679 #define PIO_IFSCDR_P19 (0x1u << 19) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
    02680 #define PIO_IFSCDR_P20 (0x1u << 20) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
    02681 #define PIO_IFSCDR_P21 (0x1u << 21) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
    02682 #define PIO_IFSCDR_P22 (0x1u << 22) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
    02683 #define PIO_IFSCDR_P23 (0x1u << 23) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
    02684 #define PIO_IFSCDR_P24 (0x1u << 24) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
    02685 #define PIO_IFSCDR_P25 (0x1u << 25) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
    02686 #define PIO_IFSCDR_P26 (0x1u << 26) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
    02687 #define PIO_IFSCDR_P27 (0x1u << 27) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
    02688 #define PIO_IFSCDR_P28 (0x1u << 28) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
    02689 #define PIO_IFSCDR_P29 (0x1u << 29) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
    02690 #define PIO_IFSCDR_P30 (0x1u << 30) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
    02691 #define PIO_IFSCDR_P31 (0x1u << 31) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
    02692 /* -------- PIO_IFSCER : (PIO Offset: 0x0084) Input Filter Slow Clock Enable Register -------- */
    02693 #define PIO_IFSCER_P0 (0x1u << 0) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
    02694 #define PIO_IFSCER_P1 (0x1u << 1) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
    02695 #define PIO_IFSCER_P2 (0x1u << 2) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
    02696 #define PIO_IFSCER_P3 (0x1u << 3) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
    02697 #define PIO_IFSCER_P4 (0x1u << 4) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
    02698 #define PIO_IFSCER_P5 (0x1u << 5) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
    02699 #define PIO_IFSCER_P6 (0x1u << 6) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
    02700 #define PIO_IFSCER_P7 (0x1u << 7) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
    02701 #define PIO_IFSCER_P8 (0x1u << 8) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
    02702 #define PIO_IFSCER_P9 (0x1u << 9) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
    02703 #define PIO_IFSCER_P10 (0x1u << 10) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
    02704 #define PIO_IFSCER_P11 (0x1u << 11) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
    02705 #define PIO_IFSCER_P12 (0x1u << 12) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
    02706 #define PIO_IFSCER_P13 (0x1u << 13) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
    02707 #define PIO_IFSCER_P14 (0x1u << 14) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
    02708 #define PIO_IFSCER_P15 (0x1u << 15) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
    02709 #define PIO_IFSCER_P16 (0x1u << 16) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
    02710 #define PIO_IFSCER_P17 (0x1u << 17) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
    02711 #define PIO_IFSCER_P18 (0x1u << 18) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
    02712 #define PIO_IFSCER_P19 (0x1u << 19) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
    02713 #define PIO_IFSCER_P20 (0x1u << 20) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
    02714 #define PIO_IFSCER_P21 (0x1u << 21) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
    02715 #define PIO_IFSCER_P22 (0x1u << 22) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
    02716 #define PIO_IFSCER_P23 (0x1u << 23) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
    02717 #define PIO_IFSCER_P24 (0x1u << 24) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
    02718 #define PIO_IFSCER_P25 (0x1u << 25) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
    02719 #define PIO_IFSCER_P26 (0x1u << 26) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
    02720 #define PIO_IFSCER_P27 (0x1u << 27) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
    02721 #define PIO_IFSCER_P28 (0x1u << 28) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
    02722 #define PIO_IFSCER_P29 (0x1u << 29) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
    02723 #define PIO_IFSCER_P30 (0x1u << 30) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
    02724 #define PIO_IFSCER_P31 (0x1u << 31) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
    02725 /* -------- PIO_IFSCSR : (PIO Offset: 0x0088) Input Filter Slow Clock Status Register -------- */
    02726 #define PIO_IFSCSR_P0 (0x1u << 0) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
    02727 #define PIO_IFSCSR_P1 (0x1u << 1) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
    02728 #define PIO_IFSCSR_P2 (0x1u << 2) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
    02729 #define PIO_IFSCSR_P3 (0x1u << 3) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
    02730 #define PIO_IFSCSR_P4 (0x1u << 4) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
    02731 #define PIO_IFSCSR_P5 (0x1u << 5) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
    02732 #define PIO_IFSCSR_P6 (0x1u << 6) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
    02733 #define PIO_IFSCSR_P7 (0x1u << 7) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
    02734 #define PIO_IFSCSR_P8 (0x1u << 8) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
    02735 #define PIO_IFSCSR_P9 (0x1u << 9) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
    02736 #define PIO_IFSCSR_P10 (0x1u << 10) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
    02737 #define PIO_IFSCSR_P11 (0x1u << 11) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
    02738 #define PIO_IFSCSR_P12 (0x1u << 12) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
    02739 #define PIO_IFSCSR_P13 (0x1u << 13) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
    02740 #define PIO_IFSCSR_P14 (0x1u << 14) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
    02741 #define PIO_IFSCSR_P15 (0x1u << 15) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
    02742 #define PIO_IFSCSR_P16 (0x1u << 16) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
    02743 #define PIO_IFSCSR_P17 (0x1u << 17) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
    02744 #define PIO_IFSCSR_P18 (0x1u << 18) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
    02745 #define PIO_IFSCSR_P19 (0x1u << 19) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
    02746 #define PIO_IFSCSR_P20 (0x1u << 20) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
    02747 #define PIO_IFSCSR_P21 (0x1u << 21) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
    02748 #define PIO_IFSCSR_P22 (0x1u << 22) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
    02749 #define PIO_IFSCSR_P23 (0x1u << 23) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
    02750 #define PIO_IFSCSR_P24 (0x1u << 24) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
    02751 #define PIO_IFSCSR_P25 (0x1u << 25) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
    02752 #define PIO_IFSCSR_P26 (0x1u << 26) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
    02753 #define PIO_IFSCSR_P27 (0x1u << 27) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
    02754 #define PIO_IFSCSR_P28 (0x1u << 28) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
    02755 #define PIO_IFSCSR_P29 (0x1u << 29) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
    02756 #define PIO_IFSCSR_P30 (0x1u << 30) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
    02757 #define PIO_IFSCSR_P31 (0x1u << 31) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
    02758 /* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */
    02759 #define PIO_SCDR_DIV_Pos 0
    02760 #define PIO_SCDR_DIV_Msk (0x3fffu << PIO_SCDR_DIV_Pos) /**< \brief (PIO_SCDR)  */
    02761 #define PIO_SCDR_DIV(value) ((PIO_SCDR_DIV_Msk & ((value) << PIO_SCDR_DIV_Pos)))
    02762 /* -------- PIO_PPDDR : (PIO Offset: 0x0090) Pad Pull-down Disable Register -------- */
    02763 #define PIO_PPDDR_P0 (0x1u << 0) /**< \brief (PIO_PPDDR) Pull Down Disable. */
    02764 #define PIO_PPDDR_P1 (0x1u << 1) /**< \brief (PIO_PPDDR) Pull Down Disable. */
    02765 #define PIO_PPDDR_P2 (0x1u << 2) /**< \brief (PIO_PPDDR) Pull Down Disable. */
    02766 #define PIO_PPDDR_P3 (0x1u << 3) /**< \brief (PIO_PPDDR) Pull Down Disable. */
    02767 #define PIO_PPDDR_P4 (0x1u << 4) /**< \brief (PIO_PPDDR) Pull Down Disable. */
    02768 #define PIO_PPDDR_P5 (0x1u << 5) /**< \brief (PIO_PPDDR) Pull Down Disable. */
    02769 #define PIO_PPDDR_P6 (0x1u << 6) /**< \brief (PIO_PPDDR) Pull Down Disable. */
    02770 #define PIO_PPDDR_P7 (0x1u << 7) /**< \brief (PIO_PPDDR) Pull Down Disable. */
    02771 #define PIO_PPDDR_P8 (0x1u << 8) /**< \brief (PIO_PPDDR) Pull Down Disable. */
    02772 #define PIO_PPDDR_P9 (0x1u << 9) /**< \brief (PIO_PPDDR) Pull Down Disable. */
    02773 #define PIO_PPDDR_P10 (0x1u << 10) /**< \brief (PIO_PPDDR) Pull Down Disable. */
    02774 #define PIO_PPDDR_P11 (0x1u << 11) /**< \brief (PIO_PPDDR) Pull Down Disable. */
    02775 #define PIO_PPDDR_P12 (0x1u << 12) /**< \brief (PIO_PPDDR) Pull Down Disable. */
    02776 #define PIO_PPDDR_P13 (0x1u << 13) /**< \brief (PIO_PPDDR) Pull Down Disable. */
    02777 #define PIO_PPDDR_P14 (0x1u << 14) /**< \brief (PIO_PPDDR) Pull Down Disable. */
    02778 #define PIO_PPDDR_P15 (0x1u << 15) /**< \brief (PIO_PPDDR) Pull Down Disable. */
    02779 #define PIO_PPDDR_P16 (0x1u << 16) /**< \brief (PIO_PPDDR) Pull Down Disable. */
    02780 #define PIO_PPDDR_P17 (0x1u << 17) /**< \brief (PIO_PPDDR) Pull Down Disable. */
    02781 #define PIO_PPDDR_P18 (0x1u << 18) /**< \brief (PIO_PPDDR) Pull Down Disable. */
    02782 #define PIO_PPDDR_P19 (0x1u << 19) /**< \brief (PIO_PPDDR) Pull Down Disable. */
    02783 #define PIO_PPDDR_P20 (0x1u << 20) /**< \brief (PIO_PPDDR) Pull Down Disable. */
    02784 #define PIO_PPDDR_P21 (0x1u << 21) /**< \brief (PIO_PPDDR) Pull Down Disable. */
    02785 #define PIO_PPDDR_P22 (0x1u << 22) /**< \brief (PIO_PPDDR) Pull Down Disable. */
    02786 #define PIO_PPDDR_P23 (0x1u << 23) /**< \brief (PIO_PPDDR) Pull Down Disable. */
    02787 #define PIO_PPDDR_P24 (0x1u << 24) /**< \brief (PIO_PPDDR) Pull Down Disable. */
    02788 #define PIO_PPDDR_P25 (0x1u << 25) /**< \brief (PIO_PPDDR) Pull Down Disable. */
    02789 #define PIO_PPDDR_P26 (0x1u << 26) /**< \brief (PIO_PPDDR) Pull Down Disable. */
    02790 #define PIO_PPDDR_P27 (0x1u << 27) /**< \brief (PIO_PPDDR) Pull Down Disable. */
    02791 #define PIO_PPDDR_P28 (0x1u << 28) /**< \brief (PIO_PPDDR) Pull Down Disable. */
    02792 #define PIO_PPDDR_P29 (0x1u << 29) /**< \brief (PIO_PPDDR) Pull Down Disable. */
    02793 #define PIO_PPDDR_P30 (0x1u << 30) /**< \brief (PIO_PPDDR) Pull Down Disable. */
    02794 #define PIO_PPDDR_P31 (0x1u << 31) /**< \brief (PIO_PPDDR) Pull Down Disable. */
    02795 /* -------- PIO_PPDER : (PIO Offset: 0x0094) Pad Pull-down Enable Register -------- */
    02796 #define PIO_PPDER_P0 (0x1u << 0) /**< \brief (PIO_PPDER) Pull Down Enable. */
    02797 #define PIO_PPDER_P1 (0x1u << 1) /**< \brief (PIO_PPDER) Pull Down Enable. */
    02798 #define PIO_PPDER_P2 (0x1u << 2) /**< \brief (PIO_PPDER) Pull Down Enable. */
    02799 #define PIO_PPDER_P3 (0x1u << 3) /**< \brief (PIO_PPDER) Pull Down Enable. */
    02800 #define PIO_PPDER_P4 (0x1u << 4) /**< \brief (PIO_PPDER) Pull Down Enable. */
    02801 #define PIO_PPDER_P5 (0x1u << 5) /**< \brief (PIO_PPDER) Pull Down Enable. */
    02802 #define PIO_PPDER_P6 (0x1u << 6) /**< \brief (PIO_PPDER) Pull Down Enable. */
    02803 #define PIO_PPDER_P7 (0x1u << 7) /**< \brief (PIO_PPDER) Pull Down Enable. */
    02804 #define PIO_PPDER_P8 (0x1u << 8) /**< \brief (PIO_PPDER) Pull Down Enable. */
    02805 #define PIO_PPDER_P9 (0x1u << 9) /**< \brief (PIO_PPDER) Pull Down Enable. */
    02806 #define PIO_PPDER_P10 (0x1u << 10) /**< \brief (PIO_PPDER) Pull Down Enable. */
    02807 #define PIO_PPDER_P11 (0x1u << 11) /**< \brief (PIO_PPDER) Pull Down Enable. */
    02808 #define PIO_PPDER_P12 (0x1u << 12) /**< \brief (PIO_PPDER) Pull Down Enable. */
    02809 #define PIO_PPDER_P13 (0x1u << 13) /**< \brief (PIO_PPDER) Pull Down Enable. */
    02810 #define PIO_PPDER_P14 (0x1u << 14) /**< \brief (PIO_PPDER) Pull Down Enable. */
    02811 #define PIO_PPDER_P15 (0x1u << 15) /**< \brief (PIO_PPDER) Pull Down Enable. */
    02812 #define PIO_PPDER_P16 (0x1u << 16) /**< \brief (PIO_PPDER) Pull Down Enable. */
    02813 #define PIO_PPDER_P17 (0x1u << 17) /**< \brief (PIO_PPDER) Pull Down Enable. */
    02814 #define PIO_PPDER_P18 (0x1u << 18) /**< \brief (PIO_PPDER) Pull Down Enable. */
    02815 #define PIO_PPDER_P19 (0x1u << 19) /**< \brief (PIO_PPDER) Pull Down Enable. */
    02816 #define PIO_PPDER_P20 (0x1u << 20) /**< \brief (PIO_PPDER) Pull Down Enable. */
    02817 #define PIO_PPDER_P21 (0x1u << 21) /**< \brief (PIO_PPDER) Pull Down Enable. */
    02818 #define PIO_PPDER_P22 (0x1u << 22) /**< \brief (PIO_PPDER) Pull Down Enable. */
    02819 #define PIO_PPDER_P23 (0x1u << 23) /**< \brief (PIO_PPDER) Pull Down Enable. */
    02820 #define PIO_PPDER_P24 (0x1u << 24) /**< \brief (PIO_PPDER) Pull Down Enable. */
    02821 #define PIO_PPDER_P25 (0x1u << 25) /**< \brief (PIO_PPDER) Pull Down Enable. */
    02822 #define PIO_PPDER_P26 (0x1u << 26) /**< \brief (PIO_PPDER) Pull Down Enable. */
    02823 #define PIO_PPDER_P27 (0x1u << 27) /**< \brief (PIO_PPDER) Pull Down Enable. */
    02824 #define PIO_PPDER_P28 (0x1u << 28) /**< \brief (PIO_PPDER) Pull Down Enable. */
    02825 #define PIO_PPDER_P29 (0x1u << 29) /**< \brief (PIO_PPDER) Pull Down Enable. */
    02826 #define PIO_PPDER_P30 (0x1u << 30) /**< \brief (PIO_PPDER) Pull Down Enable. */
    02827 #define PIO_PPDER_P31 (0x1u << 31) /**< \brief (PIO_PPDER) Pull Down Enable. */
    02828 /* -------- PIO_PPDSR : (PIO Offset: 0x0098) Pad Pull-down Status Register -------- */
    02829 #define PIO_PPDSR_P0 (0x1u << 0) /**< \brief (PIO_PPDSR) Pull Down Status. */
    02830 #define PIO_PPDSR_P1 (0x1u << 1) /**< \brief (PIO_PPDSR) Pull Down Status. */
    02831 #define PIO_PPDSR_P2 (0x1u << 2) /**< \brief (PIO_PPDSR) Pull Down Status. */
    02832 #define PIO_PPDSR_P3 (0x1u << 3) /**< \brief (PIO_PPDSR) Pull Down Status. */
    02833 #define PIO_PPDSR_P4 (0x1u << 4) /**< \brief (PIO_PPDSR) Pull Down Status. */
    02834 #define PIO_PPDSR_P5 (0x1u << 5) /**< \brief (PIO_PPDSR) Pull Down Status. */
    02835 #define PIO_PPDSR_P6 (0x1u << 6) /**< \brief (PIO_PPDSR) Pull Down Status. */
    02836 #define PIO_PPDSR_P7 (0x1u << 7) /**< \brief (PIO_PPDSR) Pull Down Status. */
    02837 #define PIO_PPDSR_P8 (0x1u << 8) /**< \brief (PIO_PPDSR) Pull Down Status. */
    02838 #define PIO_PPDSR_P9 (0x1u << 9) /**< \brief (PIO_PPDSR) Pull Down Status. */
    02839 #define PIO_PPDSR_P10 (0x1u << 10) /**< \brief (PIO_PPDSR) Pull Down Status. */
    02840 #define PIO_PPDSR_P11 (0x1u << 11) /**< \brief (PIO_PPDSR) Pull Down Status. */
    02841 #define PIO_PPDSR_P12 (0x1u << 12) /**< \brief (PIO_PPDSR) Pull Down Status. */
    02842 #define PIO_PPDSR_P13 (0x1u << 13) /**< \brief (PIO_PPDSR) Pull Down Status. */
    02843 #define PIO_PPDSR_P14 (0x1u << 14) /**< \brief (PIO_PPDSR) Pull Down Status. */
    02844 #define PIO_PPDSR_P15 (0x1u << 15) /**< \brief (PIO_PPDSR) Pull Down Status. */
    02845 #define PIO_PPDSR_P16 (0x1u << 16) /**< \brief (PIO_PPDSR) Pull Down Status. */
    02846 #define PIO_PPDSR_P17 (0x1u << 17) /**< \brief (PIO_PPDSR) Pull Down Status. */
    02847 #define PIO_PPDSR_P18 (0x1u << 18) /**< \brief (PIO_PPDSR) Pull Down Status. */
    02848 #define PIO_PPDSR_P19 (0x1u << 19) /**< \brief (PIO_PPDSR) Pull Down Status. */
    02849 #define PIO_PPDSR_P20 (0x1u << 20) /**< \brief (PIO_PPDSR) Pull Down Status. */
    02850 #define PIO_PPDSR_P21 (0x1u << 21) /**< \brief (PIO_PPDSR) Pull Down Status. */
    02851 #define PIO_PPDSR_P22 (0x1u << 22) /**< \brief (PIO_PPDSR) Pull Down Status. */
    02852 #define PIO_PPDSR_P23 (0x1u << 23) /**< \brief (PIO_PPDSR) Pull Down Status. */
    02853 #define PIO_PPDSR_P24 (0x1u << 24) /**< \brief (PIO_PPDSR) Pull Down Status. */
    02854 #define PIO_PPDSR_P25 (0x1u << 25) /**< \brief (PIO_PPDSR) Pull Down Status. */
    02855 #define PIO_PPDSR_P26 (0x1u << 26) /**< \brief (PIO_PPDSR) Pull Down Status. */
    02856 #define PIO_PPDSR_P27 (0x1u << 27) /**< \brief (PIO_PPDSR) Pull Down Status. */
    02857 #define PIO_PPDSR_P28 (0x1u << 28) /**< \brief (PIO_PPDSR) Pull Down Status. */
    02858 #define PIO_PPDSR_P29 (0x1u << 29) /**< \brief (PIO_PPDSR) Pull Down Status. */
    02859 #define PIO_PPDSR_P30 (0x1u << 30) /**< \brief (PIO_PPDSR) Pull Down Status. */
    02860 #define PIO_PPDSR_P31 (0x1u << 31) /**< \brief (PIO_PPDSR) Pull Down Status. */
    02861 /* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */
    02862 #define PIO_OWER_P0 (0x1u << 0) /**< \brief (PIO_OWER) Output Write Enable. */
    02863 #define PIO_OWER_P1 (0x1u << 1) /**< \brief (PIO_OWER) Output Write Enable. */
    02864 #define PIO_OWER_P2 (0x1u << 2) /**< \brief (PIO_OWER) Output Write Enable. */
    02865 #define PIO_OWER_P3 (0x1u << 3) /**< \brief (PIO_OWER) Output Write Enable. */
    02866 #define PIO_OWER_P4 (0x1u << 4) /**< \brief (PIO_OWER) Output Write Enable. */
    02867 #define PIO_OWER_P5 (0x1u << 5) /**< \brief (PIO_OWER) Output Write Enable. */
    02868 #define PIO_OWER_P6 (0x1u << 6) /**< \brief (PIO_OWER) Output Write Enable. */
    02869 #define PIO_OWER_P7 (0x1u << 7) /**< \brief (PIO_OWER) Output Write Enable. */
    02870 #define PIO_OWER_P8 (0x1u << 8) /**< \brief (PIO_OWER) Output Write Enable. */
    02871 #define PIO_OWER_P9 (0x1u << 9) /**< \brief (PIO_OWER) Output Write Enable. */
    02872 #define PIO_OWER_P10 (0x1u << 10) /**< \brief (PIO_OWER) Output Write Enable. */
    02873 #define PIO_OWER_P11 (0x1u << 11) /**< \brief (PIO_OWER) Output Write Enable. */
    02874 #define PIO_OWER_P12 (0x1u << 12) /**< \brief (PIO_OWER) Output Write Enable. */
    02875 #define PIO_OWER_P13 (0x1u << 13) /**< \brief (PIO_OWER) Output Write Enable. */
    02876 #define PIO_OWER_P14 (0x1u << 14) /**< \brief (PIO_OWER) Output Write Enable. */
    02877 #define PIO_OWER_P15 (0x1u << 15) /**< \brief (PIO_OWER) Output Write Enable. */
    02878 #define PIO_OWER_P16 (0x1u << 16) /**< \brief (PIO_OWER) Output Write Enable. */
    02879 #define PIO_OWER_P17 (0x1u << 17) /**< \brief (PIO_OWER) Output Write Enable. */
    02880 #define PIO_OWER_P18 (0x1u << 18) /**< \brief (PIO_OWER) Output Write Enable. */
    02881 #define PIO_OWER_P19 (0x1u << 19) /**< \brief (PIO_OWER) Output Write Enable. */
    02882 #define PIO_OWER_P20 (0x1u << 20) /**< \brief (PIO_OWER) Output Write Enable. */
    02883 #define PIO_OWER_P21 (0x1u << 21) /**< \brief (PIO_OWER) Output Write Enable. */
    02884 #define PIO_OWER_P22 (0x1u << 22) /**< \brief (PIO_OWER) Output Write Enable. */
    02885 #define PIO_OWER_P23 (0x1u << 23) /**< \brief (PIO_OWER) Output Write Enable. */
    02886 #define PIO_OWER_P24 (0x1u << 24) /**< \brief (PIO_OWER) Output Write Enable. */
    02887 #define PIO_OWER_P25 (0x1u << 25) /**< \brief (PIO_OWER) Output Write Enable. */
    02888 #define PIO_OWER_P26 (0x1u << 26) /**< \brief (PIO_OWER) Output Write Enable. */
    02889 #define PIO_OWER_P27 (0x1u << 27) /**< \brief (PIO_OWER) Output Write Enable. */
    02890 #define PIO_OWER_P28 (0x1u << 28) /**< \brief (PIO_OWER) Output Write Enable. */
    02891 #define PIO_OWER_P29 (0x1u << 29) /**< \brief (PIO_OWER) Output Write Enable. */
    02892 #define PIO_OWER_P30 (0x1u << 30) /**< \brief (PIO_OWER) Output Write Enable. */
    02893 #define PIO_OWER_P31 (0x1u << 31) /**< \brief (PIO_OWER) Output Write Enable. */
    02894 /* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */
    02895 #define PIO_OWDR_P0 (0x1u << 0) /**< \brief (PIO_OWDR) Output Write Disable. */
    02896 #define PIO_OWDR_P1 (0x1u << 1) /**< \brief (PIO_OWDR) Output Write Disable. */
    02897 #define PIO_OWDR_P2 (0x1u << 2) /**< \brief (PIO_OWDR) Output Write Disable. */
    02898 #define PIO_OWDR_P3 (0x1u << 3) /**< \brief (PIO_OWDR) Output Write Disable. */
    02899 #define PIO_OWDR_P4 (0x1u << 4) /**< \brief (PIO_OWDR) Output Write Disable. */
    02900 #define PIO_OWDR_P5 (0x1u << 5) /**< \brief (PIO_OWDR) Output Write Disable. */
    02901 #define PIO_OWDR_P6 (0x1u << 6) /**< \brief (PIO_OWDR) Output Write Disable. */
    02902 #define PIO_OWDR_P7 (0x1u << 7) /**< \brief (PIO_OWDR) Output Write Disable. */
    02903 #define PIO_OWDR_P8 (0x1u << 8) /**< \brief (PIO_OWDR) Output Write Disable. */
    02904 #define PIO_OWDR_P9 (0x1u << 9) /**< \brief (PIO_OWDR) Output Write Disable. */
    02905 #define PIO_OWDR_P10 (0x1u << 10) /**< \brief (PIO_OWDR) Output Write Disable. */
    02906 #define PIO_OWDR_P11 (0x1u << 11) /**< \brief (PIO_OWDR) Output Write Disable. */
    02907 #define PIO_OWDR_P12 (0x1u << 12) /**< \brief (PIO_OWDR) Output Write Disable. */
    02908 #define PIO_OWDR_P13 (0x1u << 13) /**< \brief (PIO_OWDR) Output Write Disable. */
    02909 #define PIO_OWDR_P14 (0x1u << 14) /**< \brief (PIO_OWDR) Output Write Disable. */
    02910 #define PIO_OWDR_P15 (0x1u << 15) /**< \brief (PIO_OWDR) Output Write Disable. */
    02911 #define PIO_OWDR_P16 (0x1u << 16) /**< \brief (PIO_OWDR) Output Write Disable. */
    02912 #define PIO_OWDR_P17 (0x1u << 17) /**< \brief (PIO_OWDR) Output Write Disable. */
    02913 #define PIO_OWDR_P18 (0x1u << 18) /**< \brief (PIO_OWDR) Output Write Disable. */
    02914 #define PIO_OWDR_P19 (0x1u << 19) /**< \brief (PIO_OWDR) Output Write Disable. */
    02915 #define PIO_OWDR_P20 (0x1u << 20) /**< \brief (PIO_OWDR) Output Write Disable. */
    02916 #define PIO_OWDR_P21 (0x1u << 21) /**< \brief (PIO_OWDR) Output Write Disable. */
    02917 #define PIO_OWDR_P22 (0x1u << 22) /**< \brief (PIO_OWDR) Output Write Disable. */
    02918 #define PIO_OWDR_P23 (0x1u << 23) /**< \brief (PIO_OWDR) Output Write Disable. */
    02919 #define PIO_OWDR_P24 (0x1u << 24) /**< \brief (PIO_OWDR) Output Write Disable. */
    02920 #define PIO_OWDR_P25 (0x1u << 25) /**< \brief (PIO_OWDR) Output Write Disable. */
    02921 #define PIO_OWDR_P26 (0x1u << 26) /**< \brief (PIO_OWDR) Output Write Disable. */
    02922 #define PIO_OWDR_P27 (0x1u << 27) /**< \brief (PIO_OWDR) Output Write Disable. */
    02923 #define PIO_OWDR_P28 (0x1u << 28) /**< \brief (PIO_OWDR) Output Write Disable. */
    02924 #define PIO_OWDR_P29 (0x1u << 29) /**< \brief (PIO_OWDR) Output Write Disable. */
    02925 #define PIO_OWDR_P30 (0x1u << 30) /**< \brief (PIO_OWDR) Output Write Disable. */
    02926 #define PIO_OWDR_P31 (0x1u << 31) /**< \brief (PIO_OWDR) Output Write Disable. */
    02927 /* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */
    02928 #define PIO_OWSR_P0 (0x1u << 0) /**< \brief (PIO_OWSR) Output Write Status. */
    02929 #define PIO_OWSR_P1 (0x1u << 1) /**< \brief (PIO_OWSR) Output Write Status. */
    02930 #define PIO_OWSR_P2 (0x1u << 2) /**< \brief (PIO_OWSR) Output Write Status. */
    02931 #define PIO_OWSR_P3 (0x1u << 3) /**< \brief (PIO_OWSR) Output Write Status. */
    02932 #define PIO_OWSR_P4 (0x1u << 4) /**< \brief (PIO_OWSR) Output Write Status. */
    02933 #define PIO_OWSR_P5 (0x1u << 5) /**< \brief (PIO_OWSR) Output Write Status. */
    02934 #define PIO_OWSR_P6 (0x1u << 6) /**< \brief (PIO_OWSR) Output Write Status. */
    02935 #define PIO_OWSR_P7 (0x1u << 7) /**< \brief (PIO_OWSR) Output Write Status. */
    02936 #define PIO_OWSR_P8 (0x1u << 8) /**< \brief (PIO_OWSR) Output Write Status. */
    02937 #define PIO_OWSR_P9 (0x1u << 9) /**< \brief (PIO_OWSR) Output Write Status. */
    02938 #define PIO_OWSR_P10 (0x1u << 10) /**< \brief (PIO_OWSR) Output Write Status. */
    02939 #define PIO_OWSR_P11 (0x1u << 11) /**< \brief (PIO_OWSR) Output Write Status. */
    02940 #define PIO_OWSR_P12 (0x1u << 12) /**< \brief (PIO_OWSR) Output Write Status. */
    02941 #define PIO_OWSR_P13 (0x1u << 13) /**< \brief (PIO_OWSR) Output Write Status. */
    02942 #define PIO_OWSR_P14 (0x1u << 14) /**< \brief (PIO_OWSR) Output Write Status. */
    02943 #define PIO_OWSR_P15 (0x1u << 15) /**< \brief (PIO_OWSR) Output Write Status. */
    02944 #define PIO_OWSR_P16 (0x1u << 16) /**< \brief (PIO_OWSR) Output Write Status. */
    02945 #define PIO_OWSR_P17 (0x1u << 17) /**< \brief (PIO_OWSR) Output Write Status. */
    02946 #define PIO_OWSR_P18 (0x1u << 18) /**< \brief (PIO_OWSR) Output Write Status. */
    02947 #define PIO_OWSR_P19 (0x1u << 19) /**< \brief (PIO_OWSR) Output Write Status. */
    02948 #define PIO_OWSR_P20 (0x1u << 20) /**< \brief (PIO_OWSR) Output Write Status. */
    02949 #define PIO_OWSR_P21 (0x1u << 21) /**< \brief (PIO_OWSR) Output Write Status. */
    02950 #define PIO_OWSR_P22 (0x1u << 22) /**< \brief (PIO_OWSR) Output Write Status. */
    02951 #define PIO_OWSR_P23 (0x1u << 23) /**< \brief (PIO_OWSR) Output Write Status. */
    02952 #define PIO_OWSR_P24 (0x1u << 24) /**< \brief (PIO_OWSR) Output Write Status. */
    02953 #define PIO_OWSR_P25 (0x1u << 25) /**< \brief (PIO_OWSR) Output Write Status. */
    02954 #define PIO_OWSR_P26 (0x1u << 26) /**< \brief (PIO_OWSR) Output Write Status. */
    02955 #define PIO_OWSR_P27 (0x1u << 27) /**< \brief (PIO_OWSR) Output Write Status. */
    02956 #define PIO_OWSR_P28 (0x1u << 28) /**< \brief (PIO_OWSR) Output Write Status. */
    02957 #define PIO_OWSR_P29 (0x1u << 29) /**< \brief (PIO_OWSR) Output Write Status. */
    02958 #define PIO_OWSR_P30 (0x1u << 30) /**< \brief (PIO_OWSR) Output Write Status. */
    02959 #define PIO_OWSR_P31 (0x1u << 31) /**< \brief (PIO_OWSR) Output Write Status. */
    02960 /* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */
    02961 #define PIO_AIMER_P0 (0x1u << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
    02962 #define PIO_AIMER_P1 (0x1u << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
    02963 #define PIO_AIMER_P2 (0x1u << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
    02964 #define PIO_AIMER_P3 (0x1u << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
    02965 #define PIO_AIMER_P4 (0x1u << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
    02966 #define PIO_AIMER_P5 (0x1u << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
    02967 #define PIO_AIMER_P6 (0x1u << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
    02968 #define PIO_AIMER_P7 (0x1u << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
    02969 #define PIO_AIMER_P8 (0x1u << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
    02970 #define PIO_AIMER_P9 (0x1u << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
    02971 #define PIO_AIMER_P10 (0x1u << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
    02972 #define PIO_AIMER_P11 (0x1u << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
    02973 #define PIO_AIMER_P12 (0x1u << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
    02974 #define PIO_AIMER_P13 (0x1u << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
    02975 #define PIO_AIMER_P14 (0x1u << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
    02976 #define PIO_AIMER_P15 (0x1u << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
    02977 #define PIO_AIMER_P16 (0x1u << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
    02978 #define PIO_AIMER_P17 (0x1u << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
    02979 #define PIO_AIMER_P18 (0x1u << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
    02980 #define PIO_AIMER_P19 (0x1u << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
    02981 #define PIO_AIMER_P20 (0x1u << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
    02982 #define PIO_AIMER_P21 (0x1u << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
    02983 #define PIO_AIMER_P22 (0x1u << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
    02984 #define PIO_AIMER_P23 (0x1u << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
    02985 #define PIO_AIMER_P24 (0x1u << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
    02986 #define PIO_AIMER_P25 (0x1u << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
    02987 #define PIO_AIMER_P26 (0x1u << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
    02988 #define PIO_AIMER_P27 (0x1u << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
    02989 #define PIO_AIMER_P28 (0x1u << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
    02990 #define PIO_AIMER_P29 (0x1u << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
    02991 #define PIO_AIMER_P30 (0x1u << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
    02992 #define PIO_AIMER_P31 (0x1u << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
    02993 /* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disables Register -------- */
    02994 #define PIO_AIMDR_P0 (0x1u << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
    02995 #define PIO_AIMDR_P1 (0x1u << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
    02996 #define PIO_AIMDR_P2 (0x1u << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
    02997 #define PIO_AIMDR_P3 (0x1u << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
    02998 #define PIO_AIMDR_P4 (0x1u << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
    02999 #define PIO_AIMDR_P5 (0x1u << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
    03000 #define PIO_AIMDR_P6 (0x1u << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
    03001 #define PIO_AIMDR_P7 (0x1u << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
    03002 #define PIO_AIMDR_P8 (0x1u << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
    03003 #define PIO_AIMDR_P9 (0x1u << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
    03004 #define PIO_AIMDR_P10 (0x1u << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
    03005 #define PIO_AIMDR_P11 (0x1u << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
    03006 #define PIO_AIMDR_P12 (0x1u << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
    03007 #define PIO_AIMDR_P13 (0x1u << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
    03008 #define PIO_AIMDR_P14 (0x1u << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
    03009 #define PIO_AIMDR_P15 (0x1u << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
    03010 #define PIO_AIMDR_P16 (0x1u << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
    03011 #define PIO_AIMDR_P17 (0x1u << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
    03012 #define PIO_AIMDR_P18 (0x1u << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
    03013 #define PIO_AIMDR_P19 (0x1u << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
    03014 #define PIO_AIMDR_P20 (0x1u << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
    03015 #define PIO_AIMDR_P21 (0x1u << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
    03016 #define PIO_AIMDR_P22 (0x1u << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
    03017 #define PIO_AIMDR_P23 (0x1u << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
    03018 #define PIO_AIMDR_P24 (0x1u << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
    03019 #define PIO_AIMDR_P25 (0x1u << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
    03020 #define PIO_AIMDR_P26 (0x1u << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
    03021 #define PIO_AIMDR_P27 (0x1u << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
    03022 #define PIO_AIMDR_P28 (0x1u << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
    03023 #define PIO_AIMDR_P29 (0x1u << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
    03024 #define PIO_AIMDR_P30 (0x1u << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
    03025 #define PIO_AIMDR_P31 (0x1u << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
    03026 /* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */
    03027 #define PIO_AIMMR_P0 (0x1u << 0) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
    03028 #define PIO_AIMMR_P1 (0x1u << 1) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
    03029 #define PIO_AIMMR_P2 (0x1u << 2) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
    03030 #define PIO_AIMMR_P3 (0x1u << 3) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
    03031 #define PIO_AIMMR_P4 (0x1u << 4) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
    03032 #define PIO_AIMMR_P5 (0x1u << 5) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
    03033 #define PIO_AIMMR_P6 (0x1u << 6) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
    03034 #define PIO_AIMMR_P7 (0x1u << 7) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
    03035 #define PIO_AIMMR_P8 (0x1u << 8) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
    03036 #define PIO_AIMMR_P9 (0x1u << 9) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
    03037 #define PIO_AIMMR_P10 (0x1u << 10) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
    03038 #define PIO_AIMMR_P11 (0x1u << 11) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
    03039 #define PIO_AIMMR_P12 (0x1u << 12) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
    03040 #define PIO_AIMMR_P13 (0x1u << 13) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
    03041 #define PIO_AIMMR_P14 (0x1u << 14) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
    03042 #define PIO_AIMMR_P15 (0x1u << 15) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
    03043 #define PIO_AIMMR_P16 (0x1u << 16) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
    03044 #define PIO_AIMMR_P17 (0x1u << 17) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
    03045 #define PIO_AIMMR_P18 (0x1u << 18) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
    03046 #define PIO_AIMMR_P19 (0x1u << 19) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
    03047 #define PIO_AIMMR_P20 (0x1u << 20) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
    03048 #define PIO_AIMMR_P21 (0x1u << 21) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
    03049 #define PIO_AIMMR_P22 (0x1u << 22) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
    03050 #define PIO_AIMMR_P23 (0x1u << 23) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
    03051 #define PIO_AIMMR_P24 (0x1u << 24) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
    03052 #define PIO_AIMMR_P25 (0x1u << 25) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
    03053 #define PIO_AIMMR_P26 (0x1u << 26) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
    03054 #define PIO_AIMMR_P27 (0x1u << 27) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
    03055 #define PIO_AIMMR_P28 (0x1u << 28) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
    03056 #define PIO_AIMMR_P29 (0x1u << 29) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
    03057 #define PIO_AIMMR_P30 (0x1u << 30) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
    03058 #define PIO_AIMMR_P31 (0x1u << 31) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
    03059 /* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */
    03060 #define PIO_ESR_P0 (0x1u << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
    03061 #define PIO_ESR_P1 (0x1u << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
    03062 #define PIO_ESR_P2 (0x1u << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
    03063 #define PIO_ESR_P3 (0x1u << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
    03064 #define PIO_ESR_P4 (0x1u << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
    03065 #define PIO_ESR_P5 (0x1u << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
    03066 #define PIO_ESR_P6 (0x1u << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
    03067 #define PIO_ESR_P7 (0x1u << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
    03068 #define PIO_ESR_P8 (0x1u << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
    03069 #define PIO_ESR_P9 (0x1u << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
    03070 #define PIO_ESR_P10 (0x1u << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
    03071 #define PIO_ESR_P11 (0x1u << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
    03072 #define PIO_ESR_P12 (0x1u << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
    03073 #define PIO_ESR_P13 (0x1u << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
    03074 #define PIO_ESR_P14 (0x1u << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
    03075 #define PIO_ESR_P15 (0x1u << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
    03076 #define PIO_ESR_P16 (0x1u << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
    03077 #define PIO_ESR_P17 (0x1u << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
    03078 #define PIO_ESR_P18 (0x1u << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
    03079 #define PIO_ESR_P19 (0x1u << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
    03080 #define PIO_ESR_P20 (0x1u << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
    03081 #define PIO_ESR_P21 (0x1u << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
    03082 #define PIO_ESR_P22 (0x1u << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
    03083 #define PIO_ESR_P23 (0x1u << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
    03084 #define PIO_ESR_P24 (0x1u << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
    03085 #define PIO_ESR_P25 (0x1u << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
    03086 #define PIO_ESR_P26 (0x1u << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
    03087 #define PIO_ESR_P27 (0x1u << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
    03088 #define PIO_ESR_P28 (0x1u << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
    03089 #define PIO_ESR_P29 (0x1u << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
    03090 #define PIO_ESR_P30 (0x1u << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
    03091 #define PIO_ESR_P31 (0x1u << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
    03092 /* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */
    03093 #define PIO_LSR_P0 (0x1u << 0) /**< \brief (PIO_LSR) Level Interrupt Selection. */
    03094 #define PIO_LSR_P1 (0x1u << 1) /**< \brief (PIO_LSR) Level Interrupt Selection. */
    03095 #define PIO_LSR_P2 (0x1u << 2) /**< \brief (PIO_LSR) Level Interrupt Selection. */
    03096 #define PIO_LSR_P3 (0x1u << 3) /**< \brief (PIO_LSR) Level Interrupt Selection. */
    03097 #define PIO_LSR_P4 (0x1u << 4) /**< \brief (PIO_LSR) Level Interrupt Selection. */
    03098 #define PIO_LSR_P5 (0x1u << 5) /**< \brief (PIO_LSR) Level Interrupt Selection. */
    03099 #define PIO_LSR_P6 (0x1u << 6) /**< \brief (PIO_LSR) Level Interrupt Selection. */
    03100 #define PIO_LSR_P7 (0x1u << 7) /**< \brief (PIO_LSR) Level Interrupt Selection. */
    03101 #define PIO_LSR_P8 (0x1u << 8) /**< \brief (PIO_LSR) Level Interrupt Selection. */
    03102 #define PIO_LSR_P9 (0x1u << 9) /**< \brief (PIO_LSR) Level Interrupt Selection. */
    03103 #define PIO_LSR_P10 (0x1u << 10) /**< \brief (PIO_LSR) Level Interrupt Selection. */
    03104 #define PIO_LSR_P11 (0x1u << 11) /**< \brief (PIO_LSR) Level Interrupt Selection. */
    03105 #define PIO_LSR_P12 (0x1u << 12) /**< \brief (PIO_LSR) Level Interrupt Selection. */
    03106 #define PIO_LSR_P13 (0x1u << 13) /**< \brief (PIO_LSR) Level Interrupt Selection. */
    03107 #define PIO_LSR_P14 (0x1u << 14) /**< \brief (PIO_LSR) Level Interrupt Selection. */
    03108 #define PIO_LSR_P15 (0x1u << 15) /**< \brief (PIO_LSR) Level Interrupt Selection. */
    03109 #define PIO_LSR_P16 (0x1u << 16) /**< \brief (PIO_LSR) Level Interrupt Selection. */
    03110 #define PIO_LSR_P17 (0x1u << 17) /**< \brief (PIO_LSR) Level Interrupt Selection. */
    03111 #define PIO_LSR_P18 (0x1u << 18) /**< \brief (PIO_LSR) Level Interrupt Selection. */
    03112 #define PIO_LSR_P19 (0x1u << 19) /**< \brief (PIO_LSR) Level Interrupt Selection. */
    03113 #define PIO_LSR_P20 (0x1u << 20) /**< \brief (PIO_LSR) Level Interrupt Selection. */
    03114 #define PIO_LSR_P21 (0x1u << 21) /**< \brief (PIO_LSR) Level Interrupt Selection. */
    03115 #define PIO_LSR_P22 (0x1u << 22) /**< \brief (PIO_LSR) Level Interrupt Selection. */
    03116 #define PIO_LSR_P23 (0x1u << 23) /**< \brief (PIO_LSR) Level Interrupt Selection. */
    03117 #define PIO_LSR_P24 (0x1u << 24) /**< \brief (PIO_LSR) Level Interrupt Selection. */
    03118 #define PIO_LSR_P25 (0x1u << 25) /**< \brief (PIO_LSR) Level Interrupt Selection. */
    03119 #define PIO_LSR_P26 (0x1u << 26) /**< \brief (PIO_LSR) Level Interrupt Selection. */
    03120 #define PIO_LSR_P27 (0x1u << 27) /**< \brief (PIO_LSR) Level Interrupt Selection. */
    03121 #define PIO_LSR_P28 (0x1u << 28) /**< \brief (PIO_LSR) Level Interrupt Selection. */
    03122 #define PIO_LSR_P29 (0x1u << 29) /**< \brief (PIO_LSR) Level Interrupt Selection. */
    03123 #define PIO_LSR_P30 (0x1u << 30) /**< \brief (PIO_LSR) Level Interrupt Selection. */
    03124 #define PIO_LSR_P31 (0x1u << 31) /**< \brief (PIO_LSR) Level Interrupt Selection. */
    03125 /* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */
    03126 #define PIO_ELSR_P0 (0x1u << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
    03127 #define PIO_ELSR_P1 (0x1u << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
    03128 #define PIO_ELSR_P2 (0x1u << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
    03129 #define PIO_ELSR_P3 (0x1u << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
    03130 #define PIO_ELSR_P4 (0x1u << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
    03131 #define PIO_ELSR_P5 (0x1u << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
    03132 #define PIO_ELSR_P6 (0x1u << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
    03133 #define PIO_ELSR_P7 (0x1u << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
    03134 #define PIO_ELSR_P8 (0x1u << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
    03135 #define PIO_ELSR_P9 (0x1u << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
    03136 #define PIO_ELSR_P10 (0x1u << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
    03137 #define PIO_ELSR_P11 (0x1u << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
    03138 #define PIO_ELSR_P12 (0x1u << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
    03139 #define PIO_ELSR_P13 (0x1u << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
    03140 #define PIO_ELSR_P14 (0x1u << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
    03141 #define PIO_ELSR_P15 (0x1u << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
    03142 #define PIO_ELSR_P16 (0x1u << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
    03143 #define PIO_ELSR_P17 (0x1u << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
    03144 #define PIO_ELSR_P18 (0x1u << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
    03145 #define PIO_ELSR_P19 (0x1u << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
    03146 #define PIO_ELSR_P20 (0x1u << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
    03147 #define PIO_ELSR_P21 (0x1u << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
    03148 #define PIO_ELSR_P22 (0x1u << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
    03149 #define PIO_ELSR_P23 (0x1u << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
    03150 #define PIO_ELSR_P24 (0x1u << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
    03151 #define PIO_ELSR_P25 (0x1u << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
    03152 #define PIO_ELSR_P26 (0x1u << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
    03153 #define PIO_ELSR_P27 (0x1u << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
    03154 #define PIO_ELSR_P28 (0x1u << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
    03155 #define PIO_ELSR_P29 (0x1u << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
    03156 #define PIO_ELSR_P30 (0x1u << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
    03157 #define PIO_ELSR_P31 (0x1u << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
    03158 /* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low Level Select Register -------- */
    03159 #define PIO_FELLSR_P0 (0x1u << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
    03160 #define PIO_FELLSR_P1 (0x1u << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
    03161 #define PIO_FELLSR_P2 (0x1u << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
    03162 #define PIO_FELLSR_P3 (0x1u << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
    03163 #define PIO_FELLSR_P4 (0x1u << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
    03164 #define PIO_FELLSR_P5 (0x1u << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
    03165 #define PIO_FELLSR_P6 (0x1u << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
    03166 #define PIO_FELLSR_P7 (0x1u << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
    03167 #define PIO_FELLSR_P8 (0x1u << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
    03168 #define PIO_FELLSR_P9 (0x1u << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
    03169 #define PIO_FELLSR_P10 (0x1u << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
    03170 #define PIO_FELLSR_P11 (0x1u << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
    03171 #define PIO_FELLSR_P12 (0x1u << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
    03172 #define PIO_FELLSR_P13 (0x1u << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
    03173 #define PIO_FELLSR_P14 (0x1u << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
    03174 #define PIO_FELLSR_P15 (0x1u << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
    03175 #define PIO_FELLSR_P16 (0x1u << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
    03176 #define PIO_FELLSR_P17 (0x1u << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
    03177 #define PIO_FELLSR_P18 (0x1u << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
    03178 #define PIO_FELLSR_P19 (0x1u << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
    03179 #define PIO_FELLSR_P20 (0x1u << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
    03180 #define PIO_FELLSR_P21 (0x1u << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
    03181 #define PIO_FELLSR_P22 (0x1u << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
    03182 #define PIO_FELLSR_P23 (0x1u << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
    03183 #define PIO_FELLSR_P24 (0x1u << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
    03184 #define PIO_FELLSR_P25 (0x1u << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
    03185 #define PIO_FELLSR_P26 (0x1u << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
    03186 #define PIO_FELLSR_P27 (0x1u << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
    03187 #define PIO_FELLSR_P28 (0x1u << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
    03188 #define PIO_FELLSR_P29 (0x1u << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
    03189 #define PIO_FELLSR_P30 (0x1u << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
    03190 #define PIO_FELLSR_P31 (0x1u << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
    03191 /* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/ High Level Select Register -------- */
    03192 #define PIO_REHLSR_P0 (0x1u << 0) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
    03193 #define PIO_REHLSR_P1 (0x1u << 1) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
    03194 #define PIO_REHLSR_P2 (0x1u << 2) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
    03195 #define PIO_REHLSR_P3 (0x1u << 3) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
    03196 #define PIO_REHLSR_P4 (0x1u << 4) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
    03197 #define PIO_REHLSR_P5 (0x1u << 5) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
    03198 #define PIO_REHLSR_P6 (0x1u << 6) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
    03199 #define PIO_REHLSR_P7 (0x1u << 7) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
    03200 #define PIO_REHLSR_P8 (0x1u << 8) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
    03201 #define PIO_REHLSR_P9 (0x1u << 9) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
    03202 #define PIO_REHLSR_P10 (0x1u << 10) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
    03203 #define PIO_REHLSR_P11 (0x1u << 11) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
    03204 #define PIO_REHLSR_P12 (0x1u << 12) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
    03205 #define PIO_REHLSR_P13 (0x1u << 13) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
    03206 #define PIO_REHLSR_P14 (0x1u << 14) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
    03207 #define PIO_REHLSR_P15 (0x1u << 15) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
    03208 #define PIO_REHLSR_P16 (0x1u << 16) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
    03209 #define PIO_REHLSR_P17 (0x1u << 17) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
    03210 #define PIO_REHLSR_P18 (0x1u << 18) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
    03211 #define PIO_REHLSR_P19 (0x1u << 19) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
    03212 #define PIO_REHLSR_P20 (0x1u << 20) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
    03213 #define PIO_REHLSR_P21 (0x1u << 21) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
    03214 #define PIO_REHLSR_P22 (0x1u << 22) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
    03215 #define PIO_REHLSR_P23 (0x1u << 23) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
    03216 #define PIO_REHLSR_P24 (0x1u << 24) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
    03217 #define PIO_REHLSR_P25 (0x1u << 25) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
    03218 #define PIO_REHLSR_P26 (0x1u << 26) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
    03219 #define PIO_REHLSR_P27 (0x1u << 27) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
    03220 #define PIO_REHLSR_P28 (0x1u << 28) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
    03221 #define PIO_REHLSR_P29 (0x1u << 29) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
    03222 #define PIO_REHLSR_P30 (0x1u << 30) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
    03223 #define PIO_REHLSR_P31 (0x1u << 31) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
    03224 /* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */
    03225 #define PIO_FRLHSR_P0 (0x1u << 0) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
    03226 #define PIO_FRLHSR_P1 (0x1u << 1) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
    03227 #define PIO_FRLHSR_P2 (0x1u << 2) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
    03228 #define PIO_FRLHSR_P3 (0x1u << 3) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
    03229 #define PIO_FRLHSR_P4 (0x1u << 4) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
    03230 #define PIO_FRLHSR_P5 (0x1u << 5) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
    03231 #define PIO_FRLHSR_P6 (0x1u << 6) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
    03232 #define PIO_FRLHSR_P7 (0x1u << 7) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
    03233 #define PIO_FRLHSR_P8 (0x1u << 8) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
    03234 #define PIO_FRLHSR_P9 (0x1u << 9) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
    03235 #define PIO_FRLHSR_P10 (0x1u << 10) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
    03236 #define PIO_FRLHSR_P11 (0x1u << 11) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
    03237 #define PIO_FRLHSR_P12 (0x1u << 12) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
    03238 #define PIO_FRLHSR_P13 (0x1u << 13) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
    03239 #define PIO_FRLHSR_P14 (0x1u << 14) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
    03240 #define PIO_FRLHSR_P15 (0x1u << 15) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
    03241 #define PIO_FRLHSR_P16 (0x1u << 16) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
    03242 #define PIO_FRLHSR_P17 (0x1u << 17) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
    03243 #define PIO_FRLHSR_P18 (0x1u << 18) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
    03244 #define PIO_FRLHSR_P19 (0x1u << 19) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
    03245 #define PIO_FRLHSR_P20 (0x1u << 20) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
    03246 #define PIO_FRLHSR_P21 (0x1u << 21) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
    03247 #define PIO_FRLHSR_P22 (0x1u << 22) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
    03248 #define PIO_FRLHSR_P23 (0x1u << 23) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
    03249 #define PIO_FRLHSR_P24 (0x1u << 24) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
    03250 #define PIO_FRLHSR_P25 (0x1u << 25) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
    03251 #define PIO_FRLHSR_P26 (0x1u << 26) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
    03252 #define PIO_FRLHSR_P27 (0x1u << 27) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
    03253 #define PIO_FRLHSR_P28 (0x1u << 28) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
    03254 #define PIO_FRLHSR_P29 (0x1u << 29) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
    03255 #define PIO_FRLHSR_P30 (0x1u << 30) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
    03256 #define PIO_FRLHSR_P31 (0x1u << 31) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
    03257 /* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */
    03258 #define PIO_LOCKSR_P0 (0x1u << 0) /**< \brief (PIO_LOCKSR) Lock Status. */
    03259 #define PIO_LOCKSR_P1 (0x1u << 1) /**< \brief (PIO_LOCKSR) Lock Status. */
    03260 #define PIO_LOCKSR_P2 (0x1u << 2) /**< \brief (PIO_LOCKSR) Lock Status. */
    03261 #define PIO_LOCKSR_P3 (0x1u << 3) /**< \brief (PIO_LOCKSR) Lock Status. */
    03262 #define PIO_LOCKSR_P4 (0x1u << 4) /**< \brief (PIO_LOCKSR) Lock Status. */
    03263 #define PIO_LOCKSR_P5 (0x1u << 5) /**< \brief (PIO_LOCKSR) Lock Status. */
    03264 #define PIO_LOCKSR_P6 (0x1u << 6) /**< \brief (PIO_LOCKSR) Lock Status. */
    03265 #define PIO_LOCKSR_P7 (0x1u << 7) /**< \brief (PIO_LOCKSR) Lock Status. */
    03266 #define PIO_LOCKSR_P8 (0x1u << 8) /**< \brief (PIO_LOCKSR) Lock Status. */
    03267 #define PIO_LOCKSR_P9 (0x1u << 9) /**< \brief (PIO_LOCKSR) Lock Status. */
    03268 #define PIO_LOCKSR_P10 (0x1u << 10) /**< \brief (PIO_LOCKSR) Lock Status. */
    03269 #define PIO_LOCKSR_P11 (0x1u << 11) /**< \brief (PIO_LOCKSR) Lock Status. */
    03270 #define PIO_LOCKSR_P12 (0x1u << 12) /**< \brief (PIO_LOCKSR) Lock Status. */
    03271 #define PIO_LOCKSR_P13 (0x1u << 13) /**< \brief (PIO_LOCKSR) Lock Status. */
    03272 #define PIO_LOCKSR_P14 (0x1u << 14) /**< \brief (PIO_LOCKSR) Lock Status. */
    03273 #define PIO_LOCKSR_P15 (0x1u << 15) /**< \brief (PIO_LOCKSR) Lock Status. */
    03274 #define PIO_LOCKSR_P16 (0x1u << 16) /**< \brief (PIO_LOCKSR) Lock Status. */
    03275 #define PIO_LOCKSR_P17 (0x1u << 17) /**< \brief (PIO_LOCKSR) Lock Status. */
    03276 #define PIO_LOCKSR_P18 (0x1u << 18) /**< \brief (PIO_LOCKSR) Lock Status. */
    03277 #define PIO_LOCKSR_P19 (0x1u << 19) /**< \brief (PIO_LOCKSR) Lock Status. */
    03278 #define PIO_LOCKSR_P20 (0x1u << 20) /**< \brief (PIO_LOCKSR) Lock Status. */
    03279 #define PIO_LOCKSR_P21 (0x1u << 21) /**< \brief (PIO_LOCKSR) Lock Status. */
    03280 #define PIO_LOCKSR_P22 (0x1u << 22) /**< \brief (PIO_LOCKSR) Lock Status. */
    03281 #define PIO_LOCKSR_P23 (0x1u << 23) /**< \brief (PIO_LOCKSR) Lock Status. */
    03282 #define PIO_LOCKSR_P24 (0x1u << 24) /**< \brief (PIO_LOCKSR) Lock Status. */
    03283 #define PIO_LOCKSR_P25 (0x1u << 25) /**< \brief (PIO_LOCKSR) Lock Status. */
    03284 #define PIO_LOCKSR_P26 (0x1u << 26) /**< \brief (PIO_LOCKSR) Lock Status. */
    03285 #define PIO_LOCKSR_P27 (0x1u << 27) /**< \brief (PIO_LOCKSR) Lock Status. */
    03286 #define PIO_LOCKSR_P28 (0x1u << 28) /**< \brief (PIO_LOCKSR) Lock Status. */
    03287 #define PIO_LOCKSR_P29 (0x1u << 29) /**< \brief (PIO_LOCKSR) Lock Status. */
    03288 #define PIO_LOCKSR_P30 (0x1u << 30) /**< \brief (PIO_LOCKSR) Lock Status. */
    03289 #define PIO_LOCKSR_P31 (0x1u << 31) /**< \brief (PIO_LOCKSR) Lock Status. */
    03290 /* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protect Mode Register -------- */
    03291 #define PIO_WPMR_WPEN (0x1u << 0) /**< \brief (PIO_WPMR) Write Protect Enable */
    03292 #define PIO_WPMR_WPKEY_Pos 8
    03293 #define PIO_WPMR_WPKEY_Msk (0xffffffu << PIO_WPMR_WPKEY_Pos) /**< \brief (PIO_WPMR) Write Protect KEY */
    03294 #define PIO_WPMR_WPKEY(value) ((PIO_WPMR_WPKEY_Msk & ((value) << PIO_WPMR_WPKEY_Pos)))
    03295 /* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protect Status Register -------- */
    03296 #define PIO_WPSR_WPVS (0x1u << 0) /**< \brief (PIO_WPSR) Write Protect Violation Status */
    03297 #define PIO_WPSR_WPVSRC_Pos 8
    03298 #define PIO_WPSR_WPVSRC_Msk (0xffffu << PIO_WPSR_WPVSRC_Pos) /**< \brief (PIO_WPSR) Write Protect Violation Source */
    03299 /* -------- PIO_SCHMITT : (PIO Offset: 0x0100) Schmitt Trigger Register -------- */
    03300 #define PIO_SCHMITT_SCHMITT0 (0x1u << 0) /**< \brief (PIO_SCHMITT)  */
    03301 #define PIO_SCHMITT_SCHMITT1 (0x1u << 1) /**< \brief (PIO_SCHMITT)  */
    03302 #define PIO_SCHMITT_SCHMITT2 (0x1u << 2) /**< \brief (PIO_SCHMITT)  */
    03303 #define PIO_SCHMITT_SCHMITT3 (0x1u << 3) /**< \brief (PIO_SCHMITT)  */
    03304 #define PIO_SCHMITT_SCHMITT4 (0x1u << 4) /**< \brief (PIO_SCHMITT)  */
    03305 #define PIO_SCHMITT_SCHMITT5 (0x1u << 5) /**< \brief (PIO_SCHMITT)  */
    03306 #define PIO_SCHMITT_SCHMITT6 (0x1u << 6) /**< \brief (PIO_SCHMITT)  */
    03307 #define PIO_SCHMITT_SCHMITT7 (0x1u << 7) /**< \brief (PIO_SCHMITT)  */
    03308 #define PIO_SCHMITT_SCHMITT8 (0x1u << 8) /**< \brief (PIO_SCHMITT)  */
    03309 #define PIO_SCHMITT_SCHMITT9 (0x1u << 9) /**< \brief (PIO_SCHMITT)  */
    03310 #define PIO_SCHMITT_SCHMITT10 (0x1u << 10) /**< \brief (PIO_SCHMITT)  */
    03311 #define PIO_SCHMITT_SCHMITT11 (0x1u << 11) /**< \brief (PIO_SCHMITT)  */
    03312 #define PIO_SCHMITT_SCHMITT12 (0x1u << 12) /**< \brief (PIO_SCHMITT)  */
    03313 #define PIO_SCHMITT_SCHMITT13 (0x1u << 13) /**< \brief (PIO_SCHMITT)  */
    03314 #define PIO_SCHMITT_SCHMITT14 (0x1u << 14) /**< \brief (PIO_SCHMITT)  */
    03315 #define PIO_SCHMITT_SCHMITT15 (0x1u << 15) /**< \brief (PIO_SCHMITT)  */
    03316 #define PIO_SCHMITT_SCHMITT16 (0x1u << 16) /**< \brief (PIO_SCHMITT)  */
    03317 #define PIO_SCHMITT_SCHMITT17 (0x1u << 17) /**< \brief (PIO_SCHMITT)  */
    03318 #define PIO_SCHMITT_SCHMITT18 (0x1u << 18) /**< \brief (PIO_SCHMITT)  */
    03319 #define PIO_SCHMITT_SCHMITT19 (0x1u << 19) /**< \brief (PIO_SCHMITT)  */
    03320 #define PIO_SCHMITT_SCHMITT20 (0x1u << 20) /**< \brief (PIO_SCHMITT)  */
    03321 #define PIO_SCHMITT_SCHMITT21 (0x1u << 21) /**< \brief (PIO_SCHMITT)  */
    03322 #define PIO_SCHMITT_SCHMITT22 (0x1u << 22) /**< \brief (PIO_SCHMITT)  */
    03323 #define PIO_SCHMITT_SCHMITT23 (0x1u << 23) /**< \brief (PIO_SCHMITT)  */
    03324 #define PIO_SCHMITT_SCHMITT24 (0x1u << 24) /**< \brief (PIO_SCHMITT)  */
    03325 #define PIO_SCHMITT_SCHMITT25 (0x1u << 25) /**< \brief (PIO_SCHMITT)  */
    03326 #define PIO_SCHMITT_SCHMITT26 (0x1u << 26) /**< \brief (PIO_SCHMITT)  */
    03327 #define PIO_SCHMITT_SCHMITT27 (0x1u << 27) /**< \brief (PIO_SCHMITT)  */
    03328 #define PIO_SCHMITT_SCHMITT28 (0x1u << 28) /**< \brief (PIO_SCHMITT)  */
    03329 #define PIO_SCHMITT_SCHMITT29 (0x1u << 29) /**< \brief (PIO_SCHMITT)  */
    03330 #define PIO_SCHMITT_SCHMITT30 (0x1u << 30) /**< \brief (PIO_SCHMITT)  */
    03331 #define PIO_SCHMITT_SCHMITT31 (0x1u << 31) /**< \brief (PIO_SCHMITT)  */
    03332 /* -------- PIO_PCMR : (PIO Offset: 0x150) Parallel Capture Mode Register -------- */
    03333 #define PIO_PCMR_PCEN (0x1u << 0) /**< \brief (PIO_PCMR) Parallel Capture Mode Enable */
    03334 #define PIO_PCMR_DSIZE_Pos 4
    03335 #define PIO_PCMR_DSIZE_Msk (0x3u << PIO_PCMR_DSIZE_Pos) /**< \brief (PIO_PCMR) Parallel Capture Mode Data Size */
    03336 #define PIO_PCMR_DSIZE(value) ((PIO_PCMR_DSIZE_Msk & ((value) << PIO_PCMR_DSIZE_Pos)))
    03337 #define PIO_PCMR_ALWYS (0x1u << 9) /**< \brief (PIO_PCMR) Parallel Capture Mode Always Sampling */
    03338 #define PIO_PCMR_HALFS (0x1u << 10) /**< \brief (PIO_PCMR) Parallel Capture Mode Half Sampling */
    03339 #define PIO_PCMR_FRSTS (0x1u << 11) /**< \brief (PIO_PCMR) Parallel Capture Mode First Sample */
    03340 /* -------- PIO_PCIER : (PIO Offset: 0x154) Parallel Capture Interrupt Enable Register -------- */
    03341 #define PIO_PCIER_DRDY (0x1u << 0) /**< \brief (PIO_PCIER) Parallel Capture Mode Data Ready Interrupt Enable */
    03342 #define PIO_PCIER_OVRE (0x1u << 1) /**< \brief (PIO_PCIER) Parallel Capture Mode Overrun Error Interrupt Enable */
    03343 #define PIO_PCIER_ENDRX (0x1u << 2) /**< \brief (PIO_PCIER) End of Reception Transfer Interrupt Enable */
    03344 #define PIO_PCIER_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIER) Reception Buffer Full Interrupt Enable */
    03345 /* -------- PIO_PCIDR : (PIO Offset: 0x158) Parallel Capture Interrupt Disable Register -------- */
    03346 #define PIO_PCIDR_DRDY (0x1u << 0) /**< \brief (PIO_PCIDR) Parallel Capture Mode Data Ready Interrupt Disable */
    03347 #define PIO_PCIDR_OVRE (0x1u << 1) /**< \brief (PIO_PCIDR) Parallel Capture Mode Overrun Error Interrupt Disable */
    03348 #define PIO_PCIDR_ENDRX (0x1u << 2) /**< \brief (PIO_PCIDR) End of Reception Transfer Interrupt Disable */
    03349 #define PIO_PCIDR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIDR) Reception Buffer Full Interrupt Disable */
    03350 /* -------- PIO_PCIMR : (PIO Offset: 0x15C) Parallel Capture Interrupt Mask Register -------- */
    03351 #define PIO_PCIMR_DRDY (0x1u << 0) /**< \brief (PIO_PCIMR) Parallel Capture Mode Data Ready Interrupt Mask */
    03352 #define PIO_PCIMR_OVRE (0x1u << 1) /**< \brief (PIO_PCIMR) Parallel Capture Mode Overrun Error Interrupt Mask */
    03353 #define PIO_PCIMR_ENDRX (0x1u << 2) /**< \brief (PIO_PCIMR) End of Reception Transfer Interrupt Mask */
    03354 #define PIO_PCIMR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIMR) Reception Buffer Full Interrupt Mask */
    03355 /* -------- PIO_PCISR : (PIO Offset: 0x160) Parallel Capture Interrupt Status Register -------- */
    03356 #define PIO_PCISR_DRDY (0x1u << 0) /**< \brief (PIO_PCISR) Parallel Capture Mode Data Ready */
    03357 #define PIO_PCISR_OVRE (0x1u << 1) /**< \brief (PIO_PCISR) Parallel Capture Mode Overrun Error. */
    03358 #define PIO_PCISR_ENDRX (0x1u << 2) /**< \brief (PIO_PCISR) End of Reception Transfer. */
    03359 #define PIO_PCISR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCISR) Reception Buffer Full */
    03360 /* -------- PIO_PCRHR : (PIO Offset: 0x164) Parallel Capture Reception Holding Register -------- */
    03361 #define PIO_PCRHR_RDATA_Pos 0
    03362 #define PIO_PCRHR_RDATA_Msk (0xffffffffu << PIO_PCRHR_RDATA_Pos) /**< \brief (PIO_PCRHR) Parallel Capture Mode Reception Data. */
    03363 /* -------- PIO_RPR : (PIO Offset: 0x168) Receive Pointer Register -------- */
    03364 #define PIO_RPR_RXPTR_Pos 0
    03365 #define PIO_RPR_RXPTR_Msk (0xffffffffu << PIO_RPR_RXPTR_Pos) /**< \brief (PIO_RPR) Receive Pointer Register */
    03366 #define PIO_RPR_RXPTR(value) ((PIO_RPR_RXPTR_Msk & ((value) << PIO_RPR_RXPTR_Pos)))
    03367 /* -------- PIO_RCR : (PIO Offset: 0x16C) Receive Counter Register -------- */
    03368 #define PIO_RCR_RXCTR_Pos 0
    03369 #define PIO_RCR_RXCTR_Msk (0xffffu << PIO_RCR_RXCTR_Pos) /**< \brief (PIO_RCR) Receive Counter Register */
    03370 #define PIO_RCR_RXCTR(value) ((PIO_RCR_RXCTR_Msk & ((value) << PIO_RCR_RXCTR_Pos)))
    03371 /* -------- PIO_TPR : (PIO Offset: 0x170) Transmit Pointer Register -------- */
    03372 #define PIO_TPR_TXPTR_Pos 0
    03373 #define PIO_TPR_TXPTR_Msk (0xffffffffu << PIO_TPR_TXPTR_Pos) /**< \brief (PIO_TPR) Transmit Counter Register */
    03374 #define PIO_TPR_TXPTR(value) ((PIO_TPR_TXPTR_Msk & ((value) << PIO_TPR_TXPTR_Pos)))
    03375 /* -------- PIO_TCR : (PIO Offset: 0x174) Transmit Counter Register -------- */
    03376 #define PIO_TCR_TXCTR_Pos 0
    03377 #define PIO_TCR_TXCTR_Msk (0xffffu << PIO_TCR_TXCTR_Pos) /**< \brief (PIO_TCR) Transmit Counter Register */
    03378 #define PIO_TCR_TXCTR(value) ((PIO_TCR_TXCTR_Msk & ((value) << PIO_TCR_TXCTR_Pos)))
    03379 /* -------- PIO_RNPR : (PIO Offset: 0x178) Receive Next Pointer Register -------- */
    03380 #define PIO_RNPR_RXNPTR_Pos 0
    03381 #define PIO_RNPR_RXNPTR_Msk (0xffffffffu << PIO_RNPR_RXNPTR_Pos) /**< \brief (PIO_RNPR) Receive Next Pointer */
    03382 #define PIO_RNPR_RXNPTR(value) ((PIO_RNPR_RXNPTR_Msk & ((value) << PIO_RNPR_RXNPTR_Pos)))
    03383 /* -------- PIO_RNCR : (PIO Offset: 0x17C) Receive Next Counter Register -------- */
    03384 #define PIO_RNCR_RXNCTR_Pos 0
    03385 #define PIO_RNCR_RXNCTR_Msk (0xffffu << PIO_RNCR_RXNCTR_Pos) /**< \brief (PIO_RNCR) Receive Next Counter */
    03386 #define PIO_RNCR_RXNCTR(value) ((PIO_RNCR_RXNCTR_Msk & ((value) << PIO_RNCR_RXNCTR_Pos)))
    03387 /* -------- PIO_TNPR : (PIO Offset: 0x180) Transmit Next Pointer Register -------- */
    03388 #define PIO_TNPR_TXNPTR_Pos 0
    03389 #define PIO_TNPR_TXNPTR_Msk (0xffffffffu << PIO_TNPR_TXNPTR_Pos) /**< \brief (PIO_TNPR) Transmit Next Pointer */
    03390 #define PIO_TNPR_TXNPTR(value) ((PIO_TNPR_TXNPTR_Msk & ((value) << PIO_TNPR_TXNPTR_Pos)))
    03391 /* -------- PIO_TNCR : (PIO Offset: 0x184) Transmit Next Counter Register -------- */
    03392 #define PIO_TNCR_TXNCTR_Pos 0
    03393 #define PIO_TNCR_TXNCTR_Msk (0xffffu << PIO_TNCR_TXNCTR_Pos) /**< \brief (PIO_TNCR) Transmit Counter Next */
    03394 #define PIO_TNCR_TXNCTR(value) ((PIO_TNCR_TXNCTR_Msk & ((value) << PIO_TNCR_TXNCTR_Pos)))
    03395 /* -------- PIO_PTCR : (PIO Offset: 0x188) Transfer Control Register -------- */
    03396 #define PIO_PTCR_RXTEN (0x1u << 0) /**< \brief (PIO_PTCR) Receiver Transfer Enable */
    03397 #define PIO_PTCR_RXTDIS (0x1u << 1) /**< \brief (PIO_PTCR) Receiver Transfer Disable */
    03398 #define PIO_PTCR_TXTEN (0x1u << 8) /**< \brief (PIO_PTCR) Transmitter Transfer Enable */
    03399 #define PIO_PTCR_TXTDIS (0x1u << 9) /**< \brief (PIO_PTCR) Transmitter Transfer Disable */
    03400 /* -------- PIO_PTSR : (PIO Offset: 0x18C) Transfer Status Register -------- */
    03401 #define PIO_PTSR_RXTEN (0x1u << 0) /**< \brief (PIO_PTSR) Receiver Transfer Enable */
    03402 #define PIO_PTSR_TXTEN (0x1u << 8) /**< \brief (PIO_PTSR) Transmitter Transfer Enable */
    03403
    03404 /*@}*/
    03405
    03406 /* ============================================================================= */
    03407 /**  SOFTWARE API DEFINITION FOR Power Management Controller */
    03408 /* ============================================================================= */
    03409 /** \addtogroup SAM3S8_PMC Power Management Controller */
    03410 /*@{*/
    03411
    03412 #ifndef __ASSEMBLY__
    03413 /** \brief Pmc hardware registers */
    03414 typedef struct {
    03415   WoReg PMC_SCER;      /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */
    03416   WoReg PMC_SCDR;      /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */
    03417   RoReg PMC_SCSR;      /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */
    03418   RoReg Reserved1[1];
    03419   WoReg PMC_PCER0;     /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */
    03420   WoReg PMC_PCDR0;     /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */
    03421   RoReg PMC_PCSR0;     /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */
    03422   RoReg Reserved2[1];
    03423   RwReg CKGR_MOR;      /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */
    03424   RoReg CKGR_MCFR;     /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */
    03425   RwReg CKGR_PLLAR;    /**< \brief (Pmc Offset: 0x0028) PLLA Register */
    03426   RwReg CKGR_PLLBR;    /**< \brief (Pmc Offset: 0x002C) PLLB Register */
    03427   RwReg PMC_MCKR;      /**< \brief (Pmc Offset: 0x0030) Master Clock Register */
    03428   RoReg Reserved3[1];
    03429   RwReg PMC_USB;       /**< \brief (Pmc Offset: 0x0038) USB Clock Register */
    03430   RoReg Reserved4[1];
    03431   RwReg PMC_PCK[3];    /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */
    03432   RoReg Reserved5[5];
    03433   WoReg PMC_IER;       /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */
    03434   WoReg PMC_IDR;       /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */
    03435   RoReg PMC_SR;        /**< \brief (Pmc Offset: 0x0068) Status Register */
    03436   RoReg PMC_IMR;       /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */
    03437   RwReg PMC_FSMR;      /**< \brief (Pmc Offset: 0x0070) Fast Startup Mode Register */
    03438   RwReg PMC_FSPR;      /**< \brief (Pmc Offset: 0x0074) Fast Startup Polarity Register */
    03439   WoReg PMC_FOCR;      /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */
    03440   RoReg Reserved6[26];
    03441   RwReg PMC_WPMR;      /**< \brief (Pmc Offset: 0x00E4) Write Protect Mode Register */
    03442   RoReg PMC_WPSR;      /**< \brief (Pmc Offset: 0x00E8) Write Protect Status Register */
    03443   RoReg Reserved7[5];
    03444   WoReg PMC_PCER1;     /**< \brief (Pmc Offset: 0x0100) Peripheral Clock Enable Register 1 */
    03445   WoReg PMC_PCDR1;     /**< \brief (Pmc Offset: 0x0104) Peripheral Clock Disable Register 1 */
    03446   RoReg PMC_PCSR1;     /**< \brief (Pmc Offset: 0x0108) Peripheral Clock Status Register 1 */
    03447   RoReg Reserved8[1];
    03448   RwReg PMC_OCR;       /**< \brief (Pmc Offset: 0x0110) Oscillator Calibration Register */
    03449 } Pmc;
    03450 #endif /* __ASSEMBLY__ */
    03451 /* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */
    03452 #define PMC_SCER_UDP (0x1u << 7) /**< \brief (PMC_SCER) USB Device Port Clock Enable */
    03453 #define PMC_SCER_PCK0 (0x1u << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */
    03454 #define PMC_SCER_PCK1 (0x1u << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */
    03455 #define PMC_SCER_PCK2 (0x1u << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */
    03456 /* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */
    03457 #define PMC_SCDR_UDP (0x1u << 7) /**< \brief (PMC_SCDR) USB Device Port Clock Disable */
    03458 #define PMC_SCDR_PCK0 (0x1u << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */
    03459 #define PMC_SCDR_PCK1 (0x1u << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */
    03460 #define PMC_SCDR_PCK2 (0x1u << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */
    03461 /* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */
    03462 #define PMC_SCSR_UDP (0x1u << 7) /**< \brief (PMC_SCSR) USB Device Port Clock Status */
    03463 #define PMC_SCSR_PCK0 (0x1u << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */
    03464 #define PMC_SCSR_PCK1 (0x1u << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */
    03465 #define PMC_SCSR_PCK2 (0x1u << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */
    03466 /* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */
    03467 #define PMC_PCER0_PID2 (0x1u << 2) /**< \brief (PMC_PCER0) Peripheral Clock 2 Enable */
    03468 #define PMC_PCER0_PID3 (0x1u << 3) /**< \brief (PMC_PCER0) Peripheral Clock 3 Enable */
    03469 #define PMC_PCER0_PID4 (0x1u << 4) /**< \brief (PMC_PCER0) Peripheral Clock 4 Enable */
    03470 #define PMC_PCER0_PID5 (0x1u << 5) /**< \brief (PMC_PCER0) Peripheral Clock 5 Enable */
    03471 #define PMC_PCER0_PID6 (0x1u << 6) /**< \brief (PMC_PCER0) Peripheral Clock 6 Enable */
    03472 #define PMC_PCER0_PID7 (0x1u << 7) /**< \brief (PMC_PCER0) Peripheral Clock 7 Enable */
    03473 #define PMC_PCER0_PID8 (0x1u << 8) /**< \brief (PMC_PCER0) Peripheral Clock 8 Enable */
    03474 #define PMC_PCER0_PID9 (0x1u << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */
    03475 #define PMC_PCER0_PID10 (0x1u << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */
    03476 #define PMC_PCER0_PID11 (0x1u << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */
    03477 #define PMC_PCER0_PID12 (0x1u << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */
    03478 #define PMC_PCER0_PID13 (0x1u << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */
    03479 #define PMC_PCER0_PID14 (0x1u << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */
    03480 #define PMC_PCER0_PID15 (0x1u << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */
    03481 #define PMC_PCER0_PID16 (0x1u << 16) /**< \brief (PMC_PCER0) Peripheral Clock 16 Enable */
    03482 #define PMC_PCER0_PID17 (0x1u << 17) /**< \brief (PMC_PCER0) Peripheral Clock 17 Enable */
    03483 #define PMC_PCER0_PID18 (0x1u << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */
    03484 #define PMC_PCER0_PID19 (0x1u << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */
    03485 #define PMC_PCER0_PID20 (0x1u << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */
    03486 #define PMC_PCER0_PID21 (0x1u << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */
    03487 #define PMC_PCER0_PID22 (0x1u << 22) /**< \brief (PMC_PCER0) Peripheral Clock 22 Enable */
    03488 #define PMC_PCER0_PID23 (0x1u << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */
    03489 #define PMC_PCER0_PID24 (0x1u << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */
    03490 #define PMC_PCER0_PID25 (0x1u << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */
    03491 #define PMC_PCER0_PID26 (0x1u << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */
    03492 #define PMC_PCER0_PID27 (0x1u << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */
    03493 #define PMC_PCER0_PID28 (0x1u << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */
    03494 #define PMC_PCER0_PID29 (0x1u << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */
    03495 #define PMC_PCER0_PID30 (0x1u << 30) /**< \brief (PMC_PCER0) Peripheral Clock 30 Enable */
    03496 #define PMC_PCER0_PID31 (0x1u << 31) /**< \brief (PMC_PCER0) Peripheral Clock 31 Enable */
    03497 /* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */
    03498 #define PMC_PCDR0_PID2 (0x1u << 2) /**< \brief (PMC_PCDR0) Peripheral Clock 2 Disable */
    03499 #define PMC_PCDR0_PID3 (0x1u << 3) /**< \brief (PMC_PCDR0) Peripheral Clock 3 Disable */
    03500 #define PMC_PCDR0_PID4 (0x1u << 4) /**< \brief (PMC_PCDR0) Peripheral Clock 4 Disable */
    03501 #define PMC_PCDR0_PID5 (0x1u << 5) /**< \brief (PMC_PCDR0) Peripheral Clock 5 Disable */
    03502 #define PMC_PCDR0_PID6 (0x1u << 6) /**< \brief (PMC_PCDR0) Peripheral Clock 6 Disable */
    03503 #define PMC_PCDR0_PID7 (0x1u << 7) /**< \brief (PMC_PCDR0) Peripheral Clock 7 Disable */
    03504 #define PMC_PCDR0_PID8 (0x1u << 8) /**< \brief (PMC_PCDR0) Peripheral Clock 8 Disable */
    03505 #define PMC_PCDR0_PID9 (0x1u << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */
    03506 #define PMC_PCDR0_PID10 (0x1u << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */
    03507 #define PMC_PCDR0_PID11 (0x1u << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */
    03508 #define PMC_PCDR0_PID12 (0x1u << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */
    03509 #define PMC_PCDR0_PID13 (0x1u << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */
    03510 #define PMC_PCDR0_PID14 (0x1u << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */
    03511 #define PMC_PCDR0_PID15 (0x1u << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */
    03512 #define PMC_PCDR0_PID16 (0x1u << 16) /**< \brief (PMC_PCDR0) Peripheral Clock 16 Disable */
    03513 #define PMC_PCDR0_PID17 (0x1u << 17) /**< \brief (PMC_PCDR0) Peripheral Clock 17 Disable */
    03514 #define PMC_PCDR0_PID18 (0x1u << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */
    03515 #define PMC_PCDR0_PID19 (0x1u << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */
    03516 #define PMC_PCDR0_PID20 (0x1u << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */
    03517 #define PMC_PCDR0_PID21 (0x1u << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */
    03518 #define PMC_PCDR0_PID22 (0x1u << 22) /**< \brief (PMC_PCDR0) Peripheral Clock 22 Disable */
    03519 #define PMC_PCDR0_PID23 (0x1u << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */
    03520 #define PMC_PCDR0_PID24 (0x1u << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */
    03521 #define PMC_PCDR0_PID25 (0x1u << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */
    03522 #define PMC_PCDR0_PID26 (0x1u << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */
    03523 #define PMC_PCDR0_PID27 (0x1u << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */
    03524 #define PMC_PCDR0_PID28 (0x1u << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */
    03525 #define PMC_PCDR0_PID29 (0x1u << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */
    03526 #define PMC_PCDR0_PID30 (0x1u << 30) /**< \brief (PMC_PCDR0) Peripheral Clock 30 Disable */
    03527 #define PMC_PCDR0_PID31 (0x1u << 31) /**< \brief (PMC_PCDR0) Peripheral Clock 31 Disable */
    03528 /* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */
    03529 #define PMC_PCSR0_PID2 (0x1u << 2) /**< \brief (PMC_PCSR0) Peripheral Clock 2 Status */
    03530 #define PMC_PCSR0_PID3 (0x1u << 3) /**< \brief (PMC_PCSR0) Peripheral Clock 3 Status */
    03531 #define PMC_PCSR0_PID4 (0x1u << 4) /**< \brief (PMC_PCSR0) Peripheral Clock 4 Status */
    03532 #define PMC_PCSR0_PID5 (0x1u << 5) /**< \brief (PMC_PCSR0) Peripheral Clock 5 Status */
    03533 #define PMC_PCSR0_PID6 (0x1u << 6) /**< \brief (PMC_PCSR0) Peripheral Clock 6 Status */
    03534 #define PMC_PCSR0_PID7 (0x1u << 7) /**< \brief (PMC_PCSR0) Peripheral Clock 7 Status */
    03535 #define PMC_PCSR0_PID8 (0x1u << 8) /**< \brief (PMC_PCSR0) Peripheral Clock 8 Status */
    03536 #define PMC_PCSR0_PID9 (0x1u << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */
    03537 #define PMC_PCSR0_PID10 (0x1u << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */
    03538 #define PMC_PCSR0_PID11 (0x1u << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */
    03539 #define PMC_PCSR0_PID12 (0x1u << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */
    03540 #define PMC_PCSR0_PID13 (0x1u << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */
    03541 #define PMC_PCSR0_PID14 (0x1u << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */
    03542 #define PMC_PCSR0_PID15 (0x1u << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */
    03543 #define PMC_PCSR0_PID16 (0x1u << 16) /**< \brief (PMC_PCSR0) Peripheral Clock 16 Status */
    03544 #define PMC_PCSR0_PID17 (0x1u << 17) /**< \brief (PMC_PCSR0) Peripheral Clock 17 Status */
    03545 #define PMC_PCSR0_PID18 (0x1u << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */
    03546 #define PMC_PCSR0_PID19 (0x1u << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */
    03547 #define PMC_PCSR0_PID20 (0x1u << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */
    03548 #define PMC_PCSR0_PID21 (0x1u << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */
    03549 #define PMC_PCSR0_PID22 (0x1u << 22) /**< \brief (PMC_PCSR0) Peripheral Clock 22 Status */
    03550 #define PMC_PCSR0_PID23 (0x1u << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */
    03551 #define PMC_PCSR0_PID24 (0x1u << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */
    03552 #define PMC_PCSR0_PID25 (0x1u << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */
    03553 #define PMC_PCSR0_PID26 (0x1u << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */
    03554 #define PMC_PCSR0_PID27 (0x1u << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */
    03555 #define PMC_PCSR0_PID28 (0x1u << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */
    03556 #define PMC_PCSR0_PID29 (0x1u << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */
    03557 #define PMC_PCSR0_PID30 (0x1u << 30) /**< \brief (PMC_PCSR0) Peripheral Clock 30 Status */
    03558 #define PMC_PCSR0_PID31 (0x1u << 31) /**< \brief (PMC_PCSR0) Peripheral Clock 31 Status */
    03559 /* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */
    03560 #define CKGR_MOR_MOSCXTEN (0x1u << 0) /**< \brief (CKGR_MOR) Main Crystal Oscillator Enable */
    03561 #define CKGR_MOR_MOSCXTBY (0x1u << 1) /**< \brief (CKGR_MOR) Main Crystal Oscillator Bypass */
    03562 #define CKGR_MOR_WAITMODE (0x1u << 2) /**< \brief (CKGR_MOR) Wait Mode Command */
    03563 #define CKGR_MOR_MOSCRCEN (0x1u << 3) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Enable */
    03564 #define CKGR_MOR_MOSCRCF_Pos 4
    03565 #define CKGR_MOR_MOSCRCF_Msk (0x7u << CKGR_MOR_MOSCRCF_Pos) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection */
    03566 #define   CKGR_MOR_MOSCRCF_4MHz (0x0u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 4 MHz (default) */
    03567 #define   CKGR_MOR_MOSCRCF_8MHz (0x1u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 8 MHz */
    03568 #define   CKGR_MOR_MOSCRCF_12MHz (0x2u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 12 MHz */
    03569 #define CKGR_MOR_MOSCXTST_Pos 8
    03570 #define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos) /**< \brief (CKGR_MOR) Main Crystal Oscillator Start-up Time */
    03571 #define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos)))
    03572 #define CKGR_MOR_KEY_Pos 16
    03573 #define CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos) /**< \brief (CKGR_MOR) Password */
    03574 #define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos)))
    03575 #define CKGR_MOR_MOSCSEL (0x1u << 24) /**< \brief (CKGR_MOR) Main Oscillator Selection */
    03576 #define CKGR_MOR_CFDEN (0x1u << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */
    03577 /* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */
    03578 #define CKGR_MCFR_MAINF_Pos 0
    03579 #define CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos) /**< \brief (CKGR_MCFR) Main Clock Frequency */
    03580 #define CKGR_MCFR_MAINFRDY (0x1u << 16) /**< \brief (CKGR_MCFR) Main Clock Ready */
    03581 /* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */
    03582 #define CKGR_PLLAR_DIVA_Pos 0
    03583 #define CKGR_PLLAR_DIVA_Msk (0xffu << CKGR_PLLAR_DIVA_Pos) /**< \brief (CKGR_PLLAR) Divider */
    03584 #define CKGR_PLLAR_DIVA(value) ((CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos)))
    03585 #define CKGR_PLLAR_PLLACOUNT_Pos 8
    03586 #define CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos) /**< \brief (CKGR_PLLAR) PLLA Counter */
    03587 #define CKGR_PLLAR_PLLACOUNT(value) ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos)))
    03588 #define CKGR_PLLAR_MULA_Pos 16
    03589 #define CKGR_PLLAR_MULA_Msk (0x7ffu << CKGR_PLLAR_MULA_Pos) /**< \brief (CKGR_PLLAR) PLLA Multiplier */
    03590 #define CKGR_PLLAR_MULA(value) ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos)))
    03591 #define CKGR_PLLAR_STUCKTO1 (0x1u << 29) /**< \brief (CKGR_PLLAR)  */
    03592 /* -------- CKGR_PLLBR : (PMC Offset: 0x002C) PLLB Register -------- */
    03593 #define CKGR_PLLBR_DIVB_Pos 0
    03594 #define CKGR_PLLBR_DIVB_Msk (0xffu << CKGR_PLLBR_DIVB_Pos) /**< \brief (CKGR_PLLBR) Divider */
    03595 #define CKGR_PLLBR_DIVB(value) ((CKGR_PLLBR_DIVB_Msk & ((value) << CKGR_PLLBR_DIVB_Pos)))
    03596 #define CKGR_PLLBR_PLLBCOUNT_Pos 8
    03597 #define CKGR_PLLBR_PLLBCOUNT_Msk (0x3fu << CKGR_PLLBR_PLLBCOUNT_Pos) /**< \brief (CKGR_PLLBR) PLLB Counter */
    03598 #define CKGR_PLLBR_PLLBCOUNT(value) ((CKGR_PLLBR_PLLBCOUNT_Msk & ((value) << CKGR_PLLBR_PLLBCOUNT_Pos)))
    03599 #define CKGR_PLLBR_MULB_Pos 16
    03600 #define CKGR_PLLBR_MULB_Msk (0x7ffu << CKGR_PLLBR_MULB_Pos) /**< \brief (CKGR_PLLBR) PLLB Multiplier */
    03601 #define CKGR_PLLBR_MULB(value) ((CKGR_PLLBR_MULB_Msk & ((value) << CKGR_PLLBR_MULB_Pos)))
    03602 /* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */
    03603 #define PMC_MCKR_CSS_Pos 0
    03604 #define PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos) /**< \brief (PMC_MCKR) Master Clock Source Selection */
    03605 #define   PMC_MCKR_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */
    03606 #define   PMC_MCKR_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_MCKR) Main Clock is selected */
    03607 #define   PMC_MCKR_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */
    03608 #define   PMC_MCKR_CSS_PLLB_CLK (0x3u << 0) /**< \brief (PMC_MCKR) PLLB Clock is selected */
    03609 #define PMC_MCKR_PRES_Pos 4
    03610 #define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) /**< \brief (PMC_MCKR) Processor Clock Prescaler */
    03611 #define   PMC_MCKR_PRES_CLK (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */
    03612 #define   PMC_MCKR_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */
    03613 #define   PMC_MCKR_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */
    03614 #define   PMC_MCKR_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */
    03615 #define   PMC_MCKR_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */
    03616 #define   PMC_MCKR_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */
    03617 #define   PMC_MCKR_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */
    03618 #define   PMC_MCKR_PRES_CLK_3 (0x7u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 3 */
    03619 #define PMC_MCKR_PLLADIV2 (0x1u << 12) /**< \brief (PMC_MCKR) PLLA Divisor by 2 */
    03620 #define PMC_MCKR_PLLBDIV2 (0x1u << 13) /**< \brief (PMC_MCKR) PLLB Divisor by 2 */
    03621 /* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */
    03622 #define PMC_USB_USBS (0x1u << 0) /**< \brief (PMC_USB) USB Input Clock Selection */
    03623 #define PMC_USB_USBDIV_Pos 8
    03624 #define PMC_USB_USBDIV_Msk (0xfu << PMC_USB_USBDIV_Pos) /**< \brief (PMC_USB) Divider for USB Clock. */
    03625 #define PMC_USB_USBDIV(value) ((PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos)))
    03626 /* -------- PMC_PCK[3] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */
    03627 #define PMC_PCK_CSS_Pos 0
    03628 #define PMC_PCK_CSS_Msk (0x7u << PMC_PCK_CSS_Pos) /**< \brief (PMC_PCK[3]) Master Clock Source Selection */
    03629 #define   PMC_PCK_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK[3]) Slow Clock is selected */
    03630 #define   PMC_PCK_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK[3]) Main Clock is selected */
    03631 #define   PMC_PCK_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK[3]) PLLA Clock is selected */
    03632 #define   PMC_PCK_CSS_PLLB_CLK (0x3u << 0) /**< \brief (PMC_PCK[3]) PLLB Clock is selected */
    03633 #define   PMC_PCK_CSS_MCK (0x4u << 0) /**< \brief (PMC_PCK[3]) Master Clock is selected */
    03634 #define PMC_PCK_PRES_Pos 4
    03635 #define PMC_PCK_PRES_Msk (0x7u << PMC_PCK_PRES_Pos) /**< \brief (PMC_PCK[3]) Programmable Clock Prescaler */
    03636 #define   PMC_PCK_PRES_CLK (0x0u << 4) /**< \brief (PMC_PCK[3]) Selected clock */
    03637 #define   PMC_PCK_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 2 */
    03638 #define   PMC_PCK_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 4 */
    03639 #define   PMC_PCK_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 8 */
    03640 #define   PMC_PCK_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 16 */
    03641 #define   PMC_PCK_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 32 */
    03642 #define   PMC_PCK_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 64 */
    03643 /* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */
    03644 #define PMC_IER_MOSCXTS (0x1u << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */
    03645 #define PMC_IER_LOCKA (0x1u << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */
    03646 #define PMC_IER_LOCKB (0x1u << 2) /**< \brief (PMC_IER) PLLB Lock Interrupt Enable */
    03647 #define PMC_IER_MCKRDY (0x1u << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */
    03648 #define PMC_IER_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */
    03649 #define PMC_IER_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */
    03650 #define PMC_IER_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */
    03651 #define PMC_IER_MOSCSELS (0x1u << 16) /**< \brief (PMC_IER) Main Oscillator Selection Status Interrupt Enable */
    03652 #define PMC_IER_MOSCRCS (0x1u << 17) /**< \brief (PMC_IER) Main On-Chip RC Status Interrupt Enable */
    03653 #define PMC_IER_CFDEV (0x1u << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */
    03654 /* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */
    03655 #define PMC_IDR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable */
    03656 #define PMC_IDR_LOCKA (0x1u << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */
    03657 #define PMC_IDR_LOCKB (0x1u << 2) /**< \brief (PMC_IDR) PLLB Lock Interrupt Disable */
    03658 #define PMC_IDR_MCKRDY (0x1u << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */
    03659 #define PMC_IDR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */
    03660 #define PMC_IDR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */
    03661 #define PMC_IDR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */
    03662 #define PMC_IDR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IDR) Main Oscillator Selection Status Interrupt Disable */
    03663 #define PMC_IDR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IDR) Main On-Chip RC Status Interrupt Disable */
    03664 #define PMC_IDR_CFDEV (0x1u << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */
    03665 /* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */
    03666 #define PMC_SR_MOSCXTS (0x1u << 0) /**< \brief (PMC_SR) Main XTAL Oscillator Status */
    03667 #define PMC_SR_LOCKA (0x1u << 1) /**< \brief (PMC_SR) PLLA Lock Status */
    03668 #define PMC_SR_LOCKB (0x1u << 2) /**< \brief (PMC_SR) PLLB Lock Status */
    03669 #define PMC_SR_MCKRDY (0x1u << 3) /**< \brief (PMC_SR) Master Clock Status */
    03670 #define PMC_SR_OSCSELS (0x1u << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */
    03671 #define PMC_SR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */
    03672 #define PMC_SR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */
    03673 #define PMC_SR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */
    03674 #define PMC_SR_MOSCSELS (0x1u << 16) /**< \brief (PMC_SR) Main Oscillator Selection Status */
    03675 #define PMC_SR_MOSCRCS (0x1u << 17) /**< \brief (PMC_SR) Main On-Chip RC Oscillator Status */
    03676 #define PMC_SR_CFDEV (0x1u << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */
    03677 #define PMC_SR_CFDS (0x1u << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */
    03678 #define PMC_SR_FOS (0x1u << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */
    03679 /* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */
    03680 #define PMC_IMR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask */
    03681 #define PMC_IMR_LOCKA (0x1u << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */
    03682 #define PMC_IMR_LOCKB (0x1u << 2) /**< \brief (PMC_IMR) PLLB Lock Interrupt Mask */
    03683 #define PMC_IMR_MCKRDY (0x1u << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */
    03684 #define PMC_IMR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */
    03685 #define PMC_IMR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */
    03686 #define PMC_IMR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */
    03687 #define PMC_IMR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IMR) Main Oscillator Selection Status Interrupt Mask */
    03688 #define PMC_IMR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IMR) Main On-Chip RC Status Interrupt Mask */
    03689 #define PMC_IMR_CFDEV (0x1u << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */
    03690 /* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */
    03691 #define PMC_FSMR_FSTT0 (0x1u << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */
    03692 #define PMC_FSMR_FSTT1 (0x1u << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */
    03693 #define PMC_FSMR_FSTT2 (0x1u << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */
    03694 #define PMC_FSMR_FSTT3 (0x1u << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */
    03695 #define PMC_FSMR_FSTT4 (0x1u << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */
    03696 #define PMC_FSMR_FSTT5 (0x1u << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */
    03697 #define PMC_FSMR_FSTT6 (0x1u << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */
    03698 #define PMC_FSMR_FSTT7 (0x1u << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */
    03699 #define PMC_FSMR_FSTT8 (0x1u << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */
    03700 #define PMC_FSMR_FSTT9 (0x1u << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */
    03701 #define PMC_FSMR_FSTT10 (0x1u << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */
    03702 #define PMC_FSMR_FSTT11 (0x1u << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */
    03703 #define PMC_FSMR_FSTT12 (0x1u << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */
    03704 #define PMC_FSMR_FSTT13 (0x1u << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */
    03705 #define PMC_FSMR_FSTT14 (0x1u << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */
    03706 #define PMC_FSMR_FSTT15 (0x1u << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */
    03707 #define PMC_FSMR_RTTAL (0x1u << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */
    03708 #define PMC_FSMR_RTCAL (0x1u << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */
    03709 #define PMC_FSMR_USBAL (0x1u << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */
    03710 #define PMC_FSMR_LPM (0x1u << 20) /**< \brief (PMC_FSMR) Low Power Mode */
    03711 /* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */
    03712 #define PMC_FSPR_FSTP0 (0x1u << 0) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
    03713 #define PMC_FSPR_FSTP1 (0x1u << 1) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
    03714 #define PMC_FSPR_FSTP2 (0x1u << 2) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
    03715 #define PMC_FSPR_FSTP3 (0x1u << 3) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
    03716 #define PMC_FSPR_FSTP4 (0x1u << 4) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
    03717 #define PMC_FSPR_FSTP5 (0x1u << 5) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
    03718 #define PMC_FSPR_FSTP6 (0x1u << 6) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
    03719 #define PMC_FSPR_FSTP7 (0x1u << 7) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
    03720 #define PMC_FSPR_FSTP8 (0x1u << 8) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
    03721 #define PMC_FSPR_FSTP9 (0x1u << 9) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
    03722 #define PMC_FSPR_FSTP10 (0x1u << 10) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
    03723 #define PMC_FSPR_FSTP11 (0x1u << 11) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
    03724 #define PMC_FSPR_FSTP12 (0x1u << 12) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
    03725 #define PMC_FSPR_FSTP13 (0x1u << 13) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
    03726 #define PMC_FSPR_FSTP14 (0x1u << 14) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
    03727 #define PMC_FSPR_FSTP15 (0x1u << 15) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
    03728 /* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */
    03729 #define PMC_FOCR_FOCLR (0x1u << 0) /**< \brief (PMC_FOCR) Fault Output Clear */
    03730 /* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protect Mode Register -------- */
    03731 #define PMC_WPMR_WPEN (0x1u << 0) /**< \brief (PMC_WPMR) Write Protect Enable */
    03732 #define PMC_WPMR_WPKEY_Pos 8
    03733 #define PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos) /**< \brief (PMC_WPMR) Write Protect KEY */
    03734 #define PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos)))
    03735 /* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protect Status Register -------- */
    03736 #define PMC_WPSR_WPVS (0x1u << 0) /**< \brief (PMC_WPSR) Write Protect Violation Status */
    03737 #define PMC_WPSR_WPVSRC_Pos 8
    03738 #define PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos) /**< \brief (PMC_WPSR) Write Protect Violation Source */
    03739 /* -------- PMC_PCER1 : (PMC Offset: 0x0100) Peripheral Clock Enable Register 1 -------- */
    03740 #define PMC_PCER1_PID32 (0x1u << 0) /**< \brief (PMC_PCER1) Peripheral Clock 32 Enable */
    03741 #define PMC_PCER1_PID33 (0x1u << 1) /**< \brief (PMC_PCER1) Peripheral Clock 33 Enable */
    03742 #define PMC_PCER1_PID34 (0x1u << 2) /**< \brief (PMC_PCER1) Peripheral Clock 34 Enable */
    03743 #define PMC_PCER1_PID35 (0x1u << 3) /**< \brief (PMC_PCER1) Peripheral Clock 35 Enable */
    03744 #define PMC_PCER1_PID36 (0x1u << 4) /**< \brief (PMC_PCER1) Peripheral Clock 36 Enable */
    03745 #define PMC_PCER1_PID37 (0x1u << 5) /**< \brief (PMC_PCER1) Peripheral Clock 37 Enable */
    03746 #define PMC_PCER1_PID38 (0x1u << 6) /**< \brief (PMC_PCER1) Peripheral Clock 38 Enable */
    03747 #define PMC_PCER1_PID39 (0x1u << 7) /**< \brief (PMC_PCER1) Peripheral Clock 39 Enable */
    03748 #define PMC_PCER1_PID40 (0x1u << 8) /**< \brief (PMC_PCER1) Peripheral Clock 40 Enable */
    03749 #define PMC_PCER1_PID41 (0x1u << 9) /**< \brief (PMC_PCER1) Peripheral Clock 41 Enable */
    03750 #define PMC_PCER1_PID42 (0x1u << 10) /**< \brief (PMC_PCER1) Peripheral Clock 42 Enable */
    03751 #define PMC_PCER1_PID43 (0x1u << 11) /**< \brief (PMC_PCER1) Peripheral Clock 43 Enable */
    03752 #define PMC_PCER1_PID44 (0x1u << 12) /**< \brief (PMC_PCER1) Peripheral Clock 44 Enable */
    03753 #define PMC_PCER1_PID45 (0x1u << 13) /**< \brief (PMC_PCER1) Peripheral Clock 45 Enable */
    03754 #define PMC_PCER1_PID46 (0x1u << 14) /**< \brief (PMC_PCER1) Peripheral Clock 46 Enable */
    03755 #define PMC_PCER1_PID47 (0x1u << 15) /**< \brief (PMC_PCER1) Peripheral Clock 47 Enable */
    03756 #define PMC_PCER1_PID48 (0x1u << 16) /**< \brief (PMC_PCER1) Peripheral Clock 48 Enable */
    03757 #define PMC_PCER1_PID49 (0x1u << 17) /**< \brief (PMC_PCER1) Peripheral Clock 49 Enable */
    03758 #define PMC_PCER1_PID50 (0x1u << 18) /**< \brief (PMC_PCER1) Peripheral Clock 50 Enable */
    03759 #define PMC_PCER1_PID51 (0x1u << 19) /**< \brief (PMC_PCER1) Peripheral Clock 51 Enable */
    03760 #define PMC_PCER1_PID52 (0x1u << 20) /**< \brief (PMC_PCER1) Peripheral Clock 52 Enable */
    03761 #define PMC_PCER1_PID53 (0x1u << 21) /**< \brief (PMC_PCER1) Peripheral Clock 53 Enable */
    03762 #define PMC_PCER1_PID54 (0x1u << 22) /**< \brief (PMC_PCER1) Peripheral Clock 54 Enable */
    03763 #define PMC_PCER1_PID55 (0x1u << 23) /**< \brief (PMC_PCER1) Peripheral Clock 55 Enable */
    03764 #define PMC_PCER1_PID56 (0x1u << 24) /**< \brief (PMC_PCER1) Peripheral Clock 56 Enable */
    03765 #define PMC_PCER1_PID57 (0x1u << 25) /**< \brief (PMC_PCER1) Peripheral Clock 57 Enable */
    03766 #define PMC_PCER1_PID58 (0x1u << 26) /**< \brief (PMC_PCER1) Peripheral Clock 58 Enable */
    03767 #define PMC_PCER1_PID59 (0x1u << 27) /**< \brief (PMC_PCER1) Peripheral Clock 59 Enable */
    03768 #define PMC_PCER1_PID60 (0x1u << 28) /**< \brief (PMC_PCER1) Peripheral Clock 60 Enable */
    03769 #define PMC_PCER1_PID61 (0x1u << 29) /**< \brief (PMC_PCER1) Peripheral Clock 61 Enable */
    03770 #define PMC_PCER1_PID62 (0x1u << 30) /**< \brief (PMC_PCER1) Peripheral Clock 62 Enable */
    03771 #define PMC_PCER1_PID63 (0x1u << 31) /**< \brief (PMC_PCER1) Peripheral Clock 63 Enable */
    03772 /* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */
    03773 #define PMC_PCDR1_PID32 (0x1u << 0) /**< \brief (PMC_PCDR1) Peripheral Clock 32 Disable */
    03774 #define PMC_PCDR1_PID33 (0x1u << 1) /**< \brief (PMC_PCDR1) Peripheral Clock 33 Disable */
    03775 #define PMC_PCDR1_PID34 (0x1u << 2) /**< \brief (PMC_PCDR1) Peripheral Clock 34 Disable */
    03776 #define PMC_PCDR1_PID35 (0x1u << 3) /**< \brief (PMC_PCDR1) Peripheral Clock 35 Disable */
    03777 #define PMC_PCDR1_PID36 (0x1u << 4) /**< \brief (PMC_PCDR1) Peripheral Clock 36 Disable */
    03778 #define PMC_PCDR1_PID37 (0x1u << 5) /**< \brief (PMC_PCDR1) Peripheral Clock 37 Disable */
    03779 #define PMC_PCDR1_PID38 (0x1u << 6) /**< \brief (PMC_PCDR1) Peripheral Clock 38 Disable */
    03780 #define PMC_PCDR1_PID39 (0x1u << 7) /**< \brief (PMC_PCDR1) Peripheral Clock 39 Disable */
    03781 #define PMC_PCDR1_PID40 (0x1u << 8) /**< \brief (PMC_PCDR1) Peripheral Clock 40 Disable */
    03782 #define PMC_PCDR1_PID41 (0x1u << 9) /**< \brief (PMC_PCDR1) Peripheral Clock 41 Disable */
    03783 #define PMC_PCDR1_PID42 (0x1u << 10) /**< \brief (PMC_PCDR1) Peripheral Clock 42 Disable */
    03784 #define PMC_PCDR1_PID43 (0x1u << 11) /**< \brief (PMC_PCDR1) Peripheral Clock 43 Disable */
    03785 #define PMC_PCDR1_PID44 (0x1u << 12) /**< \brief (PMC_PCDR1) Peripheral Clock 44 Disable */
    03786 #define PMC_PCDR1_PID45 (0x1u << 13) /**< \brief (PMC_PCDR1) Peripheral Clock 45 Disable */
    03787 #define PMC_PCDR1_PID46 (0x1u << 14) /**< \brief (PMC_PCDR1) Peripheral Clock 46 Disable */
    03788 #define PMC_PCDR1_PID47 (0x1u << 15) /**< \brief (PMC_PCDR1) Peripheral Clock 47 Disable */
    03789 #define PMC_PCDR1_PID48 (0x1u << 16) /**< \brief (PMC_PCDR1) Peripheral Clock 48 Disable */
    03790 #define PMC_PCDR1_PID49 (0x1u << 17) /**< \brief (PMC_PCDR1) Peripheral Clock 49 Disable */
    03791 #define PMC_PCDR1_PID50 (0x1u << 18) /**< \brief (PMC_PCDR1) Peripheral Clock 50 Disable */
    03792 #define PMC_PCDR1_PID51 (0x1u << 19) /**< \brief (PMC_PCDR1) Peripheral Clock 51 Disable */
    03793 #define PMC_PCDR1_PID52 (0x1u << 20) /**< \brief (PMC_PCDR1) Peripheral Clock 52 Disable */
    03794 #define PMC_PCDR1_PID53 (0x1u << 21) /**< \brief (PMC_PCDR1) Peripheral Clock 53 Disable */
    03795 #define PMC_PCDR1_PID54 (0x1u << 22) /**< \brief (PMC_PCDR1) Peripheral Clock 54 Disable */
    03796 #define PMC_PCDR1_PID55 (0x1u << 23) /**< \brief (PMC_PCDR1) Peripheral Clock 55 Disable */
    03797 #define PMC_PCDR1_PID56 (0x1u << 24) /**< \brief (PMC_PCDR1) Peripheral Clock 56 Disable */
    03798 #define PMC_PCDR1_PID57 (0x1u << 25) /**< \brief (PMC_PCDR1) Peripheral Clock 57 Disable */
    03799 #define PMC_PCDR1_PID58 (0x1u << 26) /**< \brief (PMC_PCDR1) Peripheral Clock 58 Disable */
    03800 #define PMC_PCDR1_PID59 (0x1u << 27) /**< \brief (PMC_PCDR1) Peripheral Clock 59 Disable */
    03801 #define PMC_PCDR1_PID60 (0x1u << 28) /**< \brief (PMC_PCDR1) Peripheral Clock 60 Disable */
    03802 #define PMC_PCDR1_PID61 (0x1u << 29) /**< \brief (PMC_PCDR1) Peripheral Clock 61 Disable */
    03803 #define PMC_PCDR1_PID62 (0x1u << 30) /**< \brief (PMC_PCDR1) Peripheral Clock 62 Disable */
    03804 #define PMC_PCDR1_PID63 (0x1u << 31) /**< \brief (PMC_PCDR1) Peripheral Clock 63 Disable */
    03805 /* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */
    03806 #define PMC_PCSR1_PID32 (0x1u << 0) /**< \brief (PMC_PCSR1) Peripheral Clock 32 Status */
    03807 #define PMC_PCSR1_PID33 (0x1u << 1) /**< \brief (PMC_PCSR1) Peripheral Clock 33 Status */
    03808 #define PMC_PCSR1_PID34 (0x1u << 2) /**< \brief (PMC_PCSR1) Peripheral Clock 34 Status */
    03809 #define PMC_PCSR1_PID35 (0x1u << 3) /**< \brief (PMC_PCSR1) Peripheral Clock 35 Status */
    03810 #define PMC_PCSR1_PID36 (0x1u << 4) /**< \brief (PMC_PCSR1) Peripheral Clock 36 Status */
    03811 #define PMC_PCSR1_PID37 (0x1u << 5) /**< \brief (PMC_PCSR1) Peripheral Clock 37 Status */
    03812 #define PMC_PCSR1_PID38 (0x1u << 6) /**< \brief (PMC_PCSR1) Peripheral Clock 38 Status */
    03813 #define PMC_PCSR1_PID39 (0x1u << 7) /**< \brief (PMC_PCSR1) Peripheral Clock 39 Status */
    03814 #define PMC_PCSR1_PID40 (0x1u << 8) /**< \brief (PMC_PCSR1) Peripheral Clock 40 Status */
    03815 #define PMC_PCSR1_PID41 (0x1u << 9) /**< \brief (PMC_PCSR1) Peripheral Clock 41 Status */
    03816 #define PMC_PCSR1_PID42 (0x1u << 10) /**< \brief (PMC_PCSR1) Peripheral Clock 42 Status */
    03817 #define PMC_PCSR1_PID43 (0x1u << 11) /**< \brief (PMC_PCSR1) Peripheral Clock 43 Status */
    03818 #define PMC_PCSR1_PID44 (0x1u << 12) /**< \brief (PMC_PCSR1) Peripheral Clock 44 Status */
    03819 #define PMC_PCSR1_PID45 (0x1u << 13) /**< \brief (PMC_PCSR1) Peripheral Clock 45 Status */
    03820 #define PMC_PCSR1_PID46 (0x1u << 14) /**< \brief (PMC_PCSR1) Peripheral Clock 46 Status */
    03821 #define PMC_PCSR1_PID47 (0x1u << 15) /**< \brief (PMC_PCSR1) Peripheral Clock 47 Status */
    03822 #define PMC_PCSR1_PID48 (0x1u << 16) /**< \brief (PMC_PCSR1) Peripheral Clock 48 Status */
    03823 #define PMC_PCSR1_PID49 (0x1u << 17) /**< \brief (PMC_PCSR1) Peripheral Clock 49 Status */
    03824 #define PMC_PCSR1_PID50 (0x1u << 18) /**< \brief (PMC_PCSR1) Peripheral Clock 50 Status */
    03825 #define PMC_PCSR1_PID51 (0x1u << 19) /**< \brief (PMC_PCSR1) Peripheral Clock 51 Status */
    03826 #define PMC_PCSR1_PID52 (0x1u << 20) /**< \brief (PMC_PCSR1) Peripheral Clock 52 Status */
    03827 #define PMC_PCSR1_PID53 (0x1u << 21) /**< \brief (PMC_PCSR1) Peripheral Clock 53 Status */
    03828 #define PMC_PCSR1_PID54 (0x1u << 22) /**< \brief (PMC_PCSR1) Peripheral Clock 54 Status */
    03829 #define PMC_PCSR1_PID55 (0x1u << 23) /**< \brief (PMC_PCSR1) Peripheral Clock 55 Status */
    03830 #define PMC_PCSR1_PID56 (0x1u << 24) /**< \brief (PMC_PCSR1) Peripheral Clock 56 Status */
    03831 #define PMC_PCSR1_PID57 (0x1u << 25) /**< \brief (PMC_PCSR1) Peripheral Clock 57 Status */
    03832 #define PMC_PCSR1_PID58 (0x1u << 26) /**< \brief (PMC_PCSR1) Peripheral Clock 58 Status */
    03833 #define PMC_PCSR1_PID59 (0x1u << 27) /**< \brief (PMC_PCSR1) Peripheral Clock 59 Status */
    03834 #define PMC_PCSR1_PID60 (0x1u << 28) /**< \brief (PMC_PCSR1) Peripheral Clock 60 Status */
    03835 #define PMC_PCSR1_PID61 (0x1u << 29) /**< \brief (PMC_PCSR1) Peripheral Clock 61 Status */
    03836 #define PMC_PCSR1_PID62 (0x1u << 30) /**< \brief (PMC_PCSR1) Peripheral Clock 62 Status */
    03837 #define PMC_PCSR1_PID63 (0x1u << 31) /**< \brief (PMC_PCSR1) Peripheral Clock 63 Status */
    03838 /* -------- PMC_OCR : (PMC Offset: 0x0110) Oscillator Calibration Register -------- */
    03839 #define PMC_OCR_CAL4_Pos 0
    03840 #define PMC_OCR_CAL4_Msk (0x7fu << PMC_OCR_CAL4_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 4 Mhz */
    03841 #define PMC_OCR_CAL4(value) ((PMC_OCR_CAL4_Msk & ((value) << PMC_OCR_CAL4_Pos)))
    03842 #define PMC_OCR_SEL4 (0x1u << 7) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 4 Mhz */
    03843 #define PMC_OCR_CAL8_Pos 8
    03844 #define PMC_OCR_CAL8_Msk (0x7fu << PMC_OCR_CAL8_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 8 Mhz */
    03845 #define PMC_OCR_CAL8(value) ((PMC_OCR_CAL8_Msk & ((value) << PMC_OCR_CAL8_Pos)))
    03846 #define PMC_OCR_SEL8 (0x1u << 15) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 8 Mhz */
    03847 #define PMC_OCR_CAL12_Pos 16
    03848 #define PMC_OCR_CAL12_Msk (0x7fu << PMC_OCR_CAL12_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 12 Mhz */
    03849 #define PMC_OCR_CAL12(value) ((PMC_OCR_CAL12_Msk & ((value) << PMC_OCR_CAL12_Pos)))
    03850 #define PMC_OCR_SEL12 (0x1u << 23) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 12 Mhz */
    03851
    03852 /*@}*/
    03853
    03854 /* ============================================================================= */
    03855 /**  SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */
    03856 /* ============================================================================= */
    03857 /** \addtogroup SAM3S8_PWM Pulse Width Modulation Controller */
    03858 /*@{*/
    03859
    03860 #ifndef __ASSEMBLY__
    03861 /** \brief PwmCh_num hardware registers */
    03862 typedef struct {
    03863   RwReg      PWM_CMR;       /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */
    03864   RwReg      PWM_CDTY;      /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */
    03865   RwReg      PWM_CDTYUPD;   /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */
    03866   RwReg      PWM_CPRD;      /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */
    03867   RwReg      PWM_CPRDUPD;   /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */
    03868   RwReg      PWM_CCNT;      /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */
    03869   RwReg      PWM_DT;        /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */
    03870   RwReg      PWM_DTUPD;     /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */
    03871 } PwmCh_num;
    03872 /** \brief PwmCmp hardware registers */
    03873 typedef struct {
    03874   RwReg      PWM_CMPV;      /**< \brief (PwmCmp Offset: 0x0) PWM Comparison 0 Value Register */
    03875   RwReg      PWM_CMPVUPD;   /**< \brief (PwmCmp Offset: 0x4) PWM Comparison 0 Value Update Register */
    03876   RwReg      PWM_CMPM;      /**< \brief (PwmCmp Offset: 0x8) PWM Comparison 0 Mode Register */
    03877   RwReg      PWM_CMPMUPD;   /**< \brief (PwmCmp Offset: 0xC) PWM Comparison 0 Mode Update Register */
    03878 } PwmCmp;
    03879 /** \brief Pwm hardware registers */
    03880 #define PWMCMP_NUMBER 8
    03881 #define PWMCH_NUM_NUMBER 4
    03882 typedef struct {
    03883   RwReg      PWM_CLK;       /**< \brief (Pwm Offset: 0x00) PWM Clock Register */
    03884   WoReg      PWM_ENA;       /**< \brief (Pwm Offset: 0x04) PWM Enable Register */
    03885   WoReg      PWM_DIS;       /**< \brief (Pwm Offset: 0x08) PWM Disable Register */
    03886   RoReg      PWM_SR;        /**< \brief (Pwm Offset: 0x0C) PWM Status Register */
    03887   WoReg      PWM_IER1;      /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */
    03888   WoReg      PWM_IDR1;      /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */
    03889   RoReg      PWM_IMR1;      /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */
    03890   RoReg      PWM_ISR1;      /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */
    03891   RwReg      PWM_SCM;       /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */
    03892   RoReg      Reserved1[1];
    03893   RwReg      PWM_SCUC;      /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */
    03894   RwReg      PWM_SCUP;      /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */
    03895   WoReg      PWM_SCUPUPD;   /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */
    03896   WoReg      PWM_IER2;      /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */
    03897   WoReg      PWM_IDR2;      /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */
    03898   RoReg      PWM_IMR2;      /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */
    03899   RoReg      PWM_ISR2;      /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */
    03900   RwReg      PWM_OOV;       /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */
    03901   RwReg      PWM_OS;        /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */
    03902   WoReg      PWM_OSS;       /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */
    03903   WoReg      PWM_OSC;       /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */
    03904   WoReg      PWM_OSSUPD;    /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */
    03905   WoReg      PWM_OSCUPD;    /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */
    03906   RwReg      PWM_FMR;       /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */
    03907   RoReg      PWM_FSR;       /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */
    03908   WoReg      PWM_FCR;       /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */
    03909   RwReg      PWM_FPV;       /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register */
    03910   RwReg      PWM_FPE;       /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register */
    03911   RoReg      Reserved2[3];
    03912   RwReg      PWM_ELMR[2];   /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */
    03913   RoReg      Reserved3[11];
    03914   RwReg      PWM_SMMR;      /**< \brief (Pwm Offset: 0xB0) PWM Stepper Motor Mode Register */
    03915   RoReg      Reserved4[12];
    03916   WoReg      PWM_WPCR;      /**< \brief (Pwm Offset: 0xE4) PWM Write Protect Control Register */
    03917   RoReg      PWM_WPSR;      /**< \brief (Pwm Offset: 0xE8) PWM Write Protect Status Register */
    03918   RoReg      Reserved5[5];
    03919   RwReg      PWM_RPR;       /**< \brief (Pwm Offset: 0x100) Receive Pointer Register */
    03920   RwReg      PWM_RCR;       /**< \brief (Pwm Offset: 0x104) Receive Counter Register */
    03921   RwReg      PWM_TPR;       /**< \brief (Pwm Offset: 0x108) Transmit Pointer Register */
    03922   RwReg      PWM_TCR;       /**< \brief (Pwm Offset: 0x10C) Transmit Counter Register */
    03923   RwReg      PWM_RNPR;      /**< \brief (Pwm Offset: 0x110) Receive Next Pointer Register */
    03924   RwReg      PWM_RNCR;      /**< \brief (Pwm Offset: 0x114) Receive Next Counter Register */
    03925   RwReg      PWM_TNPR;      /**< \brief (Pwm Offset: 0x118) Transmit Next Pointer Register */
    03926   RwReg      PWM_TNCR;      /**< \brief (Pwm Offset: 0x11C) Transmit Next Counter Register */
    03927   WoReg      PWM_PTCR;      /**< \brief (Pwm Offset: 0x120) Transfer Control Register */
    03928   RoReg      PWM_PTSR;      /**< \brief (Pwm Offset: 0x124) Transfer Status Register */
    03929   RoReg      Reserved6[2];
    03930   PwmCmp     PWM_CMP[PWMCMP_NUMBER]; /**< \brief (Pwm Offset: 0x130) 0 .. 7 */
    03931   RoReg      Reserved7[20];
    03932   PwmCh_num  PWM_CH_NUM[PWMCH_NUM_NUMBER]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 3 */
    03933 } Pwm;
    03934 #endif /* __ASSEMBLY__ */
    03935 /* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */
    03936 #define PWM_CLK_DIVA_Pos 0
    03937 #define PWM_CLK_DIVA_Msk (0xffu << PWM_CLK_DIVA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */
    03938 #define PWM_CLK_DIVA(value) ((PWM_CLK_DIVA_Msk & ((value) << PWM_CLK_DIVA_Pos)))
    03939 #define PWM_CLK_PREA_Pos 8
    03940 #define PWM_CLK_PREA_Msk (0xfu << PWM_CLK_PREA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */
    03941 #define PWM_CLK_PREA(value) ((PWM_CLK_PREA_Msk & ((value) << PWM_CLK_PREA_Pos)))
    03942 #define PWM_CLK_DIVB_Pos 16
    03943 #define PWM_CLK_DIVB_Msk (0xffu << PWM_CLK_DIVB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */
    03944 #define PWM_CLK_DIVB(value) ((PWM_CLK_DIVB_Msk & ((value) << PWM_CLK_DIVB_Pos)))
    03945 #define PWM_CLK_PREB_Pos 24
    03946 #define PWM_CLK_PREB_Msk (0xfu << PWM_CLK_PREB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */
    03947 #define PWM_CLK_PREB(value) ((PWM_CLK_PREB_Msk & ((value) << PWM_CLK_PREB_Pos)))
    03948 /* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */
    03949 #define PWM_ENA_CHID0 (0x1u << 0) /**< \brief (PWM_ENA) Channel ID */
    03950 #define PWM_ENA_CHID1 (0x1u << 1) /**< \brief (PWM_ENA) Channel ID */
    03951 #define PWM_ENA_CHID2 (0x1u << 2) /**< \brief (PWM_ENA) Channel ID */
    03952 #define PWM_ENA_CHID3 (0x1u << 3) /**< \brief (PWM_ENA) Channel ID */
    03953 /* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */
    03954 #define PWM_DIS_CHID0 (0x1u << 0) /**< \brief (PWM_DIS) Channel ID */
    03955 #define PWM_DIS_CHID1 (0x1u << 1) /**< \brief (PWM_DIS) Channel ID */
    03956 #define PWM_DIS_CHID2 (0x1u << 2) /**< \brief (PWM_DIS) Channel ID */
    03957 #define PWM_DIS_CHID3 (0x1u << 3) /**< \brief (PWM_DIS) Channel ID */
    03958 /* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */
    03959 #define PWM_SR_CHID0 (0x1u << 0) /**< \brief (PWM_SR) Channel ID */
    03960 #define PWM_SR_CHID1 (0x1u << 1) /**< \brief (PWM_SR) Channel ID */
    03961 #define PWM_SR_CHID2 (0x1u << 2) /**< \brief (PWM_SR) Channel ID */
    03962 #define PWM_SR_CHID3 (0x1u << 3) /**< \brief (PWM_SR) Channel ID */
    03963 /* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */
    03964 #define PWM_IER1_CHID0 (0x1u << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */
    03965 #define PWM_IER1_CHID1 (0x1u << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */
    03966 #define PWM_IER1_CHID2 (0x1u << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */
    03967 #define PWM_IER1_CHID3 (0x1u << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */
    03968 #define PWM_IER1_FCHID0 (0x1u << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */
    03969 #define PWM_IER1_FCHID1 (0x1u << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */
    03970 #define PWM_IER1_FCHID2 (0x1u << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */
    03971 #define PWM_IER1_FCHID3 (0x1u << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */
    03972 /* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */
    03973 #define PWM_IDR1_CHID0 (0x1u << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */
    03974 #define PWM_IDR1_CHID1 (0x1u << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */
    03975 #define PWM_IDR1_CHID2 (0x1u << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */
    03976 #define PWM_IDR1_CHID3 (0x1u << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */
    03977 #define PWM_IDR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */
    03978 #define PWM_IDR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */
    03979 #define PWM_IDR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */
    03980 #define PWM_IDR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */
    03981 /* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */
    03982 #define PWM_IMR1_CHID0 (0x1u << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */
    03983 #define PWM_IMR1_CHID1 (0x1u << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */
    03984 #define PWM_IMR1_CHID2 (0x1u << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */
    03985 #define PWM_IMR1_CHID3 (0x1u << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */
    03986 #define PWM_IMR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */
    03987 #define PWM_IMR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */
    03988 #define PWM_IMR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */
    03989 #define PWM_IMR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */
    03990 /* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */
    03991 #define PWM_ISR1_CHID0 (0x1u << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */
    03992 #define PWM_ISR1_CHID1 (0x1u << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */
    03993 #define PWM_ISR1_CHID2 (0x1u << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */
    03994 #define PWM_ISR1_CHID3 (0x1u << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */
    03995 #define PWM_ISR1_FCHID0 (0x1u << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */
    03996 #define PWM_ISR1_FCHID1 (0x1u << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */
    03997 #define PWM_ISR1_FCHID2 (0x1u << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */
    03998 #define PWM_ISR1_FCHID3 (0x1u << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */
    03999 /* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */
    04000 #define PWM_SCM_SYNC0 (0x1u << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */
    04001 #define PWM_SCM_SYNC1 (0x1u << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */
    04002 #define PWM_SCM_SYNC2 (0x1u << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */
    04003 #define PWM_SCM_SYNC3 (0x1u << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */
    04004 #define PWM_SCM_UPDM_Pos 16
    04005 #define PWM_SCM_UPDM_Msk (0x3u << PWM_SCM_UPDM_Pos) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */
    04006 #define   PWM_SCM_UPDM_MODE0 (0x0u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and manual update of synchronous channels */
    04007 #define   PWM_SCM_UPDM_MODE1 (0x1u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and automatic update of synchronous channels */
    04008 #define   PWM_SCM_UPDM_MODE2 (0x2u << 16) /**< \brief (PWM_SCM) Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous channels */
    04009 #define PWM_SCM_PTRM (0x1u << 20) /**< \brief (PWM_SCM) PDC Transfer Request Mode */
    04010 #define PWM_SCM_PTRCS_Pos 21
    04011 #define PWM_SCM_PTRCS_Msk (0x7u << PWM_SCM_PTRCS_Pos) /**< \brief (PWM_SCM) PDC Transfer Request Comparison Selection */
    04012 #define PWM_SCM_PTRCS(value) ((PWM_SCM_PTRCS_Msk & ((value) << PWM_SCM_PTRCS_Pos)))
    04013 /* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */
    04014 #define PWM_SCUC_UPDULOCK (0x1u << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */
    04015 /* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */
    04016 #define PWM_SCUP_UPR_Pos 0
    04017 #define PWM_SCUP_UPR_Msk (0xfu << PWM_SCUP_UPR_Pos) /**< \brief (PWM_SCUP) Update Period */
    04018 #define PWM_SCUP_UPR(value) ((PWM_SCUP_UPR_Msk & ((value) << PWM_SCUP_UPR_Pos)))
    04019 #define PWM_SCUP_UPRCNT_Pos 4
    04020 #define PWM_SCUP_UPRCNT_Msk (0xfu << PWM_SCUP_UPRCNT_Pos) /**< \brief (PWM_SCUP) Update Period Counter */
    04021 #define PWM_SCUP_UPRCNT(value) ((PWM_SCUP_UPRCNT_Msk & ((value) << PWM_SCUP_UPRCNT_Pos)))
    04022 /* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */
    04023 #define PWM_SCUPUPD_UPRUPD_Pos 0
    04024 #define PWM_SCUPUPD_UPRUPD_Msk (0xfu << PWM_SCUPUPD_UPRUPD_Pos) /**< \brief (PWM_SCUPUPD) Update Period Update */
    04025 #define PWM_SCUPUPD_UPRUPD(value) ((PWM_SCUPUPD_UPRUPD_Msk & ((value) << PWM_SCUPUPD_UPRUPD_Pos)))
    04026 /* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */
    04027 #define PWM_IER2_WRDY (0x1u << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */
    04028 #define PWM_IER2_ENDTX (0x1u << 1) /**< \brief (PWM_IER2) PDC End of TX Buffer Interrupt Enable */
    04029 #define PWM_IER2_TXBUFE (0x1u << 2) /**< \brief (PWM_IER2) PDC TX Buffer Empty Interrupt Enable */
    04030 #define PWM_IER2_UNRE (0x1u << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */
    04031 #define PWM_IER2_CMPM0 (0x1u << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */
    04032 #define PWM_IER2_CMPM1 (0x1u << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */
    04033 #define PWM_IER2_CMPM2 (0x1u << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */
    04034 #define PWM_IER2_CMPM3 (0x1u << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */
    04035 #define PWM_IER2_CMPM4 (0x1u << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */
    04036 #define PWM_IER2_CMPM5 (0x1u << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */
    04037 #define PWM_IER2_CMPM6 (0x1u << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */
    04038 #define PWM_IER2_CMPM7 (0x1u << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */
    04039 #define PWM_IER2_CMPU0 (0x1u << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */
    04040 #define PWM_IER2_CMPU1 (0x1u << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */
    04041 #define PWM_IER2_CMPU2 (0x1u << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */
    04042 #define PWM_IER2_CMPU3 (0x1u << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */
    04043 #define PWM_IER2_CMPU4 (0x1u << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */
    04044 #define PWM_IER2_CMPU5 (0x1u << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */
    04045 #define PWM_IER2_CMPU6 (0x1u << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */
    04046 #define PWM_IER2_CMPU7 (0x1u << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */
    04047 /* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */
    04048 #define PWM_IDR2_WRDY (0x1u << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */
    04049 #define PWM_IDR2_ENDTX (0x1u << 1) /**< \brief (PWM_IDR2) PDC End of TX Buffer Interrupt Disable */
    04050 #define PWM_IDR2_TXBUFE (0x1u << 2) /**< \brief (PWM_IDR2) PDC TX Buffer Empty Interrupt Disable */
    04051 #define PWM_IDR2_UNRE (0x1u << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */
    04052 #define PWM_IDR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */
    04053 #define PWM_IDR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */
    04054 #define PWM_IDR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */
    04055 #define PWM_IDR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */
    04056 #define PWM_IDR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */
    04057 #define PWM_IDR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */
    04058 #define PWM_IDR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */
    04059 #define PWM_IDR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */
    04060 #define PWM_IDR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */
    04061 #define PWM_IDR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */
    04062 #define PWM_IDR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */
    04063 #define PWM_IDR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */
    04064 #define PWM_IDR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */
    04065 #define PWM_IDR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */
    04066 #define PWM_IDR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */
    04067 #define PWM_IDR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */
    04068 /* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */
    04069 #define PWM_IMR2_WRDY (0x1u << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */
    04070 #define PWM_IMR2_ENDTX (0x1u << 1) /**< \brief (PWM_IMR2) PDC End of TX Buffer Interrupt Mask */
    04071 #define PWM_IMR2_TXBUFE (0x1u << 2) /**< \brief (PWM_IMR2) PDC TX Buffer Empty Interrupt Mask */
    04072 #define PWM_IMR2_UNRE (0x1u << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */
    04073 #define PWM_IMR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */
    04074 #define PWM_IMR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */
    04075 #define PWM_IMR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */
    04076 #define PWM_IMR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */
    04077 #define PWM_IMR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */
    04078 #define PWM_IMR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */
    04079 #define PWM_IMR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */
    04080 #define PWM_IMR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */
    04081 #define PWM_IMR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */
    04082 #define PWM_IMR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */
    04083 #define PWM_IMR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */
    04084 #define PWM_IMR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */
    04085 #define PWM_IMR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */
    04086 #define PWM_IMR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */
    04087 #define PWM_IMR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */
    04088 #define PWM_IMR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */
    04089 /* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */
    04090 #define PWM_ISR2_WRDY (0x1u << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */
    04091 #define PWM_ISR2_ENDTX (0x1u << 1) /**< \brief (PWM_ISR2) PDC End of TX Buffer */
    04092 #define PWM_ISR2_TXBUFE (0x1u << 2) /**< \brief (PWM_ISR2) PDC TX Buffer Empty */
    04093 #define PWM_ISR2_UNRE (0x1u << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */
    04094 #define PWM_ISR2_CMPM0 (0x1u << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */
    04095 #define PWM_ISR2_CMPM1 (0x1u << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */
    04096 #define PWM_ISR2_CMPM2 (0x1u << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */
    04097 #define PWM_ISR2_CMPM3 (0x1u << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */
    04098 #define PWM_ISR2_CMPM4 (0x1u << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */
    04099 #define PWM_ISR2_CMPM5 (0x1u << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */
    04100 #define PWM_ISR2_CMPM6 (0x1u << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */
    04101 #define PWM_ISR2_CMPM7 (0x1u << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */
    04102 #define PWM_ISR2_CMPU0 (0x1u << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */
    04103 #define PWM_ISR2_CMPU1 (0x1u << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */
    04104 #define PWM_ISR2_CMPU2 (0x1u << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */
    04105 #define PWM_ISR2_CMPU3 (0x1u << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */
    04106 #define PWM_ISR2_CMPU4 (0x1u << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */
    04107 #define PWM_ISR2_CMPU5 (0x1u << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */
    04108 #define PWM_ISR2_CMPU6 (0x1u << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */
    04109 #define PWM_ISR2_CMPU7 (0x1u << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */
    04110 /* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */
    04111 #define PWM_OOV_OOVH0 (0x1u << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */
    04112 #define PWM_OOV_OOVH1 (0x1u << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */
    04113 #define PWM_OOV_OOVH2 (0x1u << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */
    04114 #define PWM_OOV_OOVH3 (0x1u << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */
    04115 #define PWM_OOV_OOVL0 (0x1u << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */
    04116 #define PWM_OOV_OOVL1 (0x1u << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */
    04117 #define PWM_OOV_OOVL2 (0x1u << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */
    04118 #define PWM_OOV_OOVL3 (0x1u << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */
    04119 /* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */
    04120 #define PWM_OS_OSH0 (0x1u << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */
    04121 #define PWM_OS_OSH1 (0x1u << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */
    04122 #define PWM_OS_OSH2 (0x1u << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */
    04123 #define PWM_OS_OSH3 (0x1u << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */
    04124 #define PWM_OS_OSL0 (0x1u << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */
    04125 #define PWM_OS_OSL1 (0x1u << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */
    04126 #define PWM_OS_OSL2 (0x1u << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */
    04127 #define PWM_OS_OSL3 (0x1u << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */
    04128 /* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */
    04129 #define PWM_OSS_OSSH0 (0x1u << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */
    04130 #define PWM_OSS_OSSH1 (0x1u << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */
    04131 #define PWM_OSS_OSSH2 (0x1u << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */
    04132 #define PWM_OSS_OSSH3 (0x1u << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */
    04133 #define PWM_OSS_OSSL0 (0x1u << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */
    04134 #define PWM_OSS_OSSL1 (0x1u << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */
    04135 #define PWM_OSS_OSSL2 (0x1u << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */
    04136 #define PWM_OSS_OSSL3 (0x1u << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */
    04137 /* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */
    04138 #define PWM_OSC_OSCH0 (0x1u << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */
    04139 #define PWM_OSC_OSCH1 (0x1u << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */
    04140 #define PWM_OSC_OSCH2 (0x1u << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */
    04141 #define PWM_OSC_OSCH3 (0x1u << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */
    04142 #define PWM_OSC_OSCL0 (0x1u << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */
    04143 #define PWM_OSC_OSCL1 (0x1u << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */
    04144 #define PWM_OSC_OSCL2 (0x1u << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */
    04145 #define PWM_OSC_OSCL3 (0x1u << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */
    04146 /* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */
    04147 #define PWM_OSSUPD_OSSUPH0 (0x1u << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */
    04148 #define PWM_OSSUPD_OSSUPH1 (0x1u << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */
    04149 #define PWM_OSSUPD_OSSUPH2 (0x1u << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */
    04150 #define PWM_OSSUPD_OSSUPH3 (0x1u << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */
    04151 #define PWM_OSSUPD_OSSUPL0 (0x1u << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */
    04152 #define PWM_OSSUPD_OSSUPL1 (0x1u << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */
    04153 #define PWM_OSSUPD_OSSUPL2 (0x1u << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */
    04154 #define PWM_OSSUPD_OSSUPL3 (0x1u << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */
    04155 /* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */
    04156 #define PWM_OSCUPD_OSCUPH0 (0x1u << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */
    04157 #define PWM_OSCUPD_OSCUPH1 (0x1u << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */
    04158 #define PWM_OSCUPD_OSCUPH2 (0x1u << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */
    04159 #define PWM_OSCUPD_OSCUPH3 (0x1u << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */
    04160 #define PWM_OSCUPD_OSCUPL0 (0x1u << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */
    04161 #define PWM_OSCUPD_OSCUPL1 (0x1u << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */
    04162 #define PWM_OSCUPD_OSCUPL2 (0x1u << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */
    04163 #define PWM_OSCUPD_OSCUPL3 (0x1u << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */
    04164 /* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */
    04165 #define PWM_FMR_FPOL_Pos 0
    04166 #define PWM_FMR_FPOL_Msk (0xffu << PWM_FMR_FPOL_Pos) /**< \brief (PWM_FMR) Fault Polarity (fault input bit varies from 0 to 5) */
    04167 #define PWM_FMR_FPOL(value) ((PWM_FMR_FPOL_Msk & ((value) << PWM_FMR_FPOL_Pos)))
    04168 #define PWM_FMR_FMOD_Pos 8
    04169 #define PWM_FMR_FMOD_Msk (0xffu << PWM_FMR_FMOD_Pos) /**< \brief (PWM_FMR) Fault Activation Mode (fault input bit varies from 0 to 5) */
    04170 #define PWM_FMR_FMOD(value) ((PWM_FMR_FMOD_Msk & ((value) << PWM_FMR_FMOD_Pos)))
    04171 #define PWM_FMR_FFIL_Pos 16
    04172 #define PWM_FMR_FFIL_Msk (0xffu << PWM_FMR_FFIL_Pos) /**< \brief (PWM_FMR) Fault Filtering (fault input bit varies from 0 to 5) */
    04173 #define PWM_FMR_FFIL(value) ((PWM_FMR_FFIL_Msk & ((value) << PWM_FMR_FFIL_Pos)))
    04174 /* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */
    04175 #define PWM_FSR_FIV_Pos 0
    04176 #define PWM_FSR_FIV_Msk (0xffu << PWM_FSR_FIV_Pos) /**< \brief (PWM_FSR) Fault Input Value (fault input bit varies from 0 to 5) */
    04177 #define PWM_FSR_FS_Pos 8
    04178 #define PWM_FSR_FS_Msk (0xffu << PWM_FSR_FS_Pos) /**< \brief (PWM_FSR) Fault Status (fault input bit varies from 0 to 5) */
    04179 /* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */
    04180 #define PWM_FCR_FCLR_Pos 0
    04181 #define PWM_FCR_FCLR_Msk (0xffu << PWM_FCR_FCLR_Pos) /**< \brief (PWM_FCR) Fault Clear (fault input bit varies from 0 to 5) */
    04182 #define PWM_FCR_FCLR(value) ((PWM_FCR_FCLR_Msk & ((value) << PWM_FCR_FCLR_Pos)))
    04183 /* -------- PWM_FPV : (PWM Offset: 0x68) PWM Fault Protection Value Register -------- */
    04184 #define PWM_FPV_FPVH0 (0x1u << 0) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 0 */
    04185 #define PWM_FPV_FPVH1 (0x1u << 1) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 1 */
    04186 #define PWM_FPV_FPVH2 (0x1u << 2) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 2 */
    04187 #define PWM_FPV_FPVH3 (0x1u << 3) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 3 */
    04188 #define PWM_FPV_FPVL0 (0x1u << 16) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 0 */
    04189 #define PWM_FPV_FPVL1 (0x1u << 17) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 1 */
    04190 #define PWM_FPV_FPVL2 (0x1u << 18) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 2 */
    04191 #define PWM_FPV_FPVL3 (0x1u << 19) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 3 */
    04192 /* -------- PWM_FPE : (PWM Offset: 0x6C) PWM Fault Protection Enable Register -------- */
    04193 #define PWM_FPE_FPE0_Pos 0
    04194 #define PWM_FPE_FPE0_Msk (0xffu << PWM_FPE_FPE0_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 0 (fault input bit varies from 0 to 5) */
    04195 #define PWM_FPE_FPE0(value) ((PWM_FPE_FPE0_Msk & ((value) << PWM_FPE_FPE0_Pos)))
    04196 #define PWM_FPE_FPE1_Pos 8
    04197 #define PWM_FPE_FPE1_Msk (0xffu << PWM_FPE_FPE1_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 1 (fault input bit varies from 0 to 5) */
    04198 #define PWM_FPE_FPE1(value) ((PWM_FPE_FPE1_Msk & ((value) << PWM_FPE_FPE1_Pos)))
    04199 #define PWM_FPE_FPE2_Pos 16
    04200 #define PWM_FPE_FPE2_Msk (0xffu << PWM_FPE_FPE2_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 2 (fault input bit varies from 0 to 5) */
    04201 #define PWM_FPE_FPE2(value) ((PWM_FPE_FPE2_Msk & ((value) << PWM_FPE_FPE2_Pos)))
    04202 #define PWM_FPE_FPE3_Pos 24
    04203 #define PWM_FPE_FPE3_Msk (0xffu << PWM_FPE_FPE3_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 3 (fault input bit varies from 0 to 5) */
    04204 #define PWM_FPE_FPE3(value) ((PWM_FPE_FPE3_Msk & ((value) << PWM_FPE_FPE3_Pos)))
    04205 /* -------- PWM_ELMR[2] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */
    04206 #define PWM_ELMR_CSEL0 (0x1u << 0) /**< \brief (PWM_ELMR[2]) Comparison 0 Selection */
    04207 #define PWM_ELMR_CSEL1 (0x1u << 1) /**< \brief (PWM_ELMR[2]) Comparison 1 Selection */
    04208 #define PWM_ELMR_CSEL2 (0x1u << 2) /**< \brief (PWM_ELMR[2]) Comparison 2 Selection */
    04209 #define PWM_ELMR_CSEL3 (0x1u << 3) /**< \brief (PWM_ELMR[2]) Comparison 3 Selection */
    04210 #define PWM_ELMR_CSEL4 (0x1u << 4) /**< \brief (PWM_ELMR[2]) Comparison 4 Selection */
    04211 #define PWM_ELMR_CSEL5 (0x1u << 5) /**< \brief (PWM_ELMR[2]) Comparison 5 Selection */
    04212 #define PWM_ELMR_CSEL6 (0x1u << 6) /**< \brief (PWM_ELMR[2]) Comparison 6 Selection */
    04213 #define PWM_ELMR_CSEL7 (0x1u << 7) /**< \brief (PWM_ELMR[2]) Comparison 7 Selection */
    04214 /* -------- PWM_SMMR : (PWM Offset: 0xB0) PWM Stepper Motor Mode Register -------- */
    04215 #define PWM_SMMR_GCEN0 (0x1u << 0) /**< \brief (PWM_SMMR) Gray Count ENable */
    04216 #define PWM_SMMR_GCEN1 (0x1u << 1) /**< \brief (PWM_SMMR) Gray Count ENable */
    04217 #define PWM_SMMR_DOWN0 (0x1u << 16) /**< \brief (PWM_SMMR) DOWN Count */
    04218 #define PWM_SMMR_DOWN1 (0x1u << 17) /**< \brief (PWM_SMMR) DOWN Count */
    04219 /* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protect Control Register -------- */
    04220 #define PWM_WPCR_WPCMD_Pos 0
    04221 #define PWM_WPCR_WPCMD_Msk (0x3u << PWM_WPCR_WPCMD_Pos) /**< \brief (PWM_WPCR) Write Protect Command */
    04222 #define PWM_WPCR_WPCMD(value) ((PWM_WPCR_WPCMD_Msk & ((value) << PWM_WPCR_WPCMD_Pos)))
    04223 #define PWM_WPCR_WPRG0 (0x1u << 2) /**< \brief (PWM_WPCR) Write Protect Register Group 0 */
    04224 #define PWM_WPCR_WPRG1 (0x1u << 3) /**< \brief (PWM_WPCR) Write Protect Register Group 1 */
    04225 #define PWM_WPCR_WPRG2 (0x1u << 4) /**< \brief (PWM_WPCR) Write Protect Register Group 2 */
    04226 #define PWM_WPCR_WPRG3 (0x1u << 5) /**< \brief (PWM_WPCR) Write Protect Register Group 3 */
    04227 #define PWM_WPCR_WPRG4 (0x1u << 6) /**< \brief (PWM_WPCR) Write Protect Register Group 4 */
    04228 #define PWM_WPCR_WPRG5 (0x1u << 7) /**< \brief (PWM_WPCR) Write Protect Register Group 5 */
    04229 #define PWM_WPCR_WPKEY_Pos 8
    04230 #define PWM_WPCR_WPKEY_Msk (0xffffffu << PWM_WPCR_WPKEY_Pos) /**< \brief (PWM_WPCR) Write Protect Key */
    04231 #define PWM_WPCR_WPKEY(value) ((PWM_WPCR_WPKEY_Msk & ((value) << PWM_WPCR_WPKEY_Pos)))
    04232 /* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protect Status Register -------- */
    04233 #define PWM_WPSR_WPSWS0 (0x1u << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */
    04234 #define PWM_WPSR_WPSWS1 (0x1u << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */
    04235 #define PWM_WPSR_WPSWS2 (0x1u << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */
    04236 #define PWM_WPSR_WPSWS3 (0x1u << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */
    04237 #define PWM_WPSR_WPSWS4 (0x1u << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */
    04238 #define PWM_WPSR_WPSWS5 (0x1u << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */
    04239 #define PWM_WPSR_WPVS (0x1u << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */
    04240 #define PWM_WPSR_WPHWS0 (0x1u << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */
    04241 #define PWM_WPSR_WPHWS1 (0x1u << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */
    04242 #define PWM_WPSR_WPHWS2 (0x1u << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */
    04243 #define PWM_WPSR_WPHWS3 (0x1u << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */
    04244 #define PWM_WPSR_WPHWS4 (0x1u << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */
    04245 #define PWM_WPSR_WPHWS5 (0x1u << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */
    04246 #define PWM_WPSR_WPVSRC_Pos 16
    04247 #define PWM_WPSR_WPVSRC_Msk (0xffffu << PWM_WPSR_WPVSRC_Pos) /**< \brief (PWM_WPSR) Write Protect Violation Source */
    04248 /* -------- PWM_RPR : (PWM Offset: 0x100) Receive Pointer Register -------- */
    04249 #define PWM_RPR_RXPTR_Pos 0
    04250 #define PWM_RPR_RXPTR_Msk (0xffffffffu << PWM_RPR_RXPTR_Pos) /**< \brief (PWM_RPR) Receive Pointer Register */
    04251 #define PWM_RPR_RXPTR(value) ((PWM_RPR_RXPTR_Msk & ((value) << PWM_RPR_RXPTR_Pos)))
    04252 /* -------- PWM_RCR : (PWM Offset: 0x104) Receive Counter Register -------- */
    04253 #define PWM_RCR_RXCTR_Pos 0
    04254 #define PWM_RCR_RXCTR_Msk (0xffffu << PWM_RCR_RXCTR_Pos) /**< \brief (PWM_RCR) Receive Counter Register */
    04255 #define PWM_RCR_RXCTR(value) ((PWM_RCR_RXCTR_Msk & ((value) << PWM_RCR_RXCTR_Pos)))
    04256 /* -------- PWM_TPR : (PWM Offset: 0x108) Transmit Pointer Register -------- */
    04257 #define PWM_TPR_TXPTR_Pos 0
    04258 #define PWM_TPR_TXPTR_Msk (0xffffffffu << PWM_TPR_TXPTR_Pos) /**< \brief (PWM_TPR) Transmit Counter Register */
    04259 #define PWM_TPR_TXPTR(value) ((PWM_TPR_TXPTR_Msk & ((value) << PWM_TPR_TXPTR_Pos)))
    04260 /* -------- PWM_TCR : (PWM Offset: 0x10C) Transmit Counter Register -------- */
    04261 #define PWM_TCR_TXCTR_Pos 0
    04262 #define PWM_TCR_TXCTR_Msk (0xffffu << PWM_TCR_TXCTR_Pos) /**< \brief (PWM_TCR) Transmit Counter Register */
    04263 #define PWM_TCR_TXCTR(value) ((PWM_TCR_TXCTR_Msk & ((value) << PWM_TCR_TXCTR_Pos)))
    04264 /* -------- PWM_RNPR : (PWM Offset: 0x110) Receive Next Pointer Register -------- */
    04265 #define PWM_RNPR_RXNPTR_Pos 0
    04266 #define PWM_RNPR_RXNPTR_Msk (0xffffffffu << PWM_RNPR_RXNPTR_Pos) /**< \brief (PWM_RNPR) Receive Next Pointer */
    04267 #define PWM_RNPR_RXNPTR(value) ((PWM_RNPR_RXNPTR_Msk & ((value) << PWM_RNPR_RXNPTR_Pos)))
    04268 /* -------- PWM_RNCR : (PWM Offset: 0x114) Receive Next Counter Register -------- */
    04269 #define PWM_RNCR_RXNCTR_Pos 0
    04270 #define PWM_RNCR_RXNCTR_Msk (0xffffu << PWM_RNCR_RXNCTR_Pos) /**< \brief (PWM_RNCR) Receive Next Counter */
    04271 #define PWM_RNCR_RXNCTR(value) ((PWM_RNCR_RXNCTR_Msk & ((value) << PWM_RNCR_RXNCTR_Pos)))
    04272 /* -------- PWM_TNPR : (PWM Offset: 0x118) Transmit Next Pointer Register -------- */
    04273 #define PWM_TNPR_TXNPTR_Pos 0
    04274 #define PWM_TNPR_TXNPTR_Msk (0xffffffffu << PWM_TNPR_TXNPTR_Pos) /**< \brief (PWM_TNPR) Transmit Next Pointer */
    04275 #define PWM_TNPR_TXNPTR(value) ((PWM_TNPR_TXNPTR_Msk & ((value) << PWM_TNPR_TXNPTR_Pos)))
    04276 /* -------- PWM_TNCR : (PWM Offset: 0x11C) Transmit Next Counter Register -------- */
    04277 #define PWM_TNCR_TXNCTR_Pos 0
    04278 #define PWM_TNCR_TXNCTR_Msk (0xffffu << PWM_TNCR_TXNCTR_Pos) /**< \brief (PWM_TNCR) Transmit Counter Next */
    04279 #define PWM_TNCR_TXNCTR(value) ((PWM_TNCR_TXNCTR_Msk & ((value) << PWM_TNCR_TXNCTR_Pos)))
    04280 /* -------- PWM_PTCR : (PWM Offset: 0x120) Transfer Control Register -------- */
    04281 #define PWM_PTCR_RXTEN (0x1u << 0) /**< \brief (PWM_PTCR) Receiver Transfer Enable */
    04282 #define PWM_PTCR_RXTDIS (0x1u << 1) /**< \brief (PWM_PTCR) Receiver Transfer Disable */
    04283 #define PWM_PTCR_TXTEN (0x1u << 8) /**< \brief (PWM_PTCR) Transmitter Transfer Enable */
    04284 #define PWM_PTCR_TXTDIS (0x1u << 9) /**< \brief (PWM_PTCR) Transmitter Transfer Disable */
    04285 /* -------- PWM_PTSR : (PWM Offset: 0x124) Transfer Status Register -------- */
    04286 #define PWM_PTSR_RXTEN (0x1u << 0) /**< \brief (PWM_PTSR) Receiver Transfer Enable */
    04287 #define PWM_PTSR_TXTEN (0x1u << 8) /**< \brief (PWM_PTSR) Transmitter Transfer Enable */
    04288 /* -------- PWM_CMPV : (PWM Offset: N/A) PWM Comparison 0 Value Register -------- */
    04289 #define PWM_CMPV_CV_Pos 0
    04290 #define PWM_CMPV_CV_Msk (0xffffffu << PWM_CMPV_CV_Pos) /**< \brief (PWM_CMPV) Comparison x Value */
    04291 #define PWM_CMPV_CV(value) ((PWM_CMPV_CV_Msk & ((value) << PWM_CMPV_CV_Pos)))
    04292 #define PWM_CMPV_CVM (0x1u << 24) /**< \brief (PWM_CMPV) Comparison x Value Mode */
    04293 /* -------- PWM_CMPVUPD : (PWM Offset: N/A) PWM Comparison 0 Value Update Register -------- */
    04294 #define PWM_CMPVUPD_CVUPD_Pos 0
    04295 #define PWM_CMPVUPD_CVUPD_Msk (0xffffffu << PWM_CMPVUPD_CVUPD_Pos) /**< \brief (PWM_CMPVUPD) Comparison x Value Update */
    04296 #define PWM_CMPVUPD_CVUPD(value) ((PWM_CMPVUPD_CVUPD_Msk & ((value) << PWM_CMPVUPD_CVUPD_Pos)))
    04297 #define PWM_CMPVUPD_CVMUPD (0x1u << 24) /**< \brief (PWM_CMPVUPD) Comparison x Value Mode Update */
    04298 /* -------- PWM_CMPM : (PWM Offset: N/A) PWM Comparison 0 Mode Register -------- */
    04299 #define PWM_CMPM_CEN (0x1u << 0) /**< \brief (PWM_CMPM) Comparison x Enable */
    04300 #define PWM_CMPM_CTR_Pos 4
    04301 #define PWM_CMPM_CTR_Msk (0xfu << PWM_CMPM_CTR_Pos) /**< \brief (PWM_CMPM) Comparison x Trigger */
    04302 #define PWM_CMPM_CTR(value) ((PWM_CMPM_CTR_Msk & ((value) << PWM_CMPM_CTR_Pos)))
    04303 #define PWM_CMPM_CPR_Pos 8
    04304 #define PWM_CMPM_CPR_Msk (0xfu << PWM_CMPM_CPR_Pos) /**< \brief (PWM_CMPM) Comparison x Period */
    04305 #define PWM_CMPM_CPR(value) ((PWM_CMPM_CPR_Msk & ((value) << PWM_CMPM_CPR_Pos)))
    04306 #define PWM_CMPM_CPRCNT_Pos 12
    04307 #define PWM_CMPM_CPRCNT_Msk (0xfu << PWM_CMPM_CPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Period Counter */
    04308 #define PWM_CMPM_CPRCNT(value) ((PWM_CMPM_CPRCNT_Msk & ((value) << PWM_CMPM_CPRCNT_Pos)))
    04309 #define PWM_CMPM_CUPR_Pos 16
    04310 #define PWM_CMPM_CUPR_Msk (0xfu << PWM_CMPM_CUPR_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period */
    04311 #define PWM_CMPM_CUPR(value) ((PWM_CMPM_CUPR_Msk & ((value) << PWM_CMPM_CUPR_Pos)))
    04312 #define PWM_CMPM_CUPRCNT_Pos 20
    04313 #define PWM_CMPM_CUPRCNT_Msk (0xfu << PWM_CMPM_CUPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period Counter */
    04314 #define PWM_CMPM_CUPRCNT(value) ((PWM_CMPM_CUPRCNT_Msk & ((value) << PWM_CMPM_CUPRCNT_Pos)))
    04315 /* -------- PWM_CMPMUPD : (PWM Offset: N/A) PWM Comparison 0 Mode Update Register -------- */
    04316 #define PWM_CMPMUPD_CENUPD (0x1u << 0) /**< \brief (PWM_CMPMUPD) Comparison x Enable Update */
    04317 #define PWM_CMPMUPD_CTRUPD_Pos 4
    04318 #define PWM_CMPMUPD_CTRUPD_Msk (0xfu << PWM_CMPMUPD_CTRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Trigger Update */
    04319 #define PWM_CMPMUPD_CTRUPD(value) ((PWM_CMPMUPD_CTRUPD_Msk & ((value) << PWM_CMPMUPD_CTRUPD_Pos)))
    04320 #define PWM_CMPMUPD_CPRUPD_Pos 8
    04321 #define PWM_CMPMUPD_CPRUPD_Msk (0xfu << PWM_CMPMUPD_CPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Period Update */
    04322 #define PWM_CMPMUPD_CPRUPD(value) ((PWM_CMPMUPD_CPRUPD_Msk & ((value) << PWM_CMPMUPD_CPRUPD_Pos)))
    04323 #define PWM_CMPMUPD_CUPRUPD_Pos 16
    04324 #define PWM_CMPMUPD_CUPRUPD_Msk (0xfu << PWM_CMPMUPD_CUPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Update Period Update */
    04325 #define PWM_CMPMUPD_CUPRUPD(value) ((PWM_CMPMUPD_CUPRUPD_Msk & ((value) << PWM_CMPMUPD_CUPRUPD_Pos)))
    04326 /* -------- PWM_CMR : (PWM Offset: N/A) PWM Channel Mode Register -------- */
    04327 #define PWM_CMR_CPRE_Pos 0
    04328 #define PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos) /**< \brief (PWM_CMR) Channel Pre-scaler */
    04329 #define   PWM_CMR_CPRE_MCK (0x0u << 0) /**< \brief (PWM_CMR) Master clock */
    04330 #define   PWM_CMR_CPRE_MCK_DIV_2 (0x1u << 0) /**< \brief (PWM_CMR) Master clock/2 */
    04331 #define   PWM_CMR_CPRE_MCK_DIV_4 (0x2u << 0) /**< \brief (PWM_CMR) Master clock/4 */
    04332 #define   PWM_CMR_CPRE_MCK_DIV_8 (0x3u << 0) /**< \brief (PWM_CMR) Master clock/8 */
    04333 #define   PWM_CMR_CPRE_MCK_DIV_16 (0x4u << 0) /**< \brief (PWM_CMR) Master clock/16 */
    04334 #define   PWM_CMR_CPRE_MCK_DIV_32 (0x5u << 0) /**< \brief (PWM_CMR) Master clock/32 */
    04335 #define   PWM_CMR_CPRE_MCK_DIV_64 (0x6u << 0) /**< \brief (PWM_CMR) Master clock/64 */
    04336 #define   PWM_CMR_CPRE_MCK_DIV_128 (0x7u << 0) /**< \brief (PWM_CMR) Master clock/128 */
    04337 #define   PWM_CMR_CPRE_MCK_DIV_256 (0x8u << 0) /**< \brief (PWM_CMR) Master clock/256 */
    04338 #define   PWM_CMR_CPRE_MCK_DIV_512 (0x9u << 0) /**< \brief (PWM_CMR) Master clock/512 */
    04339 #define   PWM_CMR_CPRE_MCK_DIV_1024 (0xAu << 0) /**< \brief (PWM_CMR) Master clock/1024 */
    04340 #define   PWM_CMR_CPRE_CLKA (0xBu << 0) /**< \brief (PWM_CMR) Clock A */
    04341 #define   PWM_CMR_CPRE_CLKB (0xCu << 0) /**< \brief (PWM_CMR) Clock B */
    04342 #define PWM_CMR_CALG (0x1u << 8) /**< \brief (PWM_CMR) Channel Alignment */
    04343 #define PWM_CMR_CPOL (0x1u << 9) /**< \brief (PWM_CMR) Channel Polarity */
    04344 #define PWM_CMR_CES (0x1u << 10) /**< \brief (PWM_CMR) Counter Event Selection */
    04345 #define PWM_CMR_DTE (0x1u << 16) /**< \brief (PWM_CMR) Dead-Time Generator Enable */
    04346 #define PWM_CMR_DTHI (0x1u << 17) /**< \brief (PWM_CMR) Dead-Time PWMHx Output Inverted */
    04347 #define PWM_CMR_DTLI (0x1u << 18) /**< \brief (PWM_CMR) Dead-Time PWMLx Output Inverted */
    04348 /* -------- PWM_CDTY : (PWM Offset: N/A) PWM Channel Duty Cycle Register -------- */
    04349 #define PWM_CDTY_CDTY_Pos 0
    04350 #define PWM_CDTY_CDTY_Msk (0xffffffu << PWM_CDTY_CDTY_Pos) /**< \brief (PWM_CDTY) Channel Duty-Cycle */
    04351 #define PWM_CDTY_CDTY(value) ((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos)))
    04352 /* -------- PWM_CDTYUPD : (PWM Offset: N/A) PWM Channel Duty Cycle Update Register -------- */
    04353 #define PWM_CDTYUPD_CDTYUPD_Pos 0
    04354 #define PWM_CDTYUPD_CDTYUPD_Msk (0xffffffu << PWM_CDTYUPD_CDTYUPD_Pos) /**< \brief (PWM_CDTYUPD) Channel Duty-Cycle Update */
    04355 #define PWM_CDTYUPD_CDTYUPD(value) ((PWM_CDTYUPD_CDTYUPD_Msk & ((value) << PWM_CDTYUPD_CDTYUPD_Pos)))
    04356 /* -------- PWM_CPRD : (PWM Offset: N/A) PWM Channel Period Register -------- */
    04357 #define PWM_CPRD_CPRD_Pos 0
    04358 #define PWM_CPRD_CPRD_Msk (0xffffffu << PWM_CPRD_CPRD_Pos) /**< \brief (PWM_CPRD) Channel Period */
    04359 #define PWM_CPRD_CPRD(value) ((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos)))
    04360 /* -------- PWM_CPRDUPD : (PWM Offset: N/A) PWM Channel Period Update Register -------- */
    04361 #define PWM_CPRDUPD_CPRDUPD_Pos 0
    04362 #define PWM_CPRDUPD_CPRDUPD_Msk (0xffffffu << PWM_CPRDUPD_CPRDUPD_Pos) /**< \brief (PWM_CPRDUPD) Channel Period Update */
    04363 #define PWM_CPRDUPD_CPRDUPD(value) ((PWM_CPRDUPD_CPRDUPD_Msk & ((value) << PWM_CPRDUPD_CPRDUPD_Pos)))
    04364 /* -------- PWM_CCNT : (PWM Offset: N/A) PWM Channel Counter Register -------- */
    04365 #define PWM_CCNT_CNT_Pos 0
    04366 #define PWM_CCNT_CNT_Msk (0xffffffu << PWM_CCNT_CNT_Pos) /**< \brief (PWM_CCNT) Channel Counter Register */
    04367 /* -------- PWM_DT : (PWM Offset: N/A) PWM Channel Dead Time Register -------- */
    04368 #define PWM_DT_DTH_Pos 0
    04369 #define PWM_DT_DTH_Msk (0xffffu << PWM_DT_DTH_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMHx Output */
    04370 #define PWM_DT_DTH(value) ((PWM_DT_DTH_Msk & ((value) << PWM_DT_DTH_Pos)))
    04371 #define PWM_DT_DTL_Pos 16
    04372 #define PWM_DT_DTL_Msk (0xffffu << PWM_DT_DTL_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMLx Output */
    04373 #define PWM_DT_DTL(value) ((PWM_DT_DTL_Msk & ((value) << PWM_DT_DTL_Pos)))
    04374 /* -------- PWM_DTUPD : (PWM Offset: N/A) PWM Channel Dead Time Update Register -------- */
    04375 #define PWM_DTUPD_DTHUPD_Pos 0
    04376 #define PWM_DTUPD_DTHUPD_Msk (0xffffu << PWM_DTUPD_DTHUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMHx Output */
    04377 #define PWM_DTUPD_DTHUPD(value) ((PWM_DTUPD_DTHUPD_Msk & ((value) << PWM_DTUPD_DTHUPD_Pos)))
    04378 #define PWM_DTUPD_DTLUPD_Pos 16
    04379 #define PWM_DTUPD_DTLUPD_Msk (0xffffu << PWM_DTUPD_DTLUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMLx Output */
    04380 #define PWM_DTUPD_DTLUPD(value) ((PWM_DTUPD_DTLUPD_Msk & ((value) << PWM_DTUPD_DTLUPD_Pos)))
    04381
    04382 /*@}*/
    04383
    04384 /* ============================================================================= */
    04385 /**  SOFTWARE API DEFINITION FOR Reset Controller */
    04386 /* ============================================================================= */
    04387 /** \addtogroup SAM3S8_RSTC Reset Controller */
    04388 /*@{*/
    04389
    04390 #ifndef __ASSEMBLY__
    04391 /** \brief Rstc hardware registers */
    04392 typedef struct {
    04393   WoReg RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */
    04394   RoReg RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */
    04395   RwReg RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */
    04396 } Rstc;
    04397 #endif /* __ASSEMBLY__ */
    04398 /* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */
    04399 #define RSTC_CR_PROCRST (0x1u << 0) /**< \brief (RSTC_CR) Processor Reset */
    04400 #define RSTC_CR_PERRST (0x1u << 2) /**< \brief (RSTC_CR) Peripheral Reset */
    04401 #define RSTC_CR_EXTRST (0x1u << 3) /**< \brief (RSTC_CR) External Reset */
    04402 #define RSTC_CR_KEY_Pos 24
    04403 #define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos) /**< \brief (RSTC_CR) Password */
    04404 #define RSTC_CR_KEY(value) ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos)))
    04405 /* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */
    04406 #define RSTC_SR_URSTS (0x1u << 0) /**< \brief (RSTC_SR) User Reset Status */
    04407 #define RSTC_SR_RSTTYP_Pos 8
    04408 #define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos) /**< \brief (RSTC_SR) Reset Type */
    04409 #define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */
    04410 #define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */
    04411 /* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */
    04412 #define RSTC_MR_URSTEN (0x1u << 0) /**< \brief (RSTC_MR) User Reset Enable */
    04413 #define RSTC_MR_URSTIEN (0x1u << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */
    04414 #define RSTC_MR_ERSTL_Pos 8
    04415 #define RSTC_MR_ERSTL_Msk (0xfu << RSTC_MR_ERSTL_Pos) /**< \brief (RSTC_MR) External Reset Length */
    04416 #define RSTC_MR_ERSTL(value) ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos)))
    04417 #define RSTC_MR_KEY_Pos 24
    04418 #define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos) /**< \brief (RSTC_MR) Password */
    04419 #define RSTC_MR_KEY(value) ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos)))
    04420
    04421 /*@}*/
    04422
    04423 /* ============================================================================= */
    04424 /**  SOFTWARE API DEFINITION FOR Real-time Clock */
    04425 /* ============================================================================= */
    04426 /** \addtogroup SAM3S8_RTC Real-time Clock */
    04427 /*@{*/
    04428
    04429 #ifndef __ASSEMBLY__
    04430 /** \brief Rtc hardware registers */
    04431 typedef struct {
    04432   RwReg RTC_CR;     /**< \brief (Rtc Offset: 0x00) Control Register */
    04433   RwReg RTC_MR;     /**< \brief (Rtc Offset: 0x04) Mode Register */
    04434   RwReg RTC_TIMR;   /**< \brief (Rtc Offset: 0x08) Time Register */
    04435   RwReg RTC_CALR;   /**< \brief (Rtc Offset: 0x0C) Calendar Register */
    04436   RwReg RTC_TIMALR; /**< \brief (Rtc Offset: 0x10) Time Alarm Register */
    04437   RwReg RTC_CALALR; /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */
    04438   RoReg RTC_SR;     /**< \brief (Rtc Offset: 0x18) Status Register */
    04439   WoReg RTC_SCCR;   /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */
    04440   WoReg RTC_IER;    /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */
    04441   WoReg RTC_IDR;    /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */
    04442   RoReg RTC_IMR;    /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */
    04443   RoReg RTC_VER;    /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */
    04444 } Rtc;
    04445 #endif /* __ASSEMBLY__ */
    04446 /* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */
    04447 #define RTC_CR_UPDTIM (0x1u << 0) /**< \brief (RTC_CR) Update Request Time Register */
    04448 #define RTC_CR_UPDCAL (0x1u << 1) /**< \brief (RTC_CR) Update Request Calendar Register */
    04449 #define RTC_CR_TIMEVSEL_Pos 8
    04450 #define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos) /**< \brief (RTC_CR) Time Event Selection */
    04451 #define   RTC_CR_TIMEVSEL_MINUTE (0x0u << 8) /**< \brief (RTC_CR) Minute change */
    04452 #define   RTC_CR_TIMEVSEL_HOUR (0x1u << 8) /**< \brief (RTC_CR) Hour change */
    04453 #define   RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8) /**< \brief (RTC_CR) Every day at midnight */
    04454 #define   RTC_CR_TIMEVSEL_NOON (0x3u << 8) /**< \brief (RTC_CR) Every day at noon */
    04455 #define RTC_CR_CALEVSEL_Pos 16
    04456 #define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos) /**< \brief (RTC_CR) Calendar Event Selection */
    04457 #define   RTC_CR_CALEVSEL_WEEK (0x0u << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00) */
    04458 #define   RTC_CR_CALEVSEL_MONTH (0x1u << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00) */
    04459 #define   RTC_CR_CALEVSEL_YEAR (0x2u << 16) /**< \brief (RTC_CR) Year change (every January 1 at time 00:00:00) */
    04460 /* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */
    04461 #define RTC_MR_HRMOD (0x1u << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */
    04462 #define RTC_MR_PERSIAN (0x1u << 1) /**< \brief (RTC_MR) PERSIAN Calendar */
    04463 #define RTC_MR_NEGPPM (0x1u << 4) /**< \brief (RTC_MR) NEGative PPM Correction */
    04464 #define RTC_MR_CORRECTION_Pos 8
    04465 #define RTC_MR_CORRECTION_Msk (0x7fu << RTC_MR_CORRECTION_Pos) /**< \brief (RTC_MR)  */
    04466 #define RTC_MR_CORRECTION(value) ((RTC_MR_CORRECTION_Msk & ((value) << RTC_MR_CORRECTION_Pos)))
    04467 #define RTC_MR_HIGHPPM (0x1u << 15) /**< \brief (RTC_MR) HIGH PPM Correction */
    04468 #define RTC_MR_OUT0_Pos 16
    04469 #define RTC_MR_OUT0_Msk (0x7u << RTC_MR_OUT0_Pos) /**< \brief (RTC_MR) RTCOUT0 Output Source Selection */
    04470 #define   RTC_MR_OUT0_NO_WAVE (0x0u << 16) /**< \brief (RTC_MR) no waveform, stuck at '0' */
    04471 #define   RTC_MR_OUT0_FREQ1HZ (0x1u << 16) /**< \brief (RTC_MR) 1 Hz square wave */
    04472 #define   RTC_MR_OUT0_FREQ32HZ (0x2u << 16) /**< \brief (RTC_MR) 32 Hz square wave */
    04473 #define   RTC_MR_OUT0_FREQ64HZ (0x3u << 16) /**< \brief (RTC_MR) 64 Hz square wave */
    04474 #define   RTC_MR_OUT0_FREQ512HZ (0x4u << 16) /**< \brief (RTC_MR) 512 Hz square wave */
    04475 #define   RTC_MR_OUT0_ALARM_TOGGLE (0x5u << 16) /**< \brief (RTC_MR) output toggles when alarm flag rises */
    04476 #define   RTC_MR_OUT0_ALARM_FLAG (0x6u << 16) /**< \brief (RTC_MR) output is a copy of the alarm flag */
    04477 #define   RTC_MR_OUT0_PROG_PULSE (0x7u << 16) /**< \brief (RTC_MR) duty cycle programmable pulse */
    04478 #define RTC_MR_OUT1_Pos 20
    04479 #define RTC_MR_OUT1_Msk (0x7u << RTC_MR_OUT1_Pos) /**< \brief (RTC_MR) RTCOUT1 Output Source Selection */
    04480 #define   RTC_MR_OUT1_NO_WAVE (0x0u << 20) /**< \brief (RTC_MR) no waveform, stuck at '0' */
    04481 #define   RTC_MR_OUT1_FREQ1HZ (0x1u << 20) /**< \brief (RTC_MR) 1 Hz square wave */
    04482 #define   RTC_MR_OUT1_FREQ32HZ (0x2u << 20) /**< \brief (RTC_MR) 32 Hz square wave */
    04483 #define   RTC_MR_OUT1_FREQ64HZ (0x3u << 20) /**< \brief (RTC_MR) 64 Hz square wave */
    04484 #define   RTC_MR_OUT1_FREQ512HZ (0x4u << 20) /**< \brief (RTC_MR) 512 Hz square wave */
    04485 #define   RTC_MR_OUT1_ALARM_TOGGLE (0x5u << 20) /**< \brief (RTC_MR) output toggles when alarm flag rises */
    04486 #define   RTC_MR_OUT1_ALARM_FLAG (0x6u << 20) /**< \brief (RTC_MR) output is a copy of the alarm flag */
    04487 #define   RTC_MR_OUT1_PROG_PULSE (0x7u << 20) /**< \brief (RTC_MR) duty cycle programmable pulse */
    04488 #define RTC_MR_THIGH_Pos 24
    04489 #define RTC_MR_THIGH_Msk (0x7u << RTC_MR_THIGH_Pos) /**< \brief (RTC_MR) High Duration of the Output Pulse */
    04490 #define   RTC_MR_THIGH_H_31MS (0x0u << 24) /**< \brief (RTC_MR) 31.2 ms */
    04491 #define   RTC_MR_THIGH_H_16MS (0x1u << 24) /**< \brief (RTC_MR) 15.6 ms */
    04492 #define   RTC_MR_THIGH_H_4MS (0x2u << 24) /**< \brief (RTC_MR) 3.91 ms */
    04493 #define   RTC_MR_THIGH_H_967US (0x3u << 24) /**< \brief (RTC_MR) 967 \xb5 s */
    04494 #define   RTC_MR_THIGH_H_488US (0x4u << 24) /**< \brief (RTC_MR) 488 \xb5 s */
    04495 #define   RTC_MR_THIGH_H_122US (0x5u << 24) /**< \brief (RTC_MR) 122 \xb5 s */
    04496 #define   RTC_MR_THIGH_H_30US (0x6u << 24) /**< \brief (RTC_MR) 30.5 \xb5 s */
    04497 #define   RTC_MR_THIGH_H_15US (0x7u << 24) /**< \brief (RTC_MR) 15.2 \xb5 s */
    04498 #define RTC_MR_TPERIOD_Pos 28
    04499 #define RTC_MR_TPERIOD_Msk (0x3u << RTC_MR_TPERIOD_Pos) /**< \brief (RTC_MR) Period of the Output Pulse */
    04500 #define   RTC_MR_TPERIOD_P_1S (0x0u << 28) /**< \brief (RTC_MR) 1 second */
    04501 #define   RTC_MR_TPERIOD_P_500MS (0x1u << 28) /**< \brief (RTC_MR) 500 ms */
    04502 #define   RTC_MR_TPERIOD_P_250MS (0x2u << 28) /**< \brief (RTC_MR) 250 ms */
    04503 #define   RTC_MR_TPERIOD_P_125MS (0x3u << 28) /**< \brief (RTC_MR) 125 ms */
    04504 /* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */
    04505 #define RTC_TIMR_SEC_Pos 0
    04506 #define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos) /**< \brief (RTC_TIMR) Current Second */
    04507 #define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos)))
    04508 #define RTC_TIMR_MIN_Pos 8
    04509 #define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos) /**< \brief (RTC_TIMR) Current Minute */
    04510 #define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos)))
    04511 #define RTC_TIMR_HOUR_Pos 16
    04512 #define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos) /**< \brief (RTC_TIMR) Current Hour */
    04513 #define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos)))
    04514 #define RTC_TIMR_AMPM (0x1u << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */
    04515 /* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */
    04516 #define RTC_CALR_CENT_Pos 0
    04517 #define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos) /**< \brief (RTC_CALR) Current Century */
    04518 #define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos)))
    04519 #define RTC_CALR_YEAR_Pos 8
    04520 #define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos) /**< \brief (RTC_CALR) Current Year */
    04521 #define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos)))
    04522 #define RTC_CALR_MONTH_Pos 16
    04523 #define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos) /**< \brief (RTC_CALR) Current Month */
    04524 #define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos)))
    04525 #define RTC_CALR_DAY_Pos 21
    04526 #define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos) /**< \brief (RTC_CALR) Current Day in Current Week */
    04527 #define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos)))
    04528 #define RTC_CALR_DATE_Pos 24
    04529 #define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos) /**< \brief (RTC_CALR) Current Day in Current Month */
    04530 #define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos)))
    04531 /* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */
    04532 #define RTC_TIMALR_SEC_Pos 0
    04533 #define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos) /**< \brief (RTC_TIMALR) Second Alarm */
    04534 #define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos)))
    04535 #define RTC_TIMALR_SECEN (0x1u << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */
    04536 #define RTC_TIMALR_MIN_Pos 8
    04537 #define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos) /**< \brief (RTC_TIMALR) Minute Alarm */
    04538 #define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos)))
    04539 #define RTC_TIMALR_MINEN (0x1u << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */
    04540 #define RTC_TIMALR_HOUR_Pos 16
    04541 #define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos) /**< \brief (RTC_TIMALR) Hour Alarm */
    04542 #define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos)))
    04543 #define RTC_TIMALR_AMPM (0x1u << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */
    04544 #define RTC_TIMALR_HOUREN (0x1u << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */
    04545 /* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */
    04546 #define RTC_CALALR_MONTH_Pos 16
    04547 #define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos) /**< \brief (RTC_CALALR) Month Alarm */
    04548 #define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos)))
    04549 #define RTC_CALALR_MTHEN (0x1u << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */
    04550 #define RTC_CALALR_DATE_Pos 24
    04551 #define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos) /**< \brief (RTC_CALALR) Date Alarm */
    04552 #define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos)))
    04553 #define RTC_CALALR_DATEEN (0x1u << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */
    04554 /* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */
    04555 #define RTC_SR_ACKUPD (0x1u << 0) /**< \brief (RTC_SR) Acknowledge for Update */
    04556 #define RTC_SR_ALARM (0x1u << 1) /**< \brief (RTC_SR) Alarm Flag */
    04557 #define RTC_SR_SEC (0x1u << 2) /**< \brief (RTC_SR) Second Event */
    04558 #define RTC_SR_TIMEV (0x1u << 3) /**< \brief (RTC_SR) Time Event */
    04559 #define RTC_SR_CALEV (0x1u << 4) /**< \brief (RTC_SR) Calendar Event */
    04560 /* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */
    04561 #define RTC_SCCR_ACKCLR (0x1u << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */
    04562 #define RTC_SCCR_ALRCLR (0x1u << 1) /**< \brief (RTC_SCCR) Alarm Clear */
    04563 #define RTC_SCCR_SECCLR (0x1u << 2) /**< \brief (RTC_SCCR) Second Clear */
    04564 #define RTC_SCCR_TIMCLR (0x1u << 3) /**< \brief (RTC_SCCR) Time Clear */
    04565 #define RTC_SCCR_CALCLR (0x1u << 4) /**< \brief (RTC_SCCR) Calendar Clear */
    04566 /* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */
    04567 #define RTC_IER_ACKEN (0x1u << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */
    04568 #define RTC_IER_ALREN (0x1u << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */
    04569 #define RTC_IER_SECEN (0x1u << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */
    04570 #define RTC_IER_TIMEN (0x1u << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */
    04571 #define RTC_IER_CALEN (0x1u << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */
    04572 /* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */
    04573 #define RTC_IDR_ACKDIS (0x1u << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */
    04574 #define RTC_IDR_ALRDIS (0x1u << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */
    04575 #define RTC_IDR_SECDIS (0x1u << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */
    04576 #define RTC_IDR_TIMDIS (0x1u << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */
    04577 #define RTC_IDR_CALDIS (0x1u << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */
    04578 /* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */
    04579 #define RTC_IMR_ACK (0x1u << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */
    04580 #define RTC_IMR_ALR (0x1u << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */
    04581 #define RTC_IMR_SEC (0x1u << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */
    04582 #define RTC_IMR_TIM (0x1u << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */
    04583 #define RTC_IMR_CAL (0x1u << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */
    04584 /* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */
    04585 #define RTC_VER_NVTIM (0x1u << 0) /**< \brief (RTC_VER) Non-valid Time */
    04586 #define RTC_VER_NVCAL (0x1u << 1) /**< \brief (RTC_VER) Non-valid Calendar */
    04587 #define RTC_VER_NVTIMALR (0x1u << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */
    04588 #define RTC_VER_NVCALALR (0x1u << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */
    04589
    04590 /*@}*/
    04591
    04592 /* ============================================================================= */
    04593 /**  SOFTWARE API DEFINITION FOR Real-time Timer */
    04594 /* ============================================================================= */
    04595 /** \addtogroup SAM3S8_RTT Real-time Timer */
    04596 /*@{*/
    04597
    04598 #ifndef __ASSEMBLY__
    04599 /** \brief Rtt hardware registers */
    04600 typedef struct {
    04601   RwReg RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */
    04602   RwReg RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */
    04603   RoReg RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */
    04604   RoReg RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */
    04605 } Rtt;
    04606 #endif /* __ASSEMBLY__ */
    04607 /* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */
    04608 #define RTT_MR_RTPRES_Pos 0
    04609 #define RTT_MR_RTPRES_Msk (0xffffu << RTT_MR_RTPRES_Pos) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */
    04610 #define RTT_MR_RTPRES(value) ((RTT_MR_RTPRES_Msk & ((value) << RTT_MR_RTPRES_Pos)))
    04611 #define RTT_MR_ALMIEN (0x1u << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */
    04612 #define RTT_MR_RTTINCIEN (0x1u << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */
    04613 #define RTT_MR_RTTRST (0x1u << 18) /**< \brief (RTT_MR) Real-time Timer Restart */
    04614 /* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */
    04615 #define RTT_AR_ALMV_Pos 0
    04616 #define RTT_AR_ALMV_Msk (0xffffffffu << RTT_AR_ALMV_Pos) /**< \brief (RTT_AR) Alarm Value */
    04617 #define RTT_AR_ALMV(value) ((RTT_AR_ALMV_Msk & ((value) << RTT_AR_ALMV_Pos)))
    04618 /* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */
    04619 #define RTT_VR_CRTV_Pos 0
    04620 #define RTT_VR_CRTV_Msk (0xffffffffu << RTT_VR_CRTV_Pos) /**< \brief (RTT_VR) Current Real-time Value */
    04621 /* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */
    04622 #define RTT_SR_ALMS (0x1u << 0) /**< \brief (RTT_SR) Real-time Alarm Status */
    04623 #define RTT_SR_RTTINC (0x1u << 1) /**< \brief (RTT_SR) Real-time Timer Increment */
    04624
    04625 /*@}*/
    04626
    04627 /* ============================================================================= */
    04628 /**  SOFTWARE API DEFINITION FOR Static Memory Controller */
    04629 /* ============================================================================= */
    04630 /** \addtogroup SAM3S8_SMC Static Memory Controller */
    04631 /*@{*/
    04632
    04633 #ifndef __ASSEMBLY__
    04634 /** \brief SmcCs_number hardware registers */
    04635 typedef struct {
    04636   RwReg         SMC_SETUP;        /**< \brief (SmcCs_number Offset: 0x0) SMC Setup Register */
    04637   RwReg         SMC_PULSE;        /**< \brief (SmcCs_number Offset: 0x4) SMC Pulse Register */
    04638   RwReg         SMC_CYCLE;        /**< \brief (SmcCs_number Offset: 0x8) SMC Cycle Register */
    04639   RwReg         SMC_MODE;         /**< \brief (SmcCs_number Offset: 0xC) SMC Mode Register */
    04640 } SmcCs_number;
    04641 /** \brief Smc hardware registers */
    04642 #define SMCCS_NUMBER_NUMBER 5
    04643 typedef struct {
    04644   SmcCs_number  SMC_CS_NUMBER[SMCCS_NUMBER_NUMBER]; /**< \brief (Smc Offset: 0x0) CS_number = 0 .. 4 */
    04645   RoReg         Reserved1[12];
    04646   RwReg         SMC_OCMS;         /**< \brief (Smc Offset: 0x80) SMC OCMS MODE Register */
    04647   WoReg         SMC_KEY1;         /**< \brief (Smc Offset: 0x84) SMC OCMS KEY1 Register */
    04648   WoReg         SMC_KEY2;         /**< \brief (Smc Offset: 0x88) SMC OCMS KEY2 Register */
    04649   RoReg         Reserved2[22];
    04650   RwReg         SMC_WPMR;         /**< \brief (Smc Offset: 0xE4) SMC Write Protect Mode Register */
    04651   RoReg         SMC_WPSR;         /**< \brief (Smc Offset: 0xE8) SMC Write Protect Status Register */
    04652 } Smc;
    04653 #endif /* __ASSEMBLY__ */
    04654 /* -------- SMC_SETUP : (SMC Offset: N/A) SMC Setup Register -------- */
    04655 #define SMC_SETUP_NWE_SETUP_Pos 0
    04656 #define SMC_SETUP_NWE_SETUP_Msk (0x3fu << SMC_SETUP_NWE_SETUP_Pos) /**< \brief (SMC_SETUP) NWE Setup Length */
    04657 #define SMC_SETUP_NWE_SETUP(value) ((SMC_SETUP_NWE_SETUP_Msk & ((value) << SMC_SETUP_NWE_SETUP_Pos)))
    04658 #define SMC_SETUP_NCS_WR_SETUP_Pos 8
    04659 #define SMC_SETUP_NCS_WR_SETUP_Msk (0x3fu << SMC_SETUP_NCS_WR_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in WRITE Access */
    04660 #define SMC_SETUP_NCS_WR_SETUP(value) ((SMC_SETUP_NCS_WR_SETUP_Msk & ((value) << SMC_SETUP_NCS_WR_SETUP_Pos)))
    04661 #define SMC_SETUP_NRD_SETUP_Pos 16
    04662 #define SMC_SETUP_NRD_SETUP_Msk (0x3fu << SMC_SETUP_NRD_SETUP_Pos) /**< \brief (SMC_SETUP) NRD Setup Length */
    04663 #define SMC_SETUP_NRD_SETUP(value) ((SMC_SETUP_NRD_SETUP_Msk & ((value) << SMC_SETUP_NRD_SETUP_Pos)))
    04664 #define SMC_SETUP_NCS_RD_SETUP_Pos 24
    04665 #define SMC_SETUP_NCS_RD_SETUP_Msk (0x3fu << SMC_SETUP_NCS_RD_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in READ Access */
    04666 #define SMC_SETUP_NCS_RD_SETUP(value) ((SMC_SETUP_NCS_RD_SETUP_Msk & ((value) << SMC_SETUP_NCS_RD_SETUP_Pos)))
    04667 /* -------- SMC_PULSE : (SMC Offset: N/A) SMC Pulse Register -------- */
    04668 #define SMC_PULSE_NWE_PULSE_Pos 0
    04669 #define SMC_PULSE_NWE_PULSE_Msk (0x7fu << SMC_PULSE_NWE_PULSE_Pos) /**< \brief (SMC_PULSE) NWE Pulse Length */
    04670 #define SMC_PULSE_NWE_PULSE(value) ((SMC_PULSE_NWE_PULSE_Msk & ((value) << SMC_PULSE_NWE_PULSE_Pos)))
    04671 #define SMC_PULSE_NCS_WR_PULSE_Pos 8
    04672 #define SMC_PULSE_NCS_WR_PULSE_Msk (0x7fu << SMC_PULSE_NCS_WR_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in WRITE Access */
    04673 #define SMC_PULSE_NCS_WR_PULSE(value) ((SMC_PULSE_NCS_WR_PULSE_Msk & ((value) << SMC_PULSE_NCS_WR_PULSE_Pos)))
    04674 #define SMC_PULSE_NRD_PULSE_Pos 16
    04675 #define SMC_PULSE_NRD_PULSE_Msk (0x7fu << SMC_PULSE_NRD_PULSE_Pos) /**< \brief (SMC_PULSE) NRD Pulse Length */
    04676 #define SMC_PULSE_NRD_PULSE(value) ((SMC_PULSE_NRD_PULSE_Msk & ((value) << SMC_PULSE_NRD_PULSE_Pos)))
    04677 #define SMC_PULSE_NCS_RD_PULSE_Pos 24
    04678 #define SMC_PULSE_NCS_RD_PULSE_Msk (0x7fu << SMC_PULSE_NCS_RD_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in READ Access */
    04679 #define SMC_PULSE_NCS_RD_PULSE(value) ((SMC_PULSE_NCS_RD_PULSE_Msk & ((value) << SMC_PULSE_NCS_RD_PULSE_Pos)))
    04680 /* -------- SMC_CYCLE : (SMC Offset: N/A) SMC Cycle Register -------- */
    04681 #define SMC_CYCLE_NWE_CYCLE_Pos 0
    04682 #define SMC_CYCLE_NWE_CYCLE_Msk (0x1ffu << SMC_CYCLE_NWE_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Write Cycle Length */
    04683 #define SMC_CYCLE_NWE_CYCLE(value) ((SMC_CYCLE_NWE_CYCLE_Msk & ((value) << SMC_CYCLE_NWE_CYCLE_Pos)))
    04684 #define SMC_CYCLE_NRD_CYCLE_Pos 16
    04685 #define SMC_CYCLE_NRD_CYCLE_Msk (0x1ffu << SMC_CYCLE_NRD_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Read Cycle Length */
    04686 #define SMC_CYCLE_NRD_CYCLE(value) ((SMC_CYCLE_NRD_CYCLE_Msk & ((value) << SMC_CYCLE_NRD_CYCLE_Pos)))
    04687 /* -------- SMC_MODE : (SMC Offset: N/A) SMC Mode Register -------- */
    04688 #define SMC_MODE_READ_MODE (0x1u << 0) /**< \brief (SMC_MODE)  */
    04689 #define SMC_MODE_WRITE_MODE (0x1u << 1) /**< \brief (SMC_MODE)  */
    04690 #define SMC_MODE_EXNW_MODE_Pos 4
    04691 #define SMC_MODE_EXNW_MODE_Msk (0x3u << SMC_MODE_EXNW_MODE_Pos) /**< \brief (SMC_MODE) NWAIT Mode */
    04692 #define   SMC_MODE_EXNW_MODE_DISABLED (0x0u << 4) /**< \brief (SMC_MODE) Disabled */
    04693 #define   SMC_MODE_EXNW_MODE_FROZEN (0x2u << 4) /**< \brief (SMC_MODE) Frozen Mode */
    04694 #define   SMC_MODE_EXNW_MODE_READY (0x3u << 4) /**< \brief (SMC_MODE) Ready Mode */
    04695 #define SMC_MODE_DBW_Pos 12
    04696 #define SMC_MODE_DBW_Msk (0x3u << SMC_MODE_DBW_Pos) /**< \brief (SMC_MODE) Data Bus Width */
    04697 #define   SMC_MODE_DBW_8_BIT (0x0u << 12) /**< \brief (SMC_MODE) 8-bit bus */
    04698 #define   SMC_MODE_DBW_16_BIT (0x1u << 12) /**< \brief (SMC_MODE) 16-bit bus */
    04699 #define   SMC_MODE_DBW_32_BIT (0x2u << 12) /**< \brief (SMC_MODE) 32-bit bus */
    04700 #define SMC_MODE_TDF_CYCLES_Pos 16
    04701 #define SMC_MODE_TDF_CYCLES_Msk (0xfu << SMC_MODE_TDF_CYCLES_Pos) /**< \brief (SMC_MODE) Data Float Time */
    04702 #define SMC_MODE_TDF_CYCLES(value) ((SMC_MODE_TDF_CYCLES_Msk & ((value) << SMC_MODE_TDF_CYCLES_Pos)))
    04703 #define SMC_MODE_TDF_MODE (0x1u << 20) /**< \brief (SMC_MODE) TDF Optimization */
    04704 #define SMC_MODE_PMEN (0x1u << 24) /**< \brief (SMC_MODE) Page Mode Enabled */
    04705 #define SMC_MODE_PS_Pos 28
    04706 #define SMC_MODE_PS_Msk (0x3u << SMC_MODE_PS_Pos) /**< \brief (SMC_MODE) Page Size */
    04707 #define   SMC_MODE_PS_4_BYTE (0x0u << 28) /**< \brief (SMC_MODE) 4-byte page */
    04708 #define   SMC_MODE_PS_8_BYTE (0x1u << 28) /**< \brief (SMC_MODE) 8-byte page */
    04709 #define   SMC_MODE_PS_16_BYTE (0x2u << 28) /**< \brief (SMC_MODE) 16-byte page */
    04710 #define   SMC_MODE_PS_32_BYTE (0x3u << 28) /**< \brief (SMC_MODE) 32-byte page */
    04711 /* -------- SMC_OCMS : (SMC Offset: 0x80) SMC OCMS MODE Register -------- */
    04712 #define SMC_OCMS_SMSE (0x1u << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */
    04713 #define SMC_OCMS_CS0SE (0x1u << 16) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */
    04714 #define SMC_OCMS_CS1SE (0x1u << 17) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */
    04715 #define SMC_OCMS_CS2SE (0x1u << 18) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */
    04716 #define SMC_OCMS_CS3SE (0x1u << 19) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */
    04717 /* -------- SMC_KEY1 : (SMC Offset: 0x84) SMC OCMS KEY1 Register -------- */
    04718 #define SMC_KEY1_KEY1_Pos 0
    04719 #define SMC_KEY1_KEY1_Msk (0xffffffffu << SMC_KEY1_KEY1_Pos) /**< \brief (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */
    04720 #define SMC_KEY1_KEY1(value) ((SMC_KEY1_KEY1_Msk & ((value) << SMC_KEY1_KEY1_Pos)))
    04721 /* -------- SMC_KEY2 : (SMC Offset: 0x88) SMC OCMS KEY2 Register -------- */
    04722 #define SMC_KEY2_KEY2_Pos 0
    04723 #define SMC_KEY2_KEY2_Msk (0xffffffffu << SMC_KEY2_KEY2_Pos) /**< \brief (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */
    04724 #define SMC_KEY2_KEY2(value) ((SMC_KEY2_KEY2_Msk & ((value) << SMC_KEY2_KEY2_Pos)))
    04725 /* -------- SMC_WPMR : (SMC Offset: 0xE4) SMC Write Protect Mode Register -------- */
    04726 #define SMC_WPMR_WPEN (0x1u << 0) /**< \brief (SMC_WPMR) Write Protect Enable */
    04727 #define SMC_WPMR_WPKEY_Pos 8
    04728 #define SMC_WPMR_WPKEY_Msk (0xffffffu << SMC_WPMR_WPKEY_Pos) /**< \brief (SMC_WPMR) Write Protect KEY */
    04729 #define SMC_WPMR_WPKEY(value) ((SMC_WPMR_WPKEY_Msk & ((value) << SMC_WPMR_WPKEY_Pos)))
    04730 /* -------- SMC_WPSR : (SMC Offset: 0xE8) SMC Write Protect Status Register -------- */
    04731 #define SMC_WPSR_WPVS (0x1u << 0) /**< \brief (SMC_WPSR) Write Protect Enable */
    04732 #define SMC_WPSR_WPVSRC_Pos 8
    04733 #define SMC_WPSR_WPVSRC_Msk (0xffffu << SMC_WPSR_WPVSRC_Pos) /**< \brief (SMC_WPSR) Write Protect Violation Source */
    04734
    04735 /*@}*/
    04736
    04737 /* ============================================================================= */
    04738 /**  SOFTWARE API DEFINITION FOR Serial Peripheral Interface */
    04739 /* ============================================================================= */
    04740 /** \addtogroup SAM3S8_SPI Serial Peripheral Interface */
    04741 /*@{*/
    04742
    04743 #ifndef __ASSEMBLY__
    04744 /** \brief Spi hardware registers */
    04745 typedef struct {
    04746   WoReg SPI_CR;        /**< \brief (Spi Offset: 0x00) Control Register */
    04747   RwReg SPI_MR;        /**< \brief (Spi Offset: 0x04) Mode Register */
    04748   RoReg SPI_RDR;       /**< \brief (Spi Offset: 0x08) Receive Data Register */
    04749   WoReg SPI_TDR;       /**< \brief (Spi Offset: 0x0C) Transmit Data Register */
    04750   RoReg SPI_SR;        /**< \brief (Spi Offset: 0x10) Status Register */
    04751   WoReg SPI_IER;       /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */
    04752   WoReg SPI_IDR;       /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */
    04753   RoReg SPI_IMR;       /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */
    04754   RoReg Reserved1[4];
    04755   RwReg SPI_CSR[4];    /**< \brief (Spi Offset: 0x30) Chip Select Register */
    04756   RoReg Reserved2[41];
    04757   RwReg SPI_WPMR;      /**< \brief (Spi Offset: 0xE4) Write Protection Control Register */
    04758   RoReg SPI_WPSR;      /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */
    04759   RoReg Reserved3[5];
    04760   RwReg SPI_RPR;       /**< \brief (Spi Offset: 0x100) Receive Pointer Register */
    04761   RwReg SPI_RCR;       /**< \brief (Spi Offset: 0x104) Receive Counter Register */
    04762   RwReg SPI_TPR;       /**< \brief (Spi Offset: 0x108) Transmit Pointer Register */
    04763   RwReg SPI_TCR;       /**< \brief (Spi Offset: 0x10C) Transmit Counter Register */
    04764   RwReg SPI_RNPR;      /**< \brief (Spi Offset: 0x110) Receive Next Pointer Register */
    04765   RwReg SPI_RNCR;      /**< \brief (Spi Offset: 0x114) Receive Next Counter Register */
    04766   RwReg SPI_TNPR;      /**< \brief (Spi Offset: 0x118) Transmit Next Pointer Register */
    04767   RwReg SPI_TNCR;      /**< \brief (Spi Offset: 0x11C) Transmit Next Counter Register */
    04768   WoReg SPI_PTCR;      /**< \brief (Spi Offset: 0x120) Transfer Control Register */
    04769   RoReg SPI_PTSR;      /**< \brief (Spi Offset: 0x124) Transfer Status Register */
    04770 } Spi;
    04771 #endif /* __ASSEMBLY__ */
    04772 /* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */
    04773 #define SPI_CR_SPIEN (0x1u << 0) /**< \brief (SPI_CR) SPI Enable */
    04774 #define SPI_CR_SPIDIS (0x1u << 1) /**< \brief (SPI_CR) SPI Disable */
    04775 #define SPI_CR_SWRST (0x1u << 7) /**< \brief (SPI_CR) SPI Software Reset */
    04776 #define SPI_CR_LASTXFER (0x1u << 24) /**< \brief (SPI_CR) Last Transfer */
    04777 /* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */
    04778 #define SPI_MR_MSTR (0x1u << 0) /**< \brief (SPI_MR) Master/Slave Mode */
    04779 #define SPI_MR_PS (0x1u << 1) /**< \brief (SPI_MR) Peripheral Select */
    04780 #define SPI_MR_PCSDEC (0x1u << 2) /**< \brief (SPI_MR) Chip Select Decode */
    04781 #define SPI_MR_MODFDIS (0x1u << 4) /**< \brief (SPI_MR) Mode Fault Detection */
    04782 #define SPI_MR_WDRBT (0x1u << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */
    04783 #define SPI_MR_LLB (0x1u << 7) /**< \brief (SPI_MR) Local Loopback Enable */
    04784 #define SPI_MR_PCS_Pos 16
    04785 #define SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos) /**< \brief (SPI_MR) Peripheral Chip Select */
    04786 #define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos)))
    04787 #define SPI_MR_DLYBCS_Pos 24
    04788 #define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos) /**< \brief (SPI_MR) Delay Between Chip Selects */
    04789 #define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos)))
    04790 /* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */
    04791 #define SPI_RDR_RD_Pos 0
    04792 #define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos) /**< \brief (SPI_RDR) Receive Data */
    04793 #define SPI_RDR_PCS_Pos 16
    04794 #define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos) /**< \brief (SPI_RDR) Peripheral Chip Select */
    04795 /* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */
    04796 #define SPI_TDR_TD_Pos 0
    04797 #define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos) /**< \brief (SPI_TDR) Transmit Data */
    04798 #define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos)))
    04799 #define SPI_TDR_PCS_Pos 16
    04800 #define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos) /**< \brief (SPI_TDR) Peripheral Chip Select */
    04801 #define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos)))
    04802 #define SPI_TDR_LASTXFER (0x1u << 24) /**< \brief (SPI_TDR) Last Transfer */
    04803 /* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
    04804 #define SPI_SR_RDRF (0x1u << 0) /**< \brief (SPI_SR) Receive Data Register Full */
    04805 #define SPI_SR_TDRE (0x1u << 1) /**< \brief (SPI_SR) Transmit Data Register Empty */
    04806 #define SPI_SR_MODF (0x1u << 2) /**< \brief (SPI_SR) Mode Fault Error */
    04807 #define SPI_SR_OVRES (0x1u << 3) /**< \brief (SPI_SR) Overrun Error Status */
    04808 #define SPI_SR_ENDRX (0x1u << 4) /**< \brief (SPI_SR) End of RX buffer */
    04809 #define SPI_SR_ENDTX (0x1u << 5) /**< \brief (SPI_SR) End of TX buffer */
    04810 #define SPI_SR_RXBUFF (0x1u << 6) /**< \brief (SPI_SR) RX Buffer Full */
    04811 #define SPI_SR_TXBUFE (0x1u << 7) /**< \brief (SPI_SR) TX Buffer Empty */
    04812 #define SPI_SR_NSSR (0x1u << 8) /**< \brief (SPI_SR) NSS Rising */
    04813 #define SPI_SR_TXEMPTY (0x1u << 9) /**< \brief (SPI_SR) Transmission Registers Empty */
    04814 #define SPI_SR_UNDES (0x1u << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave Mode Only) */
    04815 #define SPI_SR_SPIENS (0x1u << 16) /**< \brief (SPI_SR) SPI Enable Status */
    04816 /* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
    04817 #define SPI_IER_RDRF (0x1u << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */
    04818 #define SPI_IER_TDRE (0x1u << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */
    04819 #define SPI_IER_MODF (0x1u << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */
    04820 #define SPI_IER_OVRES (0x1u << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */
    04821 #define SPI_IER_ENDRX (0x1u << 4) /**< \brief (SPI_IER) End of Receive Buffer Interrupt Enable */
    04822 #define SPI_IER_ENDTX (0x1u << 5) /**< \brief (SPI_IER) End of Transmit Buffer Interrupt Enable */
    04823 #define SPI_IER_RXBUFF (0x1u << 6) /**< \brief (SPI_IER) Receive Buffer Full Interrupt Enable */
    04824 #define SPI_IER_TXBUFE (0x1u << 7) /**< \brief (SPI_IER) Transmit Buffer Empty Interrupt Enable */
    04825 #define SPI_IER_NSSR (0x1u << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */
    04826 #define SPI_IER_TXEMPTY (0x1u << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */
    04827 #define SPI_IER_UNDES (0x1u << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */
    04828 /* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
    04829 #define SPI_IDR_RDRF (0x1u << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */
    04830 #define SPI_IDR_TDRE (0x1u << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */
    04831 #define SPI_IDR_MODF (0x1u << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */
    04832 #define SPI_IDR_OVRES (0x1u << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */
    04833 #define SPI_IDR_ENDRX (0x1u << 4) /**< \brief (SPI_IDR) End of Receive Buffer Interrupt Disable */
    04834 #define SPI_IDR_ENDTX (0x1u << 5) /**< \brief (SPI_IDR) End of Transmit Buffer Interrupt Disable */
    04835 #define SPI_IDR_RXBUFF (0x1u << 6) /**< \brief (SPI_IDR) Receive Buffer Full Interrupt Disable */
    04836 #define SPI_IDR_TXBUFE (0x1u << 7) /**< \brief (SPI_IDR) Transmit Buffer Empty Interrupt Disable */
    04837 #define SPI_IDR_NSSR (0x1u << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */
    04838 #define SPI_IDR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */
    04839 #define SPI_IDR_UNDES (0x1u << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */
    04840 /* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */
    04841 #define SPI_IMR_RDRF (0x1u << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */
    04842 #define SPI_IMR_TDRE (0x1u << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */
    04843 #define SPI_IMR_MODF (0x1u << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */
    04844 #define SPI_IMR_OVRES (0x1u << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */
    04845 #define SPI_IMR_ENDRX (0x1u << 4) /**< \brief (SPI_IMR) End of Receive Buffer Interrupt Mask */
    04846 #define SPI_IMR_ENDTX (0x1u << 5) /**< \brief (SPI_IMR) End of Transmit Buffer Interrupt Mask */
    04847 #define SPI_IMR_RXBUFF (0x1u << 6) /**< \brief (SPI_IMR) Receive Buffer Full Interrupt Mask */
    04848 #define SPI_IMR_TXBUFE (0x1u << 7) /**< \brief (SPI_IMR) Transmit Buffer Empty Interrupt Mask */
    04849 #define SPI_IMR_NSSR (0x1u << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */
    04850 #define SPI_IMR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */
    04851 #define SPI_IMR_UNDES (0x1u << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */
    04852 /* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */
    04853 #define SPI_CSR_CPOL (0x1u << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */
    04854 #define SPI_CSR_NCPHA (0x1u << 1) /**< \brief (SPI_CSR[4]) Clock Phase */
    04855 #define SPI_CSR_CSNAAT (0x1u << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */
    04856 #define SPI_CSR_CSAAT (0x1u << 3) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */
    04857 #define SPI_CSR_BITS_Pos 4
    04858 #define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos) /**< \brief (SPI_CSR[4]) Bits Per Transfer */
    04859 #define   SPI_CSR_BITS_8_BIT (0x0u << 4) /**< \brief (SPI_CSR[4]) 8 bits for transfer */
    04860 #define   SPI_CSR_BITS_9_BIT (0x1u << 4) /**< \brief (SPI_CSR[4]) 9 bits for transfer */
    04861 #define   SPI_CSR_BITS_10_BIT (0x2u << 4) /**< \brief (SPI_CSR[4]) 10 bits for transfer */
    04862 #define   SPI_CSR_BITS_11_BIT (0x3u << 4) /**< \brief (SPI_CSR[4]) 11 bits for transfer */
    04863 #define   SPI_CSR_BITS_12_BIT (0x4u << 4) /**< \brief (SPI_CSR[4]) 12 bits for transfer */
    04864 #define   SPI_CSR_BITS_13_BIT (0x5u << 4) /**< \brief (SPI_CSR[4]) 13 bits for transfer */
    04865 #define   SPI_CSR_BITS_14_BIT (0x6u << 4) /**< \brief (SPI_CSR[4]) 14 bits for transfer */
    04866 #define   SPI_CSR_BITS_15_BIT (0x7u << 4) /**< \brief (SPI_CSR[4]) 15 bits for transfer */
    04867 #define   SPI_CSR_BITS_16_BIT (0x8u << 4) /**< \brief (SPI_CSR[4]) 16 bits for transfer */
    04868 #define SPI_CSR_SCBR_Pos 8
    04869 #define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos) /**< \brief (SPI_CSR[4]) Serial Clock Baud Rate */
    04870 #define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos)))
    04871 #define SPI_CSR_DLYBS_Pos 16
    04872 #define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos) /**< \brief (SPI_CSR[4]) Delay Before SPCK */
    04873 #define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos)))
    04874 #define SPI_CSR_DLYBCT_Pos 24
    04875 #define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */
    04876 #define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos)))
    04877 /* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Control Register -------- */
    04878 #define SPI_WPMR_SPIWPEN (0x1u << 0) /**< \brief (SPI_WPMR) SPI Write Protection Enable */
    04879 #define SPI_WPMR_SPIWPKEY_Pos 8
    04880 #define SPI_WPMR_SPIWPKEY_Msk (0xffffffu << SPI_WPMR_SPIWPKEY_Pos) /**< \brief (SPI_WPMR) SPI Write Protection Key Password */
    04881 #define SPI_WPMR_SPIWPKEY(value) ((SPI_WPMR_SPIWPKEY_Msk & ((value) << SPI_WPMR_SPIWPKEY_Pos)))
    04882 /* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */
    04883 #define SPI_WPSR_SPIWPVS_Pos 0
    04884 #define SPI_WPSR_SPIWPVS_Msk (0x7u << SPI_WPSR_SPIWPVS_Pos) /**< \brief (SPI_WPSR) SPI Write Protection Violation Status */
    04885 #define SPI_WPSR_SPIWPVSRC_Pos 8
    04886 #define SPI_WPSR_SPIWPVSRC_Msk (0xffu << SPI_WPSR_SPIWPVSRC_Pos) /**< \brief (SPI_WPSR) SPI Write Protection Violation Source */
    04887 /* -------- SPI_RPR : (SPI Offset: 0x100) Receive Pointer Register -------- */
    04888 #define SPI_RPR_RXPTR_Pos 0
    04889 #define SPI_RPR_RXPTR_Msk (0xffffffffu << SPI_RPR_RXPTR_Pos) /**< \brief (SPI_RPR) Receive Pointer Register */
    04890 #define SPI_RPR_RXPTR(value) ((SPI_RPR_RXPTR_Msk & ((value) << SPI_RPR_RXPTR_Pos)))
    04891 /* -------- SPI_RCR : (SPI Offset: 0x104) Receive Counter Register -------- */
    04892 #define SPI_RCR_RXCTR_Pos 0
    04893 #define SPI_RCR_RXCTR_Msk (0xffffu << SPI_RCR_RXCTR_Pos) /**< \brief (SPI_RCR) Receive Counter Register */
    04894 #define SPI_RCR_RXCTR(value) ((SPI_RCR_RXCTR_Msk & ((value) << SPI_RCR_RXCTR_Pos)))
    04895 /* -------- SPI_TPR : (SPI Offset: 0x108) Transmit Pointer Register -------- */
    04896 #define SPI_TPR_TXPTR_Pos 0
    04897 #define SPI_TPR_TXPTR_Msk (0xffffffffu << SPI_TPR_TXPTR_Pos) /**< \brief (SPI_TPR) Transmit Counter Register */
    04898 #define SPI_TPR_TXPTR(value) ((SPI_TPR_TXPTR_Msk & ((value) << SPI_TPR_TXPTR_Pos)))
    04899 /* -------- SPI_TCR : (SPI Offset: 0x10C) Transmit Counter Register -------- */
    04900 #define SPI_TCR_TXCTR_Pos 0
    04901 #define SPI_TCR_TXCTR_Msk (0xffffu << SPI_TCR_TXCTR_Pos) /**< \brief (SPI_TCR) Transmit Counter Register */
    04902 #define SPI_TCR_TXCTR(value) ((SPI_TCR_TXCTR_Msk & ((value) << SPI_TCR_TXCTR_Pos)))
    04903 /* -------- SPI_RNPR : (SPI Offset: 0x110) Receive Next Pointer Register -------- */
    04904 #define SPI_RNPR_RXNPTR_Pos 0
    04905 #define SPI_RNPR_RXNPTR_Msk (0xffffffffu << SPI_RNPR_RXNPTR_Pos) /**< \brief (SPI_RNPR) Receive Next Pointer */
    04906 #define SPI_RNPR_RXNPTR(value) ((SPI_RNPR_RXNPTR_Msk & ((value) << SPI_RNPR_RXNPTR_Pos)))
    04907 /* -------- SPI_RNCR : (SPI Offset: 0x114) Receive Next Counter Register -------- */
    04908 #define SPI_RNCR_RXNCTR_Pos 0
    04909 #define SPI_RNCR_RXNCTR_Msk (0xffffu << SPI_RNCR_RXNCTR_Pos) /**< \brief (SPI_RNCR) Receive Next Counter */
    04910 #define SPI_RNCR_RXNCTR(value) ((SPI_RNCR_RXNCTR_Msk & ((value) << SPI_RNCR_RXNCTR_Pos)))
    04911 /* -------- SPI_TNPR : (SPI Offset: 0x118) Transmit Next Pointer Register -------- */
    04912 #define SPI_TNPR_TXNPTR_Pos 0
    04913 #define SPI_TNPR_TXNPTR_Msk (0xffffffffu << SPI_TNPR_TXNPTR_Pos) /**< \brief (SPI_TNPR) Transmit Next Pointer */
    04914 #define SPI_TNPR_TXNPTR(value) ((SPI_TNPR_TXNPTR_Msk & ((value) << SPI_TNPR_TXNPTR_Pos)))
    04915 /* -------- SPI_TNCR : (SPI Offset: 0x11C) Transmit Next Counter Register -------- */
    04916 #define SPI_TNCR_TXNCTR_Pos 0
    04917 #define SPI_TNCR_TXNCTR_Msk (0xffffu << SPI_TNCR_TXNCTR_Pos) /**< \brief (SPI_TNCR) Transmit Counter Next */
    04918 #define SPI_TNCR_TXNCTR(value) ((SPI_TNCR_TXNCTR_Msk & ((value) << SPI_TNCR_TXNCTR_Pos)))
    04919 /* -------- SPI_PTCR : (SPI Offset: 0x120) Transfer Control Register -------- */
    04920 #define SPI_PTCR_RXTEN (0x1u << 0) /**< \brief (SPI_PTCR) Receiver Transfer Enable */
    04921 #define SPI_PTCR_RXTDIS (0x1u << 1) /**< \brief (SPI_PTCR) Receiver Transfer Disable */
    04922 #define SPI_PTCR_TXTEN (0x1u << 8) /**< \brief (SPI_PTCR) Transmitter Transfer Enable */
    04923 #define SPI_PTCR_TXTDIS (0x1u << 9) /**< \brief (SPI_PTCR) Transmitter Transfer Disable */
    04924 /* -------- SPI_PTSR : (SPI Offset: 0x124) Transfer Status Register -------- */
    04925 #define SPI_PTSR_RXTEN (0x1u << 0) /**< \brief (SPI_PTSR) Receiver Transfer Enable */
    04926 #define SPI_PTSR_TXTEN (0x1u << 8) /**< \brief (SPI_PTSR) Transmitter Transfer Enable */
    04927
    04928 /*@}*/
    04929
    04930 /* ============================================================================= */
    04931 /**  SOFTWARE API DEFINITION FOR Synchronous Serial Controller */
    04932 /* ============================================================================= */
    04933 /** \addtogroup SAM3S8_SSC Synchronous Serial Controller */
    04934 /*@{*/
    04935
    04936 #ifndef __ASSEMBLY__
    04937 /** \brief Ssc hardware registers */
    04938 typedef struct {
    04939   WoReg SSC_CR;        /**< \brief (Ssc Offset: 0x0) Control Register */
    04940   RwReg SSC_CMR;       /**< \brief (Ssc Offset: 0x4) Clock Mode Register */
    04941   RoReg Reserved1[2];
    04942   RwReg SSC_RCMR;      /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */
    04943   RwReg SSC_RFMR;      /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */
    04944   RwReg SSC_TCMR;      /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */
    04945   RwReg SSC_TFMR;      /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */
    04946   RoReg SSC_RHR;       /**< \brief (Ssc Offset: 0x20) Receive Holding Register */
    04947   WoReg SSC_THR;       /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */
    04948   RoReg Reserved2[2];
    04949   RoReg SSC_RSHR;      /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */
    04950   RwReg SSC_TSHR;      /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */
    04951   RwReg SSC_RC0R;      /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */
    04952   RwReg SSC_RC1R;      /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */
    04953   RoReg SSC_SR;        /**< \brief (Ssc Offset: 0x40) Status Register */
    04954   WoReg SSC_IER;       /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */
    04955   WoReg SSC_IDR;       /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */
    04956   RoReg SSC_IMR;       /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */
    04957   RoReg Reserved3[37];
    04958   RwReg SSC_WPMR;      /**< \brief (Ssc Offset: 0xE4) Write Protect Mode Register */
    04959   RoReg SSC_WPSR;      /**< \brief (Ssc Offset: 0xE8) Write Protect Status Register */
    04960   RoReg Reserved4[5];
    04961   RwReg SSC_RPR;       /**< \brief (Ssc Offset: 0x100) Receive Pointer Register */
    04962   RwReg SSC_RCR;       /**< \brief (Ssc Offset: 0x104) Receive Counter Register */
    04963   RwReg SSC_TPR;       /**< \brief (Ssc Offset: 0x108) Transmit Pointer Register */
    04964   RwReg SSC_TCR;       /**< \brief (Ssc Offset: 0x10C) Transmit Counter Register */
    04965   RwReg SSC_RNPR;      /**< \brief (Ssc Offset: 0x110) Receive Next Pointer Register */
    04966   RwReg SSC_RNCR;      /**< \brief (Ssc Offset: 0x114) Receive Next Counter Register */
    04967   RwReg SSC_TNPR;      /**< \brief (Ssc Offset: 0x118) Transmit Next Pointer Register */
    04968   RwReg SSC_TNCR;      /**< \brief (Ssc Offset: 0x11C) Transmit Next Counter Register */
    04969   WoReg SSC_PTCR;      /**< \brief (Ssc Offset: 0x120) Transfer Control Register */
    04970   RoReg SSC_PTSR;      /**< \brief (Ssc Offset: 0x124) Transfer Status Register */
    04971 } Ssc;
    04972 #endif /* __ASSEMBLY__ */
    04973 /* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */
    04974 #define SSC_CR_RXEN (0x1u << 0) /**< \brief (SSC_CR) Receive Enable */
    04975 #define SSC_CR_RXDIS (0x1u << 1) /**< \brief (SSC_CR) Receive Disable */
    04976 #define SSC_CR_TXEN (0x1u << 8) /**< \brief (SSC_CR) Transmit Enable */
    04977 #define SSC_CR_TXDIS (0x1u << 9) /**< \brief (SSC_CR) Transmit Disable */
    04978 #define SSC_CR_SWRST (0x1u << 15) /**< \brief (SSC_CR) Software Reset */
    04979 /* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */
    04980 #define SSC_CMR_DIV_Pos 0
    04981 #define SSC_CMR_DIV_Msk (0xfffu << SSC_CMR_DIV_Pos) /**< \brief (SSC_CMR) Clock Divider */
    04982 #define SSC_CMR_DIV(value) ((SSC_CMR_DIV_Msk & ((value) << SSC_CMR_DIV_Pos)))
    04983 /* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */
    04984 #define SSC_RCMR_CKS_Pos 0
    04985 #define SSC_RCMR_CKS_Msk (0x3u << SSC_RCMR_CKS_Pos) /**< \brief (SSC_RCMR) Receive Clock Selection */
    04986 #define   SSC_RCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_RCMR) Divided Clock */
    04987 #define   SSC_RCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_RCMR) TK Clock signal */
    04988 #define   SSC_RCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_RCMR) RK pin */
    04989 #define SSC_RCMR_CKO_Pos 2
    04990 #define SSC_RCMR_CKO_Msk (0x7u << SSC_RCMR_CKO_Pos) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */
    04991 #define   SSC_RCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_RCMR) None */
    04992 #define   SSC_RCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_RCMR) Continuous Receive Clock */
    04993 #define   SSC_RCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_RCMR) Receive Clock only during data transfers */
    04994 #define SSC_RCMR_CKI (0x1u << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */
    04995 #define SSC_RCMR_CKG_Pos 6
    04996 #define SSC_RCMR_CKG_Msk (0x3u << SSC_RCMR_CKG_Pos) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */
    04997 #define   SSC_RCMR_CKG_NONE (0x0u << 6) /**< \brief (SSC_RCMR) None */
    04998 #define   SSC_RCMR_CKG_CONTINUOUS (0x1u << 6) /**< \brief (SSC_RCMR) Continuous Receive Clock */
    04999 #define   SSC_RCMR_CKG_TRANSFER (0x2u << 6) /**< \brief (SSC_RCMR) Receive Clock only during data transfers */
    05000 #define SSC_RCMR_START_Pos 8
    05001 #define SSC_RCMR_START_Msk (0xfu << SSC_RCMR_START_Pos) /**< \brief (SSC_RCMR) Receive Start Selection */
    05002 #define   SSC_RCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_RCMR) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */
    05003 #define   SSC_RCMR_START_TRANSMIT (0x1u << 8) /**< \brief (SSC_RCMR) Transmit start */
    05004 #define   SSC_RCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_RCMR) Detection of a low level on RF signal */
    05005 #define   SSC_RCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_RCMR) Detection of a high level on RF signal */
    05006 #define   SSC_RCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_RCMR) Detection of a falling edge on RF signal */
    05007 #define   SSC_RCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_RCMR) Detection of a rising edge on RF signal */
    05008 #define   SSC_RCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_RCMR) Detection of any level change on RF signal */
    05009 #define   SSC_RCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_RCMR) Detection of any edge on RF signal */
    05010 #define   SSC_RCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_RCMR) Compare 0 */
    05011 #define SSC_RCMR_STOP (0x1u << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */
    05012 #define SSC_RCMR_STTDLY_Pos 16
    05013 #define SSC_RCMR_STTDLY_Msk (0xffu << SSC_RCMR_STTDLY_Pos) /**< \brief (SSC_RCMR) Receive Start Delay */
    05014 #define SSC_RCMR_STTDLY(value) ((SSC_RCMR_STTDLY_Msk & ((value) << SSC_RCMR_STTDLY_Pos)))
    05015 #define SSC_RCMR_PERIOD_Pos 24
    05016 #define SSC_RCMR_PERIOD_Msk (0xffu << SSC_RCMR_PERIOD_Pos) /**< \brief (SSC_RCMR) Receive Period Divider Selection */
    05017 #define SSC_RCMR_PERIOD(value) ((SSC_RCMR_PERIOD_Msk & ((value) << SSC_RCMR_PERIOD_Pos)))
    05018 /* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */
    05019 #define SSC_RFMR_DATLEN_Pos 0
    05020 #define SSC_RFMR_DATLEN_Msk (0x1fu << SSC_RFMR_DATLEN_Pos) /**< \brief (SSC_RFMR) Data Length */
    05021 #define SSC_RFMR_DATLEN(value) ((SSC_RFMR_DATLEN_Msk & ((value) << SSC_RFMR_DATLEN_Pos)))
    05022 #define SSC_RFMR_LOOP (0x1u << 5) /**< \brief (SSC_RFMR) Loop Mode */
    05023 #define SSC_RFMR_MSBF (0x1u << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */
    05024 #define SSC_RFMR_DATNB_Pos 8
    05025 #define SSC_RFMR_DATNB_Msk (0xfu << SSC_RFMR_DATNB_Pos) /**< \brief (SSC_RFMR) Data Number per Frame */
    05026 #define SSC_RFMR_DATNB(value) ((SSC_RFMR_DATNB_Msk & ((value) << SSC_RFMR_DATNB_Pos)))
    05027 #define SSC_RFMR_FSLEN_Pos 16
    05028 #define SSC_RFMR_FSLEN_Msk (0xfu << SSC_RFMR_FSLEN_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Length */
    05029 #define SSC_RFMR_FSLEN(value) ((SSC_RFMR_FSLEN_Msk & ((value) << SSC_RFMR_FSLEN_Pos)))
    05030 #define SSC_RFMR_FSOS_Pos 20
    05031 #define SSC_RFMR_FSOS_Msk (0x7u << SSC_RFMR_FSOS_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */
    05032 #define   SSC_RFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_RFMR) None */
    05033 #define   SSC_RFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_RFMR) Negative Pulse */
    05034 #define   SSC_RFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_RFMR) Positive Pulse */
    05035 #define   SSC_RFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_RFMR) Driven Low during data transfer */
    05036 #define   SSC_RFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_RFMR) Driven High during data transfer */
    05037 #define   SSC_RFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_RFMR) Toggling at each start of data transfer */
    05038 #define SSC_RFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */
    05039 #define   SSC_RFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_RFMR) Positive Edge Detection */
    05040 #define   SSC_RFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_RFMR) Negative Edge Detection */
    05041 #define SSC_RFMR_FSLEN_EXT_Pos 28
    05042 #define SSC_RFMR_FSLEN_EXT_Msk (0xfu << SSC_RFMR_FSLEN_EXT_Pos) /**< \brief (SSC_RFMR) FSLEN Field Extension */
    05043 #define SSC_RFMR_FSLEN_EXT(value) ((SSC_RFMR_FSLEN_EXT_Msk & ((value) << SSC_RFMR_FSLEN_EXT_Pos)))
    05044 /* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */
    05045 #define SSC_TCMR_CKS_Pos 0
    05046 #define SSC_TCMR_CKS_Msk (0x3u << SSC_TCMR_CKS_Pos) /**< \brief (SSC_TCMR) Transmit Clock Selection */
    05047 #define   SSC_TCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_TCMR) Divided Clock */
    05048 #define   SSC_TCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_TCMR) TK Clock signal */
    05049 #define   SSC_TCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_TCMR) RK pin */
    05050 #define SSC_TCMR_CKO_Pos 2
    05051 #define SSC_TCMR_CKO_Msk (0x7u << SSC_TCMR_CKO_Pos) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */
    05052 #define   SSC_TCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_TCMR) None */
    05053 #define   SSC_TCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_TCMR) Continuous Receive Clock */
    05054 #define   SSC_TCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_TCMR) Transmit Clock only during data transfers */
    05055 #define SSC_TCMR_CKI (0x1u << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */
    05056 #define SSC_TCMR_CKG_Pos 6
    05057 #define SSC_TCMR_CKG_Msk (0x3u << SSC_TCMR_CKG_Pos) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */
    05058 #define   SSC_TCMR_CKG_NONE (0x0u << 6) /**< \brief (SSC_TCMR) None */
    05059 #define   SSC_TCMR_CKG_CONTINUOUS (0x1u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF Low */
    05060 #define   SSC_TCMR_CKG_TRANSFER (0x2u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF High */
    05061 #define SSC_TCMR_START_Pos 8
    05062 #define SSC_TCMR_START_Msk (0xfu << SSC_TCMR_START_Pos) /**< \brief (SSC_TCMR) Transmit Start Selection */
    05063 #define   SSC_TCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_TCMR) Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data. */
    05064 #define   SSC_TCMR_START_RECEIVE (0x1u << 8) /**< \brief (SSC_TCMR) Receive start */
    05065 #define   SSC_TCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_TCMR) Detection of a low level on TF signal */
    05066 #define   SSC_TCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_TCMR) Detection of a high level on TF signal */
    05067 #define   SSC_TCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_TCMR) Detection of a falling edge on TF signal */
    05068 #define   SSC_TCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_TCMR) Detection of a rising edge on TF signal */
    05069 #define   SSC_TCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_TCMR) Detection of any level change on TF signal */
    05070 #define   SSC_TCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_TCMR) Detection of any edge on TF signal */
    05071 #define   SSC_TCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_TCMR) Compare 0 */
    05072 #define SSC_TCMR_STTDLY_Pos 16
    05073 #define SSC_TCMR_STTDLY_Msk (0xffu << SSC_TCMR_STTDLY_Pos) /**< \brief (SSC_TCMR) Transmit Start Delay */
    05074 #define SSC_TCMR_STTDLY(value) ((SSC_TCMR_STTDLY_Msk & ((value) << SSC_TCMR_STTDLY_Pos)))
    05075 #define SSC_TCMR_PERIOD_Pos 24
    05076 #define SSC_TCMR_PERIOD_Msk (0xffu << SSC_TCMR_PERIOD_Pos) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */
    05077 #define SSC_TCMR_PERIOD(value) ((SSC_TCMR_PERIOD_Msk & ((value) << SSC_TCMR_PERIOD_Pos)))
    05078 /* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */
    05079 #define SSC_TFMR_DATLEN_Pos 0
    05080 #define SSC_TFMR_DATLEN_Msk (0x1fu << SSC_TFMR_DATLEN_Pos) /**< \brief (SSC_TFMR) Data Length */
    05081 #define SSC_TFMR_DATLEN(value) ((SSC_TFMR_DATLEN_Msk & ((value) << SSC_TFMR_DATLEN_Pos)))
    05082 #define SSC_TFMR_DATDEF (0x1u << 5) /**< \brief (SSC_TFMR) Data Default Value */
    05083 #define SSC_TFMR_MSBF (0x1u << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */
    05084 #define SSC_TFMR_DATNB_Pos 8
    05085 #define SSC_TFMR_DATNB_Msk (0xfu << SSC_TFMR_DATNB_Pos) /**< \brief (SSC_TFMR) Data Number per frame */
    05086 #define SSC_TFMR_DATNB(value) ((SSC_TFMR_DATNB_Msk & ((value) << SSC_TFMR_DATNB_Pos)))
    05087 #define SSC_TFMR_FSLEN_Pos 16
    05088 #define SSC_TFMR_FSLEN_Msk (0xfu << SSC_TFMR_FSLEN_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Length */
    05089 #define SSC_TFMR_FSLEN(value) ((SSC_TFMR_FSLEN_Msk & ((value) << SSC_TFMR_FSLEN_Pos)))
    05090 #define SSC_TFMR_FSOS_Pos 20
    05091 #define SSC_TFMR_FSOS_Msk (0x7u << SSC_TFMR_FSOS_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */
    05092 #define   SSC_TFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_TFMR) None */
    05093 #define   SSC_TFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_TFMR) Negative Pulse */
    05094 #define   SSC_TFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_TFMR) Positive Pulse */
    05095 #define   SSC_TFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_TFMR) Driven Low during data transfer */
    05096 #define   SSC_TFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_TFMR) Driven High during data transfer */
    05097 #define   SSC_TFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_TFMR) Toggling at each start of data transfer */
    05098 #define SSC_TFMR_FSDEN (0x1u << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */
    05099 #define SSC_TFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */
    05100 #define   SSC_TFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_TFMR) Positive Edge Detection */
    05101 #define   SSC_TFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_TFMR) Negative Edge Detection */
    05102 #define SSC_TFMR_FSLEN_EXT_Pos 28
    05103 #define SSC_TFMR_FSLEN_EXT_Msk (0xfu << SSC_TFMR_FSLEN_EXT_Pos) /**< \brief (SSC_TFMR) FSLEN Field Extension */
    05104 #define SSC_TFMR_FSLEN_EXT(value) ((SSC_TFMR_FSLEN_EXT_Msk & ((value) << SSC_TFMR_FSLEN_EXT_Pos)))
    05105 /* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */
    05106 #define SSC_RHR_RDAT_Pos 0
    05107 #define SSC_RHR_RDAT_Msk (0xffffffffu << SSC_RHR_RDAT_Pos) /**< \brief (SSC_RHR) Receive Data */
    05108 /* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */
    05109 #define SSC_THR_TDAT_Pos 0
    05110 #define SSC_THR_TDAT_Msk (0xffffffffu << SSC_THR_TDAT_Pos) /**< \brief (SSC_THR) Transmit Data */
    05111 #define SSC_THR_TDAT(value) ((SSC_THR_TDAT_Msk & ((value) << SSC_THR_TDAT_Pos)))
    05112 /* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */
    05113 #define SSC_RSHR_RSDAT_Pos 0
    05114 #define SSC_RSHR_RSDAT_Msk (0xffffu << SSC_RSHR_RSDAT_Pos) /**< \brief (SSC_RSHR) Receive Synchronization Data */
    05115 /* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */
    05116 #define SSC_TSHR_TSDAT_Pos 0
    05117 #define SSC_TSHR_TSDAT_Msk (0xffffu << SSC_TSHR_TSDAT_Pos) /**< \brief (SSC_TSHR) Transmit Synchronization Data */
    05118 #define SSC_TSHR_TSDAT(value) ((SSC_TSHR_TSDAT_Msk & ((value) << SSC_TSHR_TSDAT_Pos)))
    05119 /* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */
    05120 #define SSC_RC0R_CP0_Pos 0
    05121 #define SSC_RC0R_CP0_Msk (0xffffu << SSC_RC0R_CP0_Pos) /**< \brief (SSC_RC0R) Receive Compare Data 0 */
    05122 #define SSC_RC0R_CP0(value) ((SSC_RC0R_CP0_Msk & ((value) << SSC_RC0R_CP0_Pos)))
    05123 /* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */
    05124 #define SSC_RC1R_CP1_Pos 0
    05125 #define SSC_RC1R_CP1_Msk (0xffffu << SSC_RC1R_CP1_Pos) /**< \brief (SSC_RC1R) Receive Compare Data 1 */
    05126 #define SSC_RC1R_CP1(value) ((SSC_RC1R_CP1_Msk & ((value) << SSC_RC1R_CP1_Pos)))
    05127 /* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */
    05128 #define SSC_SR_TXRDY (0x1u << 0) /**< \brief (SSC_SR) Transmit Ready */
    05129 #define SSC_SR_TXEMPTY (0x1u << 1) /**< \brief (SSC_SR) Transmit Empty */
    05130 #define SSC_SR_ENDTX (0x1u << 2) /**< \brief (SSC_SR) End of Transmission */
    05131 #define SSC_SR_TXBUFE (0x1u << 3) /**< \brief (SSC_SR) Transmit Buffer Empty */
    05132 #define SSC_SR_RXRDY (0x1u << 4) /**< \brief (SSC_SR) Receive Ready */
    05133 #define SSC_SR_OVRUN (0x1u << 5) /**< \brief (SSC_SR) Receive Overrun */
    05134 #define SSC_SR_ENDRX (0x1u << 6) /**< \brief (SSC_SR) End of Reception */
    05135 #define SSC_SR_RXBUFF (0x1u << 7) /**< \brief (SSC_SR) Receive Buffer Full */
    05136 #define SSC_SR_CP0 (0x1u << 8) /**< \brief (SSC_SR) Compare 0 */
    05137 #define SSC_SR_CP1 (0x1u << 9) /**< \brief (SSC_SR) Compare 1 */
    05138 #define SSC_SR_TXSYN (0x1u << 10) /**< \brief (SSC_SR) Transmit Sync */
    05139 #define SSC_SR_RXSYN (0x1u << 11) /**< \brief (SSC_SR) Receive Sync */
    05140 #define SSC_SR_TXEN (0x1u << 16) /**< \brief (SSC_SR) Transmit Enable */
    05141 #define SSC_SR_RXEN (0x1u << 17) /**< \brief (SSC_SR) Receive Enable */
    05142 /* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */
    05143 #define SSC_IER_TXRDY (0x1u << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */
    05144 #define SSC_IER_TXEMPTY (0x1u << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */
    05145 #define SSC_IER_ENDTX (0x1u << 2) /**< \brief (SSC_IER) End of Transmission Interrupt Enable */
    05146 #define SSC_IER_TXBUFE (0x1u << 3) /**< \brief (SSC_IER) Transmit Buffer Empty Interrupt Enable */
    05147 #define SSC_IER_RXRDY (0x1u << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */
    05148 #define SSC_IER_OVRUN (0x1u << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */
    05149 #define SSC_IER_ENDRX (0x1u << 6) /**< \brief (SSC_IER) End of Reception Interrupt Enable */
    05150 #define SSC_IER_RXBUFF (0x1u << 7) /**< \brief (SSC_IER) Receive Buffer Full Interrupt Enable */
    05151 #define SSC_IER_CP0 (0x1u << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */
    05152 #define SSC_IER_CP1 (0x1u << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */
    05153 #define SSC_IER_TXSYN (0x1u << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */
    05154 #define SSC_IER_RXSYN (0x1u << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */
    05155 /* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */
    05156 #define SSC_IDR_TXRDY (0x1u << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */
    05157 #define SSC_IDR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */
    05158 #define SSC_IDR_ENDTX (0x1u << 2) /**< \brief (SSC_IDR) End of Transmission Interrupt Disable */
    05159 #define SSC_IDR_TXBUFE (0x1u << 3) /**< \brief (SSC_IDR) Transmit Buffer Empty Interrupt Disable */
    05160 #define SSC_IDR_RXRDY (0x1u << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */
    05161 #define SSC_IDR_OVRUN (0x1u << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */
    05162 #define SSC_IDR_ENDRX (0x1u << 6) /**< \brief (SSC_IDR) End of Reception Interrupt Disable */
    05163 #define SSC_IDR_RXBUFF (0x1u << 7) /**< \brief (SSC_IDR) Receive Buffer Full Interrupt Disable */
    05164 #define SSC_IDR_CP0 (0x1u << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */
    05165 #define SSC_IDR_CP1 (0x1u << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */
    05166 #define SSC_IDR_TXSYN (0x1u << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */
    05167 #define SSC_IDR_RXSYN (0x1u << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */
    05168 /* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */
    05169 #define SSC_IMR_TXRDY (0x1u << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */
    05170 #define SSC_IMR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */
    05171 #define SSC_IMR_ENDTX (0x1u << 2) /**< \brief (SSC_IMR) End of Transmission Interrupt Mask */
    05172 #define SSC_IMR_TXBUFE (0x1u << 3) /**< \brief (SSC_IMR) Transmit Buffer Empty Interrupt Mask */
    05173 #define SSC_IMR_RXRDY (0x1u << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */
    05174 #define SSC_IMR_OVRUN (0x1u << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */
    05175 #define SSC_IMR_ENDRX (0x1u << 6) /**< \brief (SSC_IMR) End of Reception Interrupt Mask */
    05176 #define SSC_IMR_RXBUFF (0x1u << 7) /**< \brief (SSC_IMR) Receive Buffer Full Interrupt Mask */
    05177 #define SSC_IMR_CP0 (0x1u << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */
    05178 #define SSC_IMR_CP1 (0x1u << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */
    05179 #define SSC_IMR_TXSYN (0x1u << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */
    05180 #define SSC_IMR_RXSYN (0x1u << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */
    05181 /* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protect Mode Register -------- */
    05182 #define SSC_WPMR_WPEN (0x1u << 0) /**< \brief (SSC_WPMR) Write Protect Enable */
    05183 #define SSC_WPMR_WPKEY_Pos 8
    05184 #define SSC_WPMR_WPKEY_Msk (0xffffffu << SSC_WPMR_WPKEY_Pos) /**< \brief (SSC_WPMR) Write Protect KEY */
    05185 #define SSC_WPMR_WPKEY(value) ((SSC_WPMR_WPKEY_Msk & ((value) << SSC_WPMR_WPKEY_Pos)))
    05186 /* -------- SSC_WPSR : (SSC Offset: 0xE8) Write Protect Status Register -------- */
    05187 #define SSC_WPSR_WPVS (0x1u << 0) /**< \brief (SSC_WPSR) Write Protect Violation Status */
    05188 #define SSC_WPSR_WPVSRC_Pos 8
    05189 #define SSC_WPSR_WPVSRC_Msk (0xffffu << SSC_WPSR_WPVSRC_Pos) /**< \brief (SSC_WPSR) Write Protect Violation Source */
    05190 /* -------- SSC_RPR : (SSC Offset: 0x100) Receive Pointer Register -------- */
    05191 #define SSC_RPR_RXPTR_Pos 0
    05192 #define SSC_RPR_RXPTR_Msk (0xffffffffu << SSC_RPR_RXPTR_Pos) /**< \brief (SSC_RPR) Receive Pointer Register */
    05193 #define SSC_RPR_RXPTR(value) ((SSC_RPR_RXPTR_Msk & ((value) << SSC_RPR_RXPTR_Pos)))
    05194 /* -------- SSC_RCR : (SSC Offset: 0x104) Receive Counter Register -------- */
    05195 #define SSC_RCR_RXCTR_Pos 0
    05196 #define SSC_RCR_RXCTR_Msk (0xffffu << SSC_RCR_RXCTR_Pos) /**< \brief (SSC_RCR) Receive Counter Register */
    05197 #define SSC_RCR_RXCTR(value) ((SSC_RCR_RXCTR_Msk & ((value) << SSC_RCR_RXCTR_Pos)))
    05198 /* -------- SSC_TPR : (SSC Offset: 0x108) Transmit Pointer Register -------- */
    05199 #define SSC_TPR_TXPTR_Pos 0
    05200 #define SSC_TPR_TXPTR_Msk (0xffffffffu << SSC_TPR_TXPTR_Pos) /**< \brief (SSC_TPR) Transmit Counter Register */
    05201 #define SSC_TPR_TXPTR(value) ((SSC_TPR_TXPTR_Msk & ((value) << SSC_TPR_TXPTR_Pos)))
    05202 /* -------- SSC_TCR : (SSC Offset: 0x10C) Transmit Counter Register -------- */
    05203 #define SSC_TCR_TXCTR_Pos 0
    05204 #define SSC_TCR_TXCTR_Msk (0xffffu << SSC_TCR_TXCTR_Pos) /**< \brief (SSC_TCR) Transmit Counter Register */
    05205 #define SSC_TCR_TXCTR(value) ((SSC_TCR_TXCTR_Msk & ((value) << SSC_TCR_TXCTR_Pos)))
    05206 /* -------- SSC_RNPR : (SSC Offset: 0x110) Receive Next Pointer Register -------- */
    05207 #define SSC_RNPR_RXNPTR_Pos 0
    05208 #define SSC_RNPR_RXNPTR_Msk (0xffffffffu << SSC_RNPR_RXNPTR_Pos) /**< \brief (SSC_RNPR) Receive Next Pointer */
    05209 #define SSC_RNPR_RXNPTR(value) ((SSC_RNPR_RXNPTR_Msk & ((value) << SSC_RNPR_RXNPTR_Pos)))
    05210 /* -------- SSC_RNCR : (SSC Offset: 0x114) Receive Next Counter Register -------- */
    05211 #define SSC_RNCR_RXNCTR_Pos 0
    05212 #define SSC_RNCR_RXNCTR_Msk (0xffffu << SSC_RNCR_RXNCTR_Pos) /**< \brief (SSC_RNCR) Receive Next Counter */
    05213 #define SSC_RNCR_RXNCTR(value) ((SSC_RNCR_RXNCTR_Msk & ((value) << SSC_RNCR_RXNCTR_Pos)))
    05214 /* -------- SSC_TNPR : (SSC Offset: 0x118) Transmit Next Pointer Register -------- */
    05215 #define SSC_TNPR_TXNPTR_Pos 0
    05216 #define SSC_TNPR_TXNPTR_Msk (0xffffffffu << SSC_TNPR_TXNPTR_Pos) /**< \brief (SSC_TNPR) Transmit Next Pointer */
    05217 #define SSC_TNPR_TXNPTR(value) ((SSC_TNPR_TXNPTR_Msk & ((value) << SSC_TNPR_TXNPTR_Pos)))
    05218 /* -------- SSC_TNCR : (SSC Offset: 0x11C) Transmit Next Counter Register -------- */
    05219 #define SSC_TNCR_TXNCTR_Pos 0
    05220 #define SSC_TNCR_TXNCTR_Msk (0xffffu << SSC_TNCR_TXNCTR_Pos) /**< \brief (SSC_TNCR) Transmit Counter Next */
    05221 #define SSC_TNCR_TXNCTR(value) ((SSC_TNCR_TXNCTR_Msk & ((value) << SSC_TNCR_TXNCTR_Pos)))
    05222 /* -------- SSC_PTCR : (SSC Offset: 0x120) Transfer Control Register -------- */
    05223 #define SSC_PTCR_RXTEN (0x1u << 0) /**< \brief (SSC_PTCR) Receiver Transfer Enable */
    05224 #define SSC_PTCR_RXTDIS (0x1u << 1) /**< \brief (SSC_PTCR) Receiver Transfer Disable */
    05225 #define SSC_PTCR_TXTEN (0x1u << 8) /**< \brief (SSC_PTCR) Transmitter Transfer Enable */
    05226 #define SSC_PTCR_TXTDIS (0x1u << 9) /**< \brief (SSC_PTCR) Transmitter Transfer Disable */
    05227 /* -------- SSC_PTSR : (SSC Offset: 0x124) Transfer Status Register -------- */
    05228 #define SSC_PTSR_RXTEN (0x1u << 0) /**< \brief (SSC_PTSR) Receiver Transfer Enable */
    05229 #define SSC_PTSR_TXTEN (0x1u << 8) /**< \brief (SSC_PTSR) Transmitter Transfer Enable */
    05230
    05231 /*@}*/
    05232
    05233 /* ============================================================================= */
    05234 /**  SOFTWARE API DEFINITION FOR Supply Controller */
    05235 /* ============================================================================= */
    05236 /** \addtogroup SAM3S8_SUPC Supply Controller */
    05237 /*@{*/
    05238
    05239 #ifndef __ASSEMBLY__
    05240 /** \brief Supc hardware registers */
    05241 typedef struct {
    05242   WoReg SUPC_CR;   /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */
    05243   RwReg SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */
    05244   RwReg SUPC_MR;   /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */
    05245   RwReg SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake Up Mode Register */
    05246   RwReg SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake Up Inputs Register */
    05247   RoReg SUPC_SR;   /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */
    05248 } Supc;
    05249 #endif /* __ASSEMBLY__ */
    05250 /* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */
    05251 #define SUPC_CR_VROFF (0x1u << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */
    05252 #define   SUPC_CR_VROFF_NO_EFFECT (0x0u << 2) /**< \brief (SUPC_CR) no effect. */
    05253 #define   SUPC_CR_VROFF_STOP_VREG (0x1u << 2) /**< \brief (SUPC_CR) if KEY is correct, asserts vddcore_nreset and stops the voltage regulator. */
    05254 #define SUPC_CR_XTALSEL (0x1u << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */
    05255 #define   SUPC_CR_XTALSEL_NO_EFFECT (0x0u << 3) /**< \brief (SUPC_CR) no effect. */
    05256 #define   SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1u << 3) /**< \brief (SUPC_CR) if KEY is correct, switches the slow clock on the crystal oscillator output. */
    05257 #define SUPC_CR_KEY_Pos 24
    05258 #define SUPC_CR_KEY_Msk (0xffu << SUPC_CR_KEY_Pos) /**< \brief (SUPC_CR) Password */
    05259 #define SUPC_CR_KEY(value) ((SUPC_CR_KEY_Msk & ((value) << SUPC_CR_KEY_Pos)))
    05260 /* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */
    05261 #define SUPC_SMMR_SMTH_Pos 0
    05262 #define SUPC_SMMR_SMTH_Msk (0xfu << SUPC_SMMR_SMTH_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */
    05263 #define   SUPC_SMMR_SMTH_1_9V (0x0u << 0) /**< \brief (SUPC_SMMR) 1.9 V */
    05264 #define   SUPC_SMMR_SMTH_2_0V (0x1u << 0) /**< \brief (SUPC_SMMR) 2.0 V */
    05265 #define   SUPC_SMMR_SMTH_2_1V (0x2u << 0) /**< \brief (SUPC_SMMR) 2.1 V */
    05266 #define   SUPC_SMMR_SMTH_2_2V (0x3u << 0) /**< \brief (SUPC_SMMR) 2.2 V */
    05267 #define   SUPC_SMMR_SMTH_2_3V (0x4u << 0) /**< \brief (SUPC_SMMR) 2.3 V */
    05268 #define   SUPC_SMMR_SMTH_2_4V (0x5u << 0) /**< \brief (SUPC_SMMR) 2.4 V */
    05269 #define   SUPC_SMMR_SMTH_2_5V (0x6u << 0) /**< \brief (SUPC_SMMR) 2.5 V */
    05270 #define   SUPC_SMMR_SMTH_2_6V (0x7u << 0) /**< \brief (SUPC_SMMR) 2.6 V */
    05271 #define   SUPC_SMMR_SMTH_2_7V (0x8u << 0) /**< \brief (SUPC_SMMR) 2.7 V */
    05272 #define   SUPC_SMMR_SMTH_2_8V (0x9u << 0) /**< \brief (SUPC_SMMR) 2.8 V */
    05273 #define   SUPC_SMMR_SMTH_2_9V (0xAu << 0) /**< \brief (SUPC_SMMR) 2.9 V */
    05274 #define   SUPC_SMMR_SMTH_3_0V (0xBu << 0) /**< \brief (SUPC_SMMR) 3.0 V */
    05275 #define   SUPC_SMMR_SMTH_3_1V (0xCu << 0) /**< \brief (SUPC_SMMR) 3.1 V */
    05276 #define   SUPC_SMMR_SMTH_3_2V (0xDu << 0) /**< \brief (SUPC_SMMR) 3.2 V */
    05277 #define   SUPC_SMMR_SMTH_3_3V (0xEu << 0) /**< \brief (SUPC_SMMR) 3.3 V */
    05278 #define   SUPC_SMMR_SMTH_3_4V (0xFu << 0) /**< \brief (SUPC_SMMR) 3.4 V */
    05279 #define SUPC_SMMR_SMSMPL_Pos 8
    05280 #define SUPC_SMMR_SMSMPL_Msk (0x7u << SUPC_SMMR_SMSMPL_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */
    05281 #define   SUPC_SMMR_SMSMPL_SMD (0x0u << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */
    05282 #define   SUPC_SMMR_SMSMPL_CSM (0x1u << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */
    05283 #define   SUPC_SMMR_SMSMPL_32SLCK (0x2u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */
    05284 #define   SUPC_SMMR_SMSMPL_256SLCK (0x3u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */
    05285 #define   SUPC_SMMR_SMSMPL_2048SLCK (0x4u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */
    05286 #define SUPC_SMMR_SMRSTEN (0x1u << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */
    05287 #define   SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_SMMR) the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. */
    05288 #define   SUPC_SMMR_SMRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_SMMR) the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */
    05289 #define SUPC_SMMR_SMIEN (0x1u << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */
    05290 #define   SUPC_SMMR_SMIEN_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is not affected when a supply monitor detection occurs. */
    05291 #define   SUPC_SMMR_SMIEN_ENABLE (0x1u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is asserted when a supply monitor detection occurs. */
    05292 /* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */
    05293 #define SUPC_MR_BODRSTEN (0x1u << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */
    05294 #define   SUPC_MR_BODRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_MR) the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. */
    05295 #define   SUPC_MR_BODRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_MR) the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */
    05296 #define SUPC_MR_BODDIS (0x1u << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */
    05297 #define   SUPC_MR_BODDIS_ENABLE (0x0u << 13) /**< \brief (SUPC_MR) the core brownout detector is enabled. */
    05298 #define   SUPC_MR_BODDIS_DISABLE (0x1u << 13) /**< \brief (SUPC_MR) the core brownout detector is disabled. */
    05299 #define SUPC_MR_ONREG (0x1u << 14) /**< \brief (SUPC_MR) Voltage Regulator enable */
    05300 #define   SUPC_MR_ONREG_ONREG_UNUSED (0x0u << 14) /**< \brief (SUPC_MR) Voltage Regulator is not used */
    05301 #define   SUPC_MR_ONREG_ONREG_USED (0x1u << 14) /**< \brief (SUPC_MR) Voltage Regulator is used */
    05302 #define SUPC_MR_OSCBYPASS (0x1u << 20) /**< \brief (SUPC_MR) Oscillator Bypass */
    05303 #define   SUPC_MR_OSCBYPASS_NO_EFFECT (0x0u << 20) /**< \brief (SUPC_MR) no effect. Clock selection depends on XTALSEL value. */
    05304 #define   SUPC_MR_OSCBYPASS_BYPASS (0x1u << 20) /**< \brief (SUPC_MR) the 32-KHz XTAL oscillator is selected and is put in bypass mode. */
    05305 #define SUPC_MR_KEY_Pos 24
    05306 #define SUPC_MR_KEY_Msk (0xffu << SUPC_MR_KEY_Pos) /**< \brief (SUPC_MR) Password Key */
    05307 #define SUPC_MR_KEY(value) ((SUPC_MR_KEY_Msk & ((value) << SUPC_MR_KEY_Pos)))
    05308 /* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake Up Mode Register -------- */
    05309 #define SUPC_WUMR_SMEN (0x1u << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake Up Enable */
    05310 #define   SUPC_WUMR_SMEN_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection has no wake up effect. */
    05311 #define   SUPC_WUMR_SMEN_ENABLE (0x1u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection forces the wake up of the core power supply. */
    05312 #define SUPC_WUMR_RTTEN (0x1u << 2) /**< \brief (SUPC_WUMR) Real Time Timer Wake Up Enable */
    05313 #define   SUPC_WUMR_RTTEN_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal has no wake up effect. */
    05314 #define   SUPC_WUMR_RTTEN_ENABLE (0x1u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal forces the wake up of the core power supply. */
    05315 #define SUPC_WUMR_RTCEN (0x1u << 3) /**< \brief (SUPC_WUMR) Real Time Clock Wake Up Enable */
    05316 #define   SUPC_WUMR_RTCEN_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal has no wake up effect. */
    05317 #define   SUPC_WUMR_RTCEN_ENABLE (0x1u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal forces the wake up of the core power supply. */
    05318 #define SUPC_WUMR_LPDBCEN0 (0x1u << 5) /**< \brief (SUPC_WUMR) Low power Debouncer ENable WKUP0 */
    05319 #define   SUPC_WUMR_LPDBCEN0_NOT_ENABLE (0x0u << 5) /**< \brief (SUPC_WUMR) the WKUP0 input pin is not connected with low power debouncer. */
    05320 #define   SUPC_WUMR_LPDBCEN0_ENABLE (0x1u << 5) /**< \brief (SUPC_WUMR) the WKUP0 input pin is connected with low power debouncer and can force the a core wake up. */
    05321 #define SUPC_WUMR_LPDBCEN1 (0x1u << 6) /**< \brief (SUPC_WUMR) Low power Debouncer ENable WKUP1 */
    05322 #define   SUPC_WUMR_LPDBCEN1_NOT_ENABLE (0x0u << 6) /**< \brief (SUPC_WUMR) the WKUP1input pin is not connected with low power debouncer. */
    05323 #define   SUPC_WUMR_LPDBCEN1_ENABLE (0x1u << 6) /**< \brief (SUPC_WUMR) the WKUP1 input pin is connected with low power debouncer and can force the a core wake up. */
    05324 #define SUPC_WUMR_LPDBCCLR (0x1u << 7) /**< \brief (SUPC_WUMR) Low power Debouncer Clear */
    05325 #define   SUPC_WUMR_LPDBCCLR_NOT_ENABLE (0x0u << 7) /**< \brief (SUPC_WUMR) a low power debounce event does not create an immediate clear on half GPBR registers. */
    05326 #define   SUPC_WUMR_LPDBCCLR_ENABLE (0x1u << 7) /**< \brief (SUPC_WUMR) a low power debounce event on WKUP0 or WKUP1 generates an immediate clear on half GPBR registers. */
    05327 #define SUPC_WUMR_WKUPDBC_Pos 12
    05328 #define SUPC_WUMR_WKUPDBC_Msk (0x7u << SUPC_WUMR_WKUPDBC_Pos) /**< \brief (SUPC_WUMR) Wake Up Inputs Debouncer Period */
    05329 #define   SUPC_WUMR_WKUPDBC_IMMEDIATE (0x0u << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */
    05330 #define   SUPC_WUMR_WKUPDBC_3_SCLK (0x1u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 3 SLCK periods */
    05331 #define   SUPC_WUMR_WKUPDBC_32_SCLK (0x2u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32 SLCK periods */
    05332 #define   SUPC_WUMR_WKUPDBC_512_SCLK (0x3u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 512 SLCK periods */
    05333 #define   SUPC_WUMR_WKUPDBC_4096_SCLK (0x4u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 4,096 SLCK periods */
    05334 #define   SUPC_WUMR_WKUPDBC_32768_SCLK (0x5u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32,768 SLCK periods */
    05335 #define SUPC_WUMR_LPDBC_Pos 16
    05336 #define SUPC_WUMR_LPDBC_Msk (0x7u << SUPC_WUMR_LPDBC_Pos) /**< \brief (SUPC_WUMR) Low Power DeBounCer Period */
    05337 #define   SUPC_WUMR_LPDBC_DISABLE (0x0u << 16) /**< \brief (SUPC_WUMR) Disable the low power debouncer. */
    05338 #define   SUPC_WUMR_LPDBC_2_RTCOUT0 (0x1u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 2 RTCOUT0 periods */
    05339 #define   SUPC_WUMR_LPDBC_3_RTCOUT0 (0x2u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 3 RTCOUT0 periods */
    05340 #define   SUPC_WUMR_LPDBC_4_RTCOUT0 (0x3u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 4 RTCOUT0 periods */
    05341 #define   SUPC_WUMR_LPDBC_5_RTCOUT0 (0x4u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 5 RTCOUT0 periods */
    05342 #define   SUPC_WUMR_LPDBC_6_RTCOUT0 (0x5u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 6 RTCOUT0 periods */
    05343 #define   SUPC_WUMR_LPDBC_7_RTCOUT0 (0x6u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 7 RTCOUT0 periods */
    05344 #define   SUPC_WUMR_LPDBC_8_RTCOUT0 (0x7u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 8 RTCOUT0 periods */
    05345 /* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake Up Inputs Register -------- */
    05346 #define SUPC_WUIR_WKUPEN0 (0x1u << 0) /**< \brief (SUPC_WUIR) Wake Up Input Enable 0 */
    05347 #define   SUPC_WUIR_WKUPEN0_NOT_ENABLE (0x0u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
    05348 #define   SUPC_WUIR_WKUPEN0_ENABLE (0x1u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
    05349 #define SUPC_WUIR_WKUPEN1 (0x1u << 1) /**< \brief (SUPC_WUIR) Wake Up Input Enable 1 */
    05350 #define   SUPC_WUIR_WKUPEN1_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
    05351 #define   SUPC_WUIR_WKUPEN1_ENABLE (0x1u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
    05352 #define SUPC_WUIR_WKUPEN2 (0x1u << 2) /**< \brief (SUPC_WUIR) Wake Up Input Enable 2 */
    05353 #define   SUPC_WUIR_WKUPEN2_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
    05354 #define   SUPC_WUIR_WKUPEN2_ENABLE (0x1u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
    05355 #define SUPC_WUIR_WKUPEN3 (0x1u << 3) /**< \brief (SUPC_WUIR) Wake Up Input Enable 3 */
    05356 #define   SUPC_WUIR_WKUPEN3_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
    05357 #define   SUPC_WUIR_WKUPEN3_ENABLE (0x1u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
    05358 #define SUPC_WUIR_WKUPEN4 (0x1u << 4) /**< \brief (SUPC_WUIR) Wake Up Input Enable 4 */
    05359 #define   SUPC_WUIR_WKUPEN4_NOT_ENABLE (0x0u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
    05360 #define   SUPC_WUIR_WKUPEN4_ENABLE (0x1u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
    05361 #define SUPC_WUIR_WKUPEN5 (0x1u << 5) /**< \brief (SUPC_WUIR) Wake Up Input Enable 5 */
    05362 #define   SUPC_WUIR_WKUPEN5_NOT_ENABLE (0x0u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
    05363 #define   SUPC_WUIR_WKUPEN5_ENABLE (0x1u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
    05364 #define SUPC_WUIR_WKUPEN6 (0x1u << 6) /**< \brief (SUPC_WUIR) Wake Up Input Enable 6 */
    05365 #define   SUPC_WUIR_WKUPEN6_NOT_ENABLE (0x0u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
    05366 #define   SUPC_WUIR_WKUPEN6_ENABLE (0x1u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
    05367 #define SUPC_WUIR_WKUPEN7 (0x1u << 7) /**< \brief (SUPC_WUIR) Wake Up Input Enable 7 */
    05368 #define   SUPC_WUIR_WKUPEN7_NOT_ENABLE (0x0u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
    05369 #define   SUPC_WUIR_WKUPEN7_ENABLE (0x1u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
    05370 #define SUPC_WUIR_WKUPEN8 (0x1u << 8) /**< \brief (SUPC_WUIR) Wake Up Input Enable 8 */
    05371 #define   SUPC_WUIR_WKUPEN8_NOT_ENABLE (0x0u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
    05372 #define   SUPC_WUIR_WKUPEN8_ENABLE (0x1u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
    05373 #define SUPC_WUIR_WKUPEN9 (0x1u << 9) /**< \brief (SUPC_WUIR) Wake Up Input Enable 9 */
    05374 #define   SUPC_WUIR_WKUPEN9_NOT_ENABLE (0x0u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
    05375 #define   SUPC_WUIR_WKUPEN9_ENABLE (0x1u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
    05376 #define SUPC_WUIR_WKUPEN10 (0x1u << 10) /**< \brief (SUPC_WUIR) Wake Up Input Enable 10 */
    05377 #define   SUPC_WUIR_WKUPEN10_NOT_ENABLE (0x0u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
    05378 #define   SUPC_WUIR_WKUPEN10_ENABLE (0x1u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
    05379 #define SUPC_WUIR_WKUPEN11 (0x1u << 11) /**< \brief (SUPC_WUIR) Wake Up Input Enable 11 */
    05380 #define   SUPC_WUIR_WKUPEN11_NOT_ENABLE (0x0u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
    05381 #define   SUPC_WUIR_WKUPEN11_ENABLE (0x1u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
    05382 #define SUPC_WUIR_WKUPEN12 (0x1u << 12) /**< \brief (SUPC_WUIR) Wake Up Input Enable 12 */
    05383 #define   SUPC_WUIR_WKUPEN12_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
    05384 #define   SUPC_WUIR_WKUPEN12_ENABLE (0x1u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
    05385 #define SUPC_WUIR_WKUPEN13 (0x1u << 13) /**< \brief (SUPC_WUIR) Wake Up Input Enable 13 */
    05386 #define   SUPC_WUIR_WKUPEN13_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
    05387 #define   SUPC_WUIR_WKUPEN13_ENABLE (0x1u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
    05388 #define SUPC_WUIR_WKUPEN14 (0x1u << 14) /**< \brief (SUPC_WUIR) Wake Up Input Enable 14 */
    05389 #define   SUPC_WUIR_WKUPEN14_NOT_ENABLE (0x0u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
    05390 #define   SUPC_WUIR_WKUPEN14_ENABLE (0x1u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
    05391 #define SUPC_WUIR_WKUPEN15 (0x1u << 15) /**< \brief (SUPC_WUIR) Wake Up Input Enable 15 */
    05392 #define   SUPC_WUIR_WKUPEN15_NOT_ENABLE (0x0u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
    05393 #define   SUPC_WUIR_WKUPEN15_ENABLE (0x1u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
    05394 #define SUPC_WUIR_WKUPT0 (0x1u << 16) /**< \brief (SUPC_WUIR) Wake Up Input Transition 0 */
    05395 #define   SUPC_WUIR_WKUPT0_HIGH_TO_LOW (0x0u << 16) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
    05396 #define   SUPC_WUIR_WKUPT0_LOW_TO_HIGH (0x1u << 16) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
    05397 #define SUPC_WUIR_WKUPT1 (0x1u << 17) /**< \brief (SUPC_WUIR) Wake Up Input Transition 1 */
    05398 #define   SUPC_WUIR_WKUPT1_HIGH_TO_LOW (0x0u << 17) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
    05399 #define   SUPC_WUIR_WKUPT1_LOW_TO_HIGH (0x1u << 17) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
    05400 #define SUPC_WUIR_WKUPT2 (0x1u << 18) /**< \brief (SUPC_WUIR) Wake Up Input Transition 2 */
    05401 #define   SUPC_WUIR_WKUPT2_HIGH_TO_LOW (0x0u << 18) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
    05402 #define   SUPC_WUIR_WKUPT2_LOW_TO_HIGH (0x1u << 18) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
    05403 #define SUPC_WUIR_WKUPT3 (0x1u << 19) /**< \brief (SUPC_WUIR) Wake Up Input Transition 3 */
    05404 #define   SUPC_WUIR_WKUPT3_HIGH_TO_LOW (0x0u << 19) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
    05405 #define   SUPC_WUIR_WKUPT3_LOW_TO_HIGH (0x1u << 19) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
    05406 #define SUPC_WUIR_WKUPT4 (0x1u << 20) /**< \brief (SUPC_WUIR) Wake Up Input Transition 4 */
    05407 #define   SUPC_WUIR_WKUPT4_HIGH_TO_LOW (0x0u << 20) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
    05408 #define   SUPC_WUIR_WKUPT4_LOW_TO_HIGH (0x1u << 20) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
    05409 #define SUPC_WUIR_WKUPT5 (0x1u << 21) /**< \brief (SUPC_WUIR) Wake Up Input Transition 5 */
    05410 #define   SUPC_WUIR_WKUPT5_HIGH_TO_LOW (0x0u << 21) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
    05411 #define   SUPC_WUIR_WKUPT5_LOW_TO_HIGH (0x1u << 21) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
    05412 #define SUPC_WUIR_WKUPT6 (0x1u << 22) /**< \brief (SUPC_WUIR) Wake Up Input Transition 6 */
    05413 #define   SUPC_WUIR_WKUPT6_HIGH_TO_LOW (0x0u << 22) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
    05414 #define   SUPC_WUIR_WKUPT6_LOW_TO_HIGH (0x1u << 22) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
    05415 #define SUPC_WUIR_WKUPT7 (0x1u << 23) /**< \brief (SUPC_WUIR) Wake Up Input Transition 7 */
    05416 #define   SUPC_WUIR_WKUPT7_HIGH_TO_LOW (0x0u << 23) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
    05417 #define   SUPC_WUIR_WKUPT7_LOW_TO_HIGH (0x1u << 23) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
    05418 #define SUPC_WUIR_WKUPT8 (0x1u << 24) /**< \brief (SUPC_WUIR) Wake Up Input Transition 8 */
    05419 #define   SUPC_WUIR_WKUPT8_HIGH_TO_LOW (0x0u << 24) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
    05420 #define   SUPC_WUIR_WKUPT8_LOW_TO_HIGH (0x1u << 24) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
    05421 #define SUPC_WUIR_WKUPT9 (0x1u << 25) /**< \brief (SUPC_WUIR) Wake Up Input Transition 9 */
    05422 #define   SUPC_WUIR_WKUPT9_HIGH_TO_LOW (0x0u << 25) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
    05423 #define   SUPC_WUIR_WKUPT9_LOW_TO_HIGH (0x1u << 25) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
    05424 #define SUPC_WUIR_WKUPT10 (0x1u << 26) /**< \brief (SUPC_WUIR) Wake Up Input Transition 10 */
    05425 #define   SUPC_WUIR_WKUPT10_HIGH_TO_LOW (0x0u << 26) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
    05426 #define   SUPC_WUIR_WKUPT10_LOW_TO_HIGH (0x1u << 26) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
    05427 #define SUPC_WUIR_WKUPT11 (0x1u << 27) /**< \brief (SUPC_WUIR) Wake Up Input Transition 11 */
    05428 #define   SUPC_WUIR_WKUPT11_HIGH_TO_LOW (0x0u << 27) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
    05429 #define   SUPC_WUIR_WKUPT11_LOW_TO_HIGH (0x1u << 27) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
    05430 #define SUPC_WUIR_WKUPT12 (0x1u << 28) /**< \brief (SUPC_WUIR) Wake Up Input Transition 12 */
    05431 #define   SUPC_WUIR_WKUPT12_HIGH_TO_LOW (0x0u << 28) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
    05432 #define   SUPC_WUIR_WKUPT12_LOW_TO_HIGH (0x1u << 28) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
    05433 #define SUPC_WUIR_WKUPT13 (0x1u << 29) /**< \brief (SUPC_WUIR) Wake Up Input Transition 13 */
    05434 #define   SUPC_WUIR_WKUPT13_HIGH_TO_LOW (0x0u << 29) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
    05435 #define   SUPC_WUIR_WKUPT13_LOW_TO_HIGH (0x1u << 29) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
    05436 #define SUPC_WUIR_WKUPT14 (0x1u << 30) /**< \brief (SUPC_WUIR) Wake Up Input Transition 14 */
    05437 #define   SUPC_WUIR_WKUPT14_HIGH_TO_LOW (0x0u << 30) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
    05438 #define   SUPC_WUIR_WKUPT14_LOW_TO_HIGH (0x1u << 30) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
    05439 #define SUPC_WUIR_WKUPT15 (0x1u << 31) /**< \brief (SUPC_WUIR) Wake Up Input Transition 15 */
    05440 #define   SUPC_WUIR_WKUPT15_HIGH_TO_LOW (0x0u << 31) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
    05441 #define   SUPC_WUIR_WKUPT15_LOW_TO_HIGH (0x1u << 31) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
    05442 /* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */
    05443 #define SUPC_SR_WKUPS (0x1u << 1) /**< \brief (SUPC_SR) WKUP Wake Up Status */
    05444 #define   SUPC_SR_WKUPS_NO (0x0u << 1) /**< \brief (SUPC_SR) no wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */
    05445 #define   SUPC_SR_WKUPS_PRESENT (0x1u << 1) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */
    05446 #define SUPC_SR_SMWS (0x1u << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake Up Status */
    05447 #define   SUPC_SR_SMWS_NO (0x0u << 2) /**< \brief (SUPC_SR) no wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */
    05448 #define   SUPC_SR_SMWS_PRESENT (0x1u << 2) /**< \brief (SUPC_SR) at least one wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */
    05449 #define SUPC_SR_BODRSTS (0x1u << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status */
    05450 #define   SUPC_SR_BODRSTS_NO (0x0u << 3) /**< \brief (SUPC_SR) no core brownout rising edge event has been detected since the last read of the SUPC_SR. */
    05451 #define   SUPC_SR_BODRSTS_PRESENT (0x1u << 3) /**< \brief (SUPC_SR) at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */
    05452 #define SUPC_SR_SMRSTS (0x1u << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status */
    05453 #define   SUPC_SR_SMRSTS_NO (0x0u << 4) /**< \brief (SUPC_SR) no supply monitor detection has generated a core reset since the last read of the SUPC_SR. */
    05454 #define   SUPC_SR_SMRSTS_PRESENT (0x1u << 4) /**< \brief (SUPC_SR) at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */
    05455 #define SUPC_SR_SMS (0x1u << 5) /**< \brief (SUPC_SR) Supply Monitor Status */
    05456 #define   SUPC_SR_SMS_NO (0x0u << 5) /**< \brief (SUPC_SR) no supply monitor detection since the last read of SUPC_SR. */
    05457 #define   SUPC_SR_SMS_PRESENT (0x1u << 5) /**< \brief (SUPC_SR) at least one supply monitor detection since the last read of SUPC_SR. */
    05458 #define SUPC_SR_SMOS (0x1u << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */
    05459 #define   SUPC_SR_SMOS_HIGH (0x0u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO higher than its threshold at its last measurement. */
    05460 #define   SUPC_SR_SMOS_LOW (0x1u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO lower than its threshold at its last measurement. */
    05461 #define SUPC_SR_OSCSEL (0x1u << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */
    05462 #define   SUPC_SR_OSCSEL_RC (0x0u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. */
    05463 #define   SUPC_SR_OSCSEL_CRYST (0x1u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the 32-kHz crystal oscillator. */
    05464 #define SUPC_SR_LPDBCS0 (0x1u << 13) /**< \brief (SUPC_SR) Low Power Debouncer Wake Up Status on WKUP0 */
    05465 #define   SUPC_SR_LPDBCS0_NO (0x0u << 13) /**< \brief (SUPC_SR) no wake up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */
    05466 #define   SUPC_SR_LPDBCS0_PRESENT (0x1u << 13) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */
    05467 #define SUPC_SR_LPDBCS1 (0x1u << 14) /**< \brief (SUPC_SR) Low Power Debouncer Wake Up Status on WKUP1 */
    05468 #define   SUPC_SR_LPDBCS1_NO (0x0u << 14) /**< \brief (SUPC_SR) no wake up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */
    05469 #define   SUPC_SR_LPDBCS1_PRESENT (0x1u << 14) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */
    05470 #define SUPC_SR_WKUPIS0 (0x1u << 16) /**< \brief (SUPC_SR) WKUP Input Status 0 */
    05471 #define   SUPC_SR_WKUPIS0_DIS (0x0u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
    05472 #define   SUPC_SR_WKUPIS0_EN (0x1u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
    05473 #define SUPC_SR_WKUPIS1 (0x1u << 17) /**< \brief (SUPC_SR) WKUP Input Status 1 */
    05474 #define   SUPC_SR_WKUPIS1_DIS (0x0u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
    05475 #define   SUPC_SR_WKUPIS1_EN (0x1u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
    05476 #define SUPC_SR_WKUPIS2 (0x1u << 18) /**< \brief (SUPC_SR) WKUP Input Status 2 */
    05477 #define   SUPC_SR_WKUPIS2_DIS (0x0u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
    05478 #define   SUPC_SR_WKUPIS2_EN (0x1u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
    05479 #define SUPC_SR_WKUPIS3 (0x1u << 19) /**< \brief (SUPC_SR) WKUP Input Status 3 */
    05480 #define   SUPC_SR_WKUPIS3_DIS (0x0u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
    05481 #define   SUPC_SR_WKUPIS3_EN (0x1u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
    05482 #define SUPC_SR_WKUPIS4 (0x1u << 20) /**< \brief (SUPC_SR) WKUP Input Status 4 */
    05483 #define   SUPC_SR_WKUPIS4_DIS (0x0u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
    05484 #define   SUPC_SR_WKUPIS4_EN (0x1u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
    05485 #define SUPC_SR_WKUPIS5 (0x1u << 21) /**< \brief (SUPC_SR) WKUP Input Status 5 */
    05486 #define   SUPC_SR_WKUPIS5_DIS (0x0u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
    05487 #define   SUPC_SR_WKUPIS5_EN (0x1u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
    05488 #define SUPC_SR_WKUPIS6 (0x1u << 22) /**< \brief (SUPC_SR) WKUP Input Status 6 */
    05489 #define   SUPC_SR_WKUPIS6_DIS (0x0u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
    05490 #define   SUPC_SR_WKUPIS6_EN (0x1u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
    05491 #define SUPC_SR_WKUPIS7 (0x1u << 23) /**< \brief (SUPC_SR) WKUP Input Status 7 */
    05492 #define   SUPC_SR_WKUPIS7_DIS (0x0u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
    05493 #define   SUPC_SR_WKUPIS7_EN (0x1u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
    05494 #define SUPC_SR_WKUPIS8 (0x1u << 24) /**< \brief (SUPC_SR) WKUP Input Status 8 */
    05495 #define   SUPC_SR_WKUPIS8_DIS (0x0u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
    05496 #define   SUPC_SR_WKUPIS8_EN (0x1u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
    05497 #define SUPC_SR_WKUPIS9 (0x1u << 25) /**< \brief (SUPC_SR) WKUP Input Status 9 */
    05498 #define   SUPC_SR_WKUPIS9_DIS (0x0u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
    05499 #define   SUPC_SR_WKUPIS9_EN (0x1u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
    05500 #define SUPC_SR_WKUPIS10 (0x1u << 26) /**< \brief (SUPC_SR) WKUP Input Status 10 */
    05501 #define   SUPC_SR_WKUPIS10_DIS (0x0u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
    05502 #define   SUPC_SR_WKUPIS10_EN (0x1u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
    05503 #define SUPC_SR_WKUPIS11 (0x1u << 27) /**< \brief (SUPC_SR) WKUP Input Status 11 */
    05504 #define   SUPC_SR_WKUPIS11_DIS (0x0u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
    05505 #define   SUPC_SR_WKUPIS11_EN (0x1u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
    05506 #define SUPC_SR_WKUPIS12 (0x1u << 28) /**< \brief (SUPC_SR) WKUP Input Status 12 */
    05507 #define   SUPC_SR_WKUPIS12_DIS (0x0u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
    05508 #define   SUPC_SR_WKUPIS12_EN (0x1u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
    05509 #define SUPC_SR_WKUPIS13 (0x1u << 29) /**< \brief (SUPC_SR) WKUP Input Status 13 */
    05510 #define   SUPC_SR_WKUPIS13_DIS (0x0u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
    05511 #define   SUPC_SR_WKUPIS13_EN (0x1u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
    05512 #define SUPC_SR_WKUPIS14 (0x1u << 30) /**< \brief (SUPC_SR) WKUP Input Status 14 */
    05513 #define   SUPC_SR_WKUPIS14_DIS (0x0u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
    05514 #define   SUPC_SR_WKUPIS14_EN (0x1u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
    05515 #define SUPC_SR_WKUPIS15 (0x1u << 31) /**< \brief (SUPC_SR) WKUP Input Status 15 */
    05516 #define   SUPC_SR_WKUPIS15_DIS (0x0u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
    05517 #define   SUPC_SR_WKUPIS15_EN (0x1u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
    05518
    05519 /*@}*/
    05520
    05521 /* ============================================================================= */
    05522 /**  SOFTWARE API DEFINITION FOR Timer Counter */
    05523 /* ============================================================================= */
    05524 /** \addtogroup SAM3S8_TC Timer Counter */
    05525 /*@{*/
    05526
    05527 #ifndef __ASSEMBLY__
    05528 /** \brief TcChannel hardware registers */
    05529 typedef struct {
    05530   RwReg      TC_CCR;        /**< \brief (TcChannel Offset: 0x0) Channel Control Register */
    05531   RwReg      TC_CMR;        /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */
    05532   RwReg      TC_SMMR;       /**< \brief (TcChannel Offset: 0x8) Stepper Motor Mode Register */
    05533   RoReg      Reserved1[1];
    05534   RwReg      TC_CV;         /**< \brief (TcChannel Offset: 0x10) Counter Value */
    05535   RwReg      TC_RA;         /**< \brief (TcChannel Offset: 0x14) Register A */
    05536   RwReg      TC_RB;         /**< \brief (TcChannel Offset: 0x18) Register B */
    05537   RwReg      TC_RC;         /**< \brief (TcChannel Offset: 0x1C) Register C */
    05538   RwReg      TC_SR;         /**< \brief (TcChannel Offset: 0x20) Status Register */
    05539   RwReg      TC_IER;        /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */
    05540   RwReg      TC_IDR;        /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */
    05541   RwReg      TC_IMR;        /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */
    05542   RoReg      Reserved2[4];
    05543 } TcChannel;
    05544 /** \brief Tc hardware registers */
    05545 #define TCCHANNEL_NUMBER 3
    05546 typedef struct {
    05547   TcChannel  TC_CHANNEL[TCCHANNEL_NUMBER]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */
    05548   WoReg      TC_BCR;        /**< \brief (Tc Offset: 0xC0) Block Control Register */
    05549   RwReg      TC_BMR;        /**< \brief (Tc Offset: 0xC4) Block Mode Register */
    05550   WoReg      TC_QIER;       /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */
    05551   WoReg      TC_QIDR;       /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */
    05552   RoReg      TC_QIMR;       /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */
    05553   RoReg      TC_QISR;       /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */
    05554   RwReg      TC_FMR;        /**< \brief (Tc Offset: 0xD8) Fault Mode Register */
    05555   RoReg      Reserved1[2];
    05556   RwReg      TC_WPMR;       /**< \brief (Tc Offset: 0xE4) Write Protect Mode Register */
    05557 } Tc;
    05558 #endif /* __ASSEMBLY__ */
    05559 /* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */
    05560 #define TC_CCR_CLKEN (0x1u << 0) /**< \brief (TC_CCR) Counter Clock Enable Command */
    05561 #define TC_CCR_CLKDIS (0x1u << 1) /**< \brief (TC_CCR) Counter Clock Disable Command */
    05562 #define TC_CCR_SWTRG (0x1u << 2) /**< \brief (TC_CCR) Software Trigger Command */
    05563 /* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */
    05564 #define TC_CMR_TCCLKS_Pos 0
    05565 #define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) /**< \brief (TC_CMR) Clock Selection */
    05566 #define   TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /**< \brief (TC_CMR) Clock selected: TCLK1 */
    05567 #define   TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /**< \brief (TC_CMR) Clock selected: TCLK2 */
    05568 #define   TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /**< \brief (TC_CMR) Clock selected: TCLK3 */
    05569 #define   TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /**< \brief (TC_CMR) Clock selected: TCLK4 */
    05570 #define   TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /**< \brief (TC_CMR) Clock selected: TCLK5 */
    05571 #define   TC_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_CMR) Clock selected: XC0 */
    05572 #define   TC_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_CMR) Clock selected: XC1 */
    05573 #define   TC_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_CMR) Clock selected: XC2 */
    05574 #define TC_CMR_CLKI (0x1u << 3) /**< \brief (TC_CMR) Clock Invert */
    05575 #define TC_CMR_BURST_Pos 4
    05576 #define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) /**< \brief (TC_CMR) Burst Signal Selection */
    05577 #define   TC_CMR_BURST_NONE (0x0u << 4) /**< \brief (TC_CMR) The clock is not gated by an external signal. */
    05578 #define   TC_CMR_BURST_XC0 (0x1u << 4) /**< \brief (TC_CMR) XC0 is ANDed with the selected clock. */
    05579 #define   TC_CMR_BURST_XC1 (0x2u << 4) /**< \brief (TC_CMR) XC1 is ANDed with the selected clock. */
    05580 #define   TC_CMR_BURST_XC2 (0x3u << 4) /**< \brief (TC_CMR) XC2 is ANDed with the selected clock. */
    05581 #define TC_CMR_LDBSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RB Loading */
    05582 #define TC_CMR_LDBDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RB Loading */
    05583 #define TC_CMR_ETRGEDG_Pos 8
    05584 #define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) /**< \brief (TC_CMR) External Trigger Edge Selection */
    05585 #define   TC_CMR_ETRGEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) The clock is not gated by an external signal. */
    05586 #define   TC_CMR_ETRGEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */
    05587 #define   TC_CMR_ETRGEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */
    05588 #define   TC_CMR_ETRGEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */
    05589 #define TC_CMR_ABETRG (0x1u << 10) /**< \brief (TC_CMR) TIOA or TIOB External Trigger Selection */
    05590 #define TC_CMR_CPCTRG (0x1u << 14) /**< \brief (TC_CMR) RC Compare Trigger Enable */
    05591 #define TC_CMR_WAVE (0x1u << 15) /**< \brief (TC_CMR) Waveform Mode */
    05592 #define TC_CMR_LDRA_Pos 16
    05593 #define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) /**< \brief (TC_CMR) RA Loading Edge Selection */
    05594 #define   TC_CMR_LDRA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */
    05595 #define   TC_CMR_LDRA_RISING (0x1u << 16) /**< \brief (TC_CMR) Rising edge of TIOA */
    05596 #define   TC_CMR_LDRA_FALLING (0x2u << 16) /**< \brief (TC_CMR) Falling edge of TIOA */
    05597 #define   TC_CMR_LDRA_EDGE (0x3u << 16) /**< \brief (TC_CMR) Each edge of TIOA */
    05598 #define TC_CMR_LDRB_Pos 18
    05599 #define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) /**< \brief (TC_CMR) RB Loading Edge Selection */
    05600 #define   TC_CMR_LDRB_NONE (0x0u << 18) /**< \brief (TC_CMR) None */
    05601 #define   TC_CMR_LDRB_RISING (0x1u << 18) /**< \brief (TC_CMR) Rising edge of TIOA */
    05602 #define   TC_CMR_LDRB_FALLING (0x2u << 18) /**< \brief (TC_CMR) Falling edge of TIOA */
    05603 #define   TC_CMR_LDRB_EDGE (0x3u << 18) /**< \brief (TC_CMR) Each edge of TIOA */
    05604 #define TC_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */
    05605 #define TC_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */
    05606 #define TC_CMR_EEVTEDG_Pos 8
    05607 #define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /**< \brief (TC_CMR) External Event Edge Selection */
    05608 #define   TC_CMR_EEVTEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) None */
    05609 #define   TC_CMR_EEVTEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */
    05610 #define   TC_CMR_EEVTEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */
    05611 #define   TC_CMR_EEVTEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */
    05612 #define TC_CMR_EEVT_Pos 10
    05613 #define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) /**< \brief (TC_CMR) External Event Selection */
    05614 #define   TC_CMR_EEVT_TIOB (0x0u << 10) /**< \brief (TC_CMR) TIOB */
    05615 #define   TC_CMR_EEVT_XC0 (0x1u << 10) /**< \brief (TC_CMR) XC0 */
    05616 #define   TC_CMR_EEVT_XC1 (0x2u << 10) /**< \brief (TC_CMR) XC1 */
    05617 #define   TC_CMR_EEVT_XC2 (0x3u << 10) /**< \brief (TC_CMR) XC2 */
    05618 #define TC_CMR_ENETRG (0x1u << 12) /**< \brief (TC_CMR) External Event Trigger Enable */
    05619 #define TC_CMR_WAVSEL_Pos 13
    05620 #define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /**< \brief (TC_CMR) Waveform Selection */
    05621 #define   TC_CMR_WAVSEL_UP (0x0u << 13) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */
    05622 #define   TC_CMR_WAVSEL_UPDOWN (0x1u << 13) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */
    05623 #define   TC_CMR_WAVSEL_UP_RC (0x2u << 13) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */
    05624 #define   TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */
    05625 #define TC_CMR_ACPA_Pos 16
    05626 #define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /**< \brief (TC_CMR) RA Compare Effect on TIOA */
    05627 #define   TC_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */
    05628 #define   TC_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_CMR) Set */
    05629 #define   TC_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_CMR) Clear */
    05630 #define   TC_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_CMR) Toggle */
    05631 #define TC_CMR_ACPC_Pos 18
    05632 #define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOA */
    05633 #define   TC_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_CMR) None */
    05634 #define   TC_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_CMR) Set */
    05635 #define   TC_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_CMR) Clear */
    05636 #define   TC_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_CMR) Toggle */
    05637 #define TC_CMR_AEEVT_Pos 20
    05638 #define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOA */
    05639 #define   TC_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_CMR) None */
    05640 #define   TC_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_CMR) Set */
    05641 #define   TC_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_CMR) Clear */
    05642 #define   TC_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_CMR) Toggle */
    05643 #define TC_CMR_ASWTRG_Pos 22
    05644 #define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOA */
    05645 #define   TC_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_CMR) None */
    05646 #define   TC_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_CMR) Set */
    05647 #define   TC_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_CMR) Clear */
    05648 #define   TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_CMR) Toggle */
    05649 #define TC_CMR_BCPB_Pos 24
    05650 #define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /**< \brief (TC_CMR) RB Compare Effect on TIOB */
    05651 #define   TC_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_CMR) None */
    05652 #define   TC_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_CMR) Set */
    05653 #define   TC_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_CMR) Clear */
    05654 #define   TC_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_CMR) Toggle */
    05655 #define TC_CMR_BCPC_Pos 26
    05656 #define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOB */
    05657 #define   TC_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_CMR) None */
    05658 #define   TC_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_CMR) Set */
    05659 #define   TC_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_CMR) Clear */
    05660 #define   TC_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_CMR) Toggle */
    05661 #define TC_CMR_BEEVT_Pos 28
    05662 #define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOB */
    05663 #define   TC_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_CMR) None */
    05664 #define   TC_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_CMR) Set */
    05665 #define   TC_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_CMR) Clear */
    05666 #define   TC_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_CMR) Toggle */
    05667 #define TC_CMR_BSWTRG_Pos 30
    05668 #define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOB */
    05669 #define   TC_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_CMR) None */
    05670 #define   TC_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_CMR) Set */
    05671 #define   TC_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_CMR) Clear */
    05672 #define   TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_CMR) Toggle */
    05673 /* -------- TC_SMMR : (TC Offset: N/A) Stepper Motor Mode Register -------- */
    05674 #define TC_SMMR_GCEN (0x1u << 0) /**< \brief (TC_SMMR) Gray Count Enable */
    05675 #define TC_SMMR_DOWN (0x1u << 1) /**< \brief (TC_SMMR) DOWN Count */
    05676 /* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */
    05677 #define TC_CV_CV_Pos 0
    05678 #define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos) /**< \brief (TC_CV) Counter Value */
    05679 /* -------- TC_RA : (TC Offset: N/A) Register A -------- */
    05680 #define TC_RA_RA_Pos 0
    05681 #define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos) /**< \brief (TC_RA) Register A */
    05682 #define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos)))
    05683 /* -------- TC_RB : (TC Offset: N/A) Register B -------- */
    05684 #define TC_RB_RB_Pos 0
    05685 #define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos) /**< \brief (TC_RB) Register B */
    05686 #define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos)))
    05687 /* -------- TC_RC : (TC Offset: N/A) Register C -------- */
    05688 #define TC_RC_RC_Pos 0
    05689 #define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos) /**< \brief (TC_RC) Register C */
    05690 #define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos)))
    05691 /* -------- TC_SR : (TC Offset: N/A) Status Register -------- */
    05692 #define TC_SR_COVFS (0x1u << 0) /**< \brief (TC_SR) Counter Overflow Status */
    05693 #define TC_SR_LOVRS (0x1u << 1) /**< \brief (TC_SR) Load Overrun Status */
    05694 #define TC_SR_CPAS (0x1u << 2) /**< \brief (TC_SR) RA Compare Status */
    05695 #define TC_SR_CPBS (0x1u << 3) /**< \brief (TC_SR) RB Compare Status */
    05696 #define TC_SR_CPCS (0x1u << 4) /**< \brief (TC_SR) RC Compare Status */
    05697 #define TC_SR_LDRAS (0x1u << 5) /**< \brief (TC_SR) RA Loading Status */
    05698 #define TC_SR_LDRBS (0x1u << 6) /**< \brief (TC_SR) RB Loading Status */
    05699 #define TC_SR_ETRGS (0x1u << 7) /**< \brief (TC_SR) External Trigger Status */
    05700 #define TC_SR_CLKSTA (0x1u << 16) /**< \brief (TC_SR) Clock Enabling Status */
    05701 #define TC_SR_MTIOA (0x1u << 17) /**< \brief (TC_SR) TIOA Mirror */
    05702 #define TC_SR_MTIOB (0x1u << 18) /**< \brief (TC_SR) TIOB Mirror */
    05703 /* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */
    05704 #define TC_IER_COVFS (0x1u << 0) /**< \brief (TC_IER) Counter Overflow */
    05705 #define TC_IER_LOVRS (0x1u << 1) /**< \brief (TC_IER) Load Overrun */
    05706 #define TC_IER_CPAS (0x1u << 2) /**< \brief (TC_IER) RA Compare */
    05707 #define TC_IER_CPBS (0x1u << 3) /**< \brief (TC_IER) RB Compare */
    05708 #define TC_IER_CPCS (0x1u << 4) /**< \brief (TC_IER) RC Compare */
    05709 #define TC_IER_LDRAS (0x1u << 5) /**< \brief (TC_IER) RA Loading */
    05710 #define TC_IER_LDRBS (0x1u << 6) /**< \brief (TC_IER) RB Loading */
    05711 #define TC_IER_ETRGS (0x1u << 7) /**< \brief (TC_IER) External Trigger */
    05712 /* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */
    05713 #define TC_IDR_COVFS (0x1u << 0) /**< \brief (TC_IDR) Counter Overflow */
    05714 #define TC_IDR_LOVRS (0x1u << 1) /**< \brief (TC_IDR) Load Overrun */
    05715 #define TC_IDR_CPAS (0x1u << 2) /**< \brief (TC_IDR) RA Compare */
    05716 #define TC_IDR_CPBS (0x1u << 3) /**< \brief (TC_IDR) RB Compare */
    05717 #define TC_IDR_CPCS (0x1u << 4) /**< \brief (TC_IDR) RC Compare */
    05718 #define TC_IDR_LDRAS (0x1u << 5) /**< \brief (TC_IDR) RA Loading */
    05719 #define TC_IDR_LDRBS (0x1u << 6) /**< \brief (TC_IDR) RB Loading */
    05720 #define TC_IDR_ETRGS (0x1u << 7) /**< \brief (TC_IDR) External Trigger */
    05721 /* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */
    05722 #define TC_IMR_COVFS (0x1u << 0) /**< \brief (TC_IMR) Counter Overflow */
    05723 #define TC_IMR_LOVRS (0x1u << 1) /**< \brief (TC_IMR) Load Overrun */
    05724 #define TC_IMR_CPAS (0x1u << 2) /**< \brief (TC_IMR) RA Compare */
    05725 #define TC_IMR_CPBS (0x1u << 3) /**< \brief (TC_IMR) RB Compare */
    05726 #define TC_IMR_CPCS (0x1u << 4) /**< \brief (TC_IMR) RC Compare */
    05727 #define TC_IMR_LDRAS (0x1u << 5) /**< \brief (TC_IMR) RA Loading */
    05728 #define TC_IMR_LDRBS (0x1u << 6) /**< \brief (TC_IMR) RB Loading */
    05729 #define TC_IMR_ETRGS (0x1u << 7) /**< \brief (TC_IMR) External Trigger */
    05730 /* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */
    05731 #define TC_BCR_SYNC (0x1u << 0) /**< \brief (TC_BCR) Synchro Command */
    05732 /* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */
    05733 #define TC_BMR_TC0XC0S_Pos 0
    05734 #define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) /**< \brief (TC_BMR) External Clock Signal 0 Selection */
    05735 #define   TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TCLK0 */
    05736 #define   TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA1 */
    05737 #define   TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA2 */
    05738 #define TC_BMR_TC1XC1S_Pos 2
    05739 #define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) /**< \brief (TC_BMR) External Clock Signal 1 Selection */
    05740 #define   TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TCLK1 */
    05741 #define   TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA0 */
    05742 #define   TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA2 */
    05743 #define TC_BMR_TC2XC2S_Pos 4
    05744 #define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) /**< \brief (TC_BMR) External Clock Signal 2 Selection */
    05745 #define   TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TCLK2 */
    05746 #define   TC_BMR_TC2XC2S_TIOA1 (0x2u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA1 */
    05747 #define   TC_BMR_TC2XC2S_TIOA2 (0x3u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA2 */
    05748 #define TC_BMR_QDEN (0x1u << 8) /**< \brief (TC_BMR) Quadrature Decoder ENabled */
    05749 #define TC_BMR_POSEN (0x1u << 9) /**< \brief (TC_BMR) POSition ENabled */
    05750 #define TC_BMR_SPEEDEN (0x1u << 10) /**< \brief (TC_BMR) SPEED ENabled */
    05751 #define TC_BMR_QDTRANS (0x1u << 11) /**< \brief (TC_BMR) Quadrature Decoding TRANSparent */
    05752 #define TC_BMR_EDGPHA (0x1u << 12) /**< \brief (TC_BMR) EDGe on PHA count mode */
    05753 #define TC_BMR_INVA (0x1u << 13) /**< \brief (TC_BMR) INVerted phA */
    05754 #define TC_BMR_INVB (0x1u << 14) /**< \brief (TC_BMR) INVerted phB */
    05755 #define TC_BMR_INVIDX (0x1u << 15) /**< \brief (TC_BMR) INVerted InDeX */
    05756 #define TC_BMR_SWAP (0x1u << 16) /**< \brief (TC_BMR) SWAP PHA and PHB */
    05757 #define TC_BMR_IDXPHB (0x1u << 17) /**< \brief (TC_BMR) InDeX pin is PHB pin */
    05758 #define TC_BMR_FILTER (0x1u << 19) /**< \brief (TC_BMR)  */
    05759 #define TC_BMR_MAXFILT_Pos 20
    05760 #define TC_BMR_MAXFILT_Msk (0x3fu << TC_BMR_MAXFILT_Pos) /**< \brief (TC_BMR) MAXimum FILTer */
    05761 #define TC_BMR_MAXFILT(value) ((TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos)))
    05762 /* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */
    05763 #define TC_QIER_IDX (0x1u << 0) /**< \brief (TC_QIER) InDeX */
    05764 #define TC_QIER_DIRCHG (0x1u << 1) /**< \brief (TC_QIER) DIRection CHanGe */
    05765 #define TC_QIER_QERR (0x1u << 2) /**< \brief (TC_QIER) Quadrature ERRor */
    05766 /* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */
    05767 #define TC_QIDR_IDX (0x1u << 0) /**< \brief (TC_QIDR) InDeX */
    05768 #define TC_QIDR_DIRCHG (0x1u << 1) /**< \brief (TC_QIDR) DIRection CHanGe */
    05769 #define TC_QIDR_QERR (0x1u << 2) /**< \brief (TC_QIDR) Quadrature ERRor */
    05770 /* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */
    05771 #define TC_QIMR_IDX (0x1u << 0) /**< \brief (TC_QIMR) InDeX */
    05772 #define TC_QIMR_DIRCHG (0x1u << 1) /**< \brief (TC_QIMR) DIRection CHanGe */
    05773 #define TC_QIMR_QERR (0x1u << 2) /**< \brief (TC_QIMR) Quadrature ERRor */
    05774 /* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */
    05775 #define TC_QISR_IDX (0x1u << 0) /**< \brief (TC_QISR) InDeX */
    05776 #define TC_QISR_DIRCHG (0x1u << 1) /**< \brief (TC_QISR) DIRection CHanGe */
    05777 #define TC_QISR_QERR (0x1u << 2) /**< \brief (TC_QISR) Quadrature ERRor */
    05778 #define TC_QISR_DIR (0x1u << 8) /**< \brief (TC_QISR) Direction */
    05779 /* -------- TC_FMR : (TC Offset: 0xD8) Fault Mode Register -------- */
    05780 #define TC_FMR_ENCF0 (0x1u << 0) /**< \brief (TC_FMR) ENable Compare Fault Channel 0 */
    05781 #define TC_FMR_ENCF1 (0x1u << 1) /**< \brief (TC_FMR) ENable Compare Fault Channel 1 */
    05782 /* -------- TC_WPMR : (TC Offset: 0xE4) Write Protect Mode Register -------- */
    05783 #define TC_WPMR_WPEN (0x1u << 0) /**< \brief (TC_WPMR) Write Protect Enable */
    05784 #define TC_WPMR_WPKEY_Pos 8
    05785 #define TC_WPMR_WPKEY_Msk (0xffffffu << TC_WPMR_WPKEY_Pos) /**< \brief (TC_WPMR) Write Protect KEY */
    05786 #define TC_WPMR_WPKEY(value) ((TC_WPMR_WPKEY_Msk & ((value) << TC_WPMR_WPKEY_Pos)))
    05787
    05788 /*@}*/
    05789
    05790 /* ============================================================================= */
    05791 /**  SOFTWARE API DEFINITION FOR Two-wire Interface */
    05792 /* ============================================================================= */
    05793 /** \addtogroup SAM3S8_TWI Two-wire Interface */
    05794 /*@{*/
    05795
    05796 #ifndef __ASSEMBLY__
    05797 /** \brief Twi hardware registers */
    05798 typedef struct {
    05799   WoReg TWI_CR;        /**< \brief (Twi Offset: 0x00) Control Register */
    05800   RwReg TWI_MMR;       /**< \brief (Twi Offset: 0x04) Master Mode Register */
    05801   RwReg TWI_SMR;       /**< \brief (Twi Offset: 0x08) Slave Mode Register */
    05802   RwReg TWI_IADR;      /**< \brief (Twi Offset: 0x0C) Internal Address Register */
    05803   RwReg TWI_CWGR;      /**< \brief (Twi Offset: 0x10) Clock Waveform Generator Register */
    05804   RoReg Reserved1[3];
    05805   RoReg TWI_SR;        /**< \brief (Twi Offset: 0x20) Status Register */
    05806   WoReg TWI_IER;       /**< \brief (Twi Offset: 0x24) Interrupt Enable Register */
    05807   WoReg TWI_IDR;       /**< \brief (Twi Offset: 0x28) Interrupt Disable Register */
    05808   RoReg TWI_IMR;       /**< \brief (Twi Offset: 0x2C) Interrupt Mask Register */
    05809   RoReg TWI_RHR;       /**< \brief (Twi Offset: 0x30) Receive Holding Register */
    05810   WoReg TWI_THR;       /**< \brief (Twi Offset: 0x34) Transmit Holding Register */
    05811   RoReg Reserved2[50];
    05812   RwReg TWI_RPR;       /**< \brief (Twi Offset: 0x100) Receive Pointer Register */
    05813   RwReg TWI_RCR;       /**< \brief (Twi Offset: 0x104) Receive Counter Register */
    05814   RwReg TWI_TPR;       /**< \brief (Twi Offset: 0x108) Transmit Pointer Register */
    05815   RwReg TWI_TCR;       /**< \brief (Twi Offset: 0x10C) Transmit Counter Register */
    05816   RwReg TWI_RNPR;      /**< \brief (Twi Offset: 0x110) Receive Next Pointer Register */
    05817   RwReg TWI_RNCR;      /**< \brief (Twi Offset: 0x114) Receive Next Counter Register */
    05818   RwReg TWI_TNPR;      /**< \brief (Twi Offset: 0x118) Transmit Next Pointer Register */
    05819   RwReg TWI_TNCR;      /**< \brief (Twi Offset: 0x11C) Transmit Next Counter Register */
    05820   WoReg TWI_PTCR;      /**< \brief (Twi Offset: 0x120) Transfer Control Register */
    05821   RoReg TWI_PTSR;      /**< \brief (Twi Offset: 0x124) Transfer Status Register */
    05822 } Twi;
    05823 #endif /* __ASSEMBLY__ */
    05824 /* -------- TWI_CR : (TWI Offset: 0x00) Control Register -------- */
    05825 #define TWI_CR_START (0x1u << 0) /**< \brief (TWI_CR) Send a START Condition */
    05826 #define TWI_CR_STOP (0x1u << 1) /**< \brief (TWI_CR) Send a STOP Condition */
    05827 #define TWI_CR_MSEN (0x1u << 2) /**< \brief (TWI_CR) TWI Master Mode Enabled */
    05828 #define TWI_CR_MSDIS (0x1u << 3) /**< \brief (TWI_CR) TWI Master Mode Disabled */
    05829 #define TWI_CR_SVEN (0x1u << 4) /**< \brief (TWI_CR) TWI Slave Mode Enabled */
    05830 #define TWI_CR_SVDIS (0x1u << 5) /**< \brief (TWI_CR) TWI Slave Mode Disabled */
    05831 #define TWI_CR_QUICK (0x1u << 6) /**< \brief (TWI_CR) SMBUS Quick Command */
    05832 #define TWI_CR_SWRST (0x1u << 7) /**< \brief (TWI_CR) Software Reset */
    05833 /* -------- TWI_MMR : (TWI Offset: 0x04) Master Mode Register -------- */
    05834 #define TWI_MMR_IADRSZ_Pos 8
    05835 #define TWI_MMR_IADRSZ_Msk (0x3u << TWI_MMR_IADRSZ_Pos) /**< \brief (TWI_MMR) Internal Device Address Size */
    05836 #define   TWI_MMR_IADRSZ_NONE (0x0u << 8) /**< \brief (TWI_MMR) No internal device address */
    05837 #define   TWI_MMR_IADRSZ_1_BYTE (0x1u << 8) /**< \brief (TWI_MMR) One-byte internal device address */
    05838 #define   TWI_MMR_IADRSZ_2_BYTE (0x2u << 8) /**< \brief (TWI_MMR) Two-byte internal device address */
    05839 #define   TWI_MMR_IADRSZ_3_BYTE (0x3u << 8) /**< \brief (TWI_MMR) Three-byte internal device address */
    05840 #define TWI_MMR_MREAD (0x1u << 12) /**< \brief (TWI_MMR) Master Read Direction */
    05841 #define TWI_MMR_DADR_Pos 16
    05842 #define TWI_MMR_DADR_Msk (0x7fu << TWI_MMR_DADR_Pos) /**< \brief (TWI_MMR) Device Address */
    05843 #define TWI_MMR_DADR(value) ((TWI_MMR_DADR_Msk & ((value) << TWI_MMR_DADR_Pos)))
    05844 /* -------- TWI_SMR : (TWI Offset: 0x08) Slave Mode Register -------- */
    05845 #define TWI_SMR_SADR_Pos 16
    05846 #define TWI_SMR_SADR_Msk (0x7fu << TWI_SMR_SADR_Pos) /**< \brief (TWI_SMR) Slave Address */
    05847 #define TWI_SMR_SADR(value) ((TWI_SMR_SADR_Msk & ((value) << TWI_SMR_SADR_Pos)))
    05848 /* -------- TWI_IADR : (TWI Offset: 0x0C) Internal Address Register -------- */
    05849 #define TWI_IADR_IADR_Pos 0
    05850 #define TWI_IADR_IADR_Msk (0xffffffu << TWI_IADR_IADR_Pos) /**< \brief (TWI_IADR) Internal Address */
    05851 #define TWI_IADR_IADR(value) ((TWI_IADR_IADR_Msk & ((value) << TWI_IADR_IADR_Pos)))
    05852 /* -------- TWI_CWGR : (TWI Offset: 0x10) Clock Waveform Generator Register -------- */
    05853 #define TWI_CWGR_CLDIV_Pos 0
    05854 #define TWI_CWGR_CLDIV_Msk (0xffu << TWI_CWGR_CLDIV_Pos) /**< \brief (TWI_CWGR) Clock Low Divider */
    05855 #define TWI_CWGR_CLDIV(value) ((TWI_CWGR_CLDIV_Msk & ((value) << TWI_CWGR_CLDIV_Pos)))
    05856 #define TWI_CWGR_CHDIV_Pos 8
    05857 #define TWI_CWGR_CHDIV_Msk (0xffu << TWI_CWGR_CHDIV_Pos) /**< \brief (TWI_CWGR) Clock High Divider */
    05858 #define TWI_CWGR_CHDIV(value) ((TWI_CWGR_CHDIV_Msk & ((value) << TWI_CWGR_CHDIV_Pos)))
    05859 #define TWI_CWGR_CKDIV_Pos 16
    05860 #define TWI_CWGR_CKDIV_Msk (0x7u << TWI_CWGR_CKDIV_Pos) /**< \brief (TWI_CWGR) Clock Divider */
    05861 #define TWI_CWGR_CKDIV(value) ((TWI_CWGR_CKDIV_Msk & ((value) << TWI_CWGR_CKDIV_Pos)))
    05862 /* -------- TWI_SR : (TWI Offset: 0x20) Status Register -------- */
    05863 #define TWI_SR_TXCOMP (0x1u << 0) /**< \brief (TWI_SR) Transmission Completed (automatically set / reset) */
    05864 #define TWI_SR_RXRDY (0x1u << 1) /**< \brief (TWI_SR) Receive Holding Register Ready (automatically set / reset) */
    05865 #define TWI_SR_TXRDY (0x1u << 2) /**< \brief (TWI_SR) Transmit Holding Register Ready (automatically set / reset) */
    05866 #define TWI_SR_SVREAD (0x1u << 3) /**< \brief (TWI_SR) Slave Read (automatically set / reset) */
    05867 #define TWI_SR_SVACC (0x1u << 4) /**< \brief (TWI_SR) Slave Access (automatically set / reset) */
    05868 #define TWI_SR_GACC (0x1u << 5) /**< \brief (TWI_SR) General Call Access (clear on read) */
    05869 #define TWI_SR_OVRE (0x1u << 6) /**< \brief (TWI_SR) Overrun Error (clear on read) */
    05870 #define TWI_SR_NACK (0x1u << 8) /**< \brief (TWI_SR) Not Acknowledged (clear on read) */
    05871 #define TWI_SR_ARBLST (0x1u << 9) /**< \brief (TWI_SR) Arbitration Lost (clear on read) */
    05872 #define TWI_SR_SCLWS (0x1u << 10) /**< \brief (TWI_SR) Clock Wait State (automatically set / reset) */
    05873 #define TWI_SR_EOSACC (0x1u << 11) /**< \brief (TWI_SR) End Of Slave Access (clear on read) */
    05874 #define TWI_SR_ENDRX (0x1u << 12) /**< \brief (TWI_SR) End of RX buffer */
    05875 #define TWI_SR_ENDTX (0x1u << 13) /**< \brief (TWI_SR) End of TX buffer */
    05876 #define TWI_SR_RXBUFF (0x1u << 14) /**< \brief (TWI_SR) RX Buffer Full */
    05877 #define TWI_SR_TXBUFE (0x1u << 15) /**< \brief (TWI_SR) TX Buffer Empty */
    05878 /* -------- TWI_IER : (TWI Offset: 0x24) Interrupt Enable Register -------- */
    05879 #define TWI_IER_TXCOMP (0x1u << 0) /**< \brief (TWI_IER) Transmission Completed Interrupt Enable */
    05880 #define TWI_IER_RXRDY (0x1u << 1) /**< \brief (TWI_IER) Receive Holding Register Ready Interrupt Enable */
    05881 #define TWI_IER_TXRDY (0x1u << 2) /**< \brief (TWI_IER) Transmit Holding Register Ready Interrupt Enable */
    05882 #define TWI_IER_SVACC (0x1u << 4) /**< \brief (TWI_IER) Slave Access Interrupt Enable */
    05883 #define TWI_IER_GACC (0x1u << 5) /**< \brief (TWI_IER) General Call Access Interrupt Enable */
    05884 #define TWI_IER_OVRE (0x1u << 6) /**< \brief (TWI_IER) Overrun Error Interrupt Enable */
    05885 #define TWI_IER_NACK (0x1u << 8) /**< \brief (TWI_IER) Not Acknowledge Interrupt Enable */
    05886 #define TWI_IER_ARBLST (0x1u << 9) /**< \brief (TWI_IER) Arbitration Lost Interrupt Enable */
    05887 #define TWI_IER_SCL_WS (0x1u << 10) /**< \brief (TWI_IER) Clock Wait State Interrupt Enable */
    05888 #define TWI_IER_EOSACC (0x1u << 11) /**< \brief (TWI_IER) End Of Slave Access Interrupt Enable */
    05889 #define TWI_IER_ENDRX (0x1u << 12) /**< \brief (TWI_IER) End of Receive Buffer Interrupt Enable */
    05890 #define TWI_IER_ENDTX (0x1u << 13) /**< \brief (TWI_IER) End of Transmit Buffer Interrupt Enable */
    05891 #define TWI_IER_RXBUFF (0x1u << 14) /**< \brief (TWI_IER) Receive Buffer Full Interrupt Enable */
    05892 #define TWI_IER_TXBUFE (0x1u << 15) /**< \brief (TWI_IER) Transmit Buffer Empty Interrupt Enable */
    05893 /* -------- TWI_IDR : (TWI Offset: 0x28) Interrupt Disable Register -------- */
    05894 #define TWI_IDR_TXCOMP (0x1u << 0) /**< \brief (TWI_IDR) Transmission Completed Interrupt Disable */
    05895 #define TWI_IDR_RXRDY (0x1u << 1) /**< \brief (TWI_IDR) Receive Holding Register Ready Interrupt Disable */
    05896 #define TWI_IDR_TXRDY (0x1u << 2) /**< \brief (TWI_IDR) Transmit Holding Register Ready Interrupt Disable */
    05897 #define TWI_IDR_SVACC (0x1u << 4) /**< \brief (TWI_IDR) Slave Access Interrupt Disable */
    05898 #define TWI_IDR_GACC (0x1u << 5) /**< \brief (TWI_IDR) General Call Access Interrupt Disable */
    05899 #define TWI_IDR_OVRE (0x1u << 6) /**< \brief (TWI_IDR) Overrun Error Interrupt Disable */
    05900 #define TWI_IDR_NACK (0x1u << 8) /**< \brief (TWI_IDR) Not Acknowledge Interrupt Disable */
    05901 #define TWI_IDR_ARBLST (0x1u << 9) /**< \brief (TWI_IDR) Arbitration Lost Interrupt Disable */
    05902 #define TWI_IDR_SCL_WS (0x1u << 10) /**< \brief (TWI_IDR) Clock Wait State Interrupt Disable */
    05903 #define TWI_IDR_EOSACC (0x1u << 11) /**< \brief (TWI_IDR) End Of Slave Access Interrupt Disable */
    05904 #define TWI_IDR_ENDRX (0x1u << 12) /**< \brief (TWI_IDR) End of Receive Buffer Interrupt Disable */
    05905 #define TWI_IDR_ENDTX (0x1u << 13) /**< \brief (TWI_IDR) End of Transmit Buffer Interrupt Disable */
    05906 #define TWI_IDR_RXBUFF (0x1u << 14) /**< \brief (TWI_IDR) Receive Buffer Full Interrupt Disable */
    05907 #define TWI_IDR_TXBUFE (0x1u << 15) /**< \brief (TWI_IDR) Transmit Buffer Empty Interrupt Disable */
    05908 /* -------- TWI_IMR : (TWI Offset: 0x2C) Interrupt Mask Register -------- */
    05909 #define TWI_IMR_TXCOMP (0x1u << 0) /**< \brief (TWI_IMR) Transmission Completed Interrupt Mask */
    05910 #define TWI_IMR_RXRDY (0x1u << 1) /**< \brief (TWI_IMR) Receive Holding Register Ready Interrupt Mask */
    05911 #define TWI_IMR_TXRDY (0x1u << 2) /**< \brief (TWI_IMR) Transmit Holding Register Ready Interrupt Mask */
    05912 #define TWI_IMR_SVACC (0x1u << 4) /**< \brief (TWI_IMR) Slave Access Interrupt Mask */
    05913 #define TWI_IMR_GACC (0x1u << 5) /**< \brief (TWI_IMR) General Call Access Interrupt Mask */
    05914 #define TWI_IMR_OVRE (0x1u << 6) /**< \brief (TWI_IMR) Overrun Error Interrupt Mask */
    05915 #define TWI_IMR_NACK (0x1u << 8) /**< \brief (TWI_IMR) Not Acknowledge Interrupt Mask */
    05916 #define TWI_IMR_ARBLST (0x1u << 9) /**< \brief (TWI_IMR) Arbitration Lost Interrupt Mask */
    05917 #define TWI_IMR_SCL_WS (0x1u << 10) /**< \brief (TWI_IMR) Clock Wait State Interrupt Mask */
    05918 #define TWI_IMR_EOSACC (0x1u << 11) /**< \brief (TWI_IMR) End Of Slave Access Interrupt Mask */
    05919 #define TWI_IMR_ENDRX (0x1u << 12) /**< \brief (TWI_IMR) End of Receive Buffer Interrupt Mask */
    05920 #define TWI_IMR_ENDTX (0x1u << 13) /**< \brief (TWI_IMR) End of Transmit Buffer Interrupt Mask */
    05921 #define TWI_IMR_RXBUFF (0x1u << 14) /**< \brief (TWI_IMR) Receive Buffer Full Interrupt Mask */
    05922 #define TWI_IMR_TXBUFE (0x1u << 15) /**< \brief (TWI_IMR) Transmit Buffer Empty Interrupt Mask */
    05923 /* -------- TWI_RHR : (TWI Offset: 0x30) Receive Holding Register -------- */
    05924 #define TWI_RHR_RXDATA_Pos 0
    05925 #define TWI_RHR_RXDATA_Msk (0xffu << TWI_RHR_RXDATA_Pos) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data */
    05926 /* -------- TWI_THR : (TWI Offset: 0x34) Transmit Holding Register -------- */
    05927 #define TWI_THR_TXDATA_Pos 0
    05928 #define TWI_THR_TXDATA_Msk (0xffu << TWI_THR_TXDATA_Pos) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data */
    05929 #define TWI_THR_TXDATA(value) ((TWI_THR_TXDATA_Msk & ((value) << TWI_THR_TXDATA_Pos)))
    05930 /* -------- TWI_RPR : (TWI Offset: 0x100) Receive Pointer Register -------- */
    05931 #define TWI_RPR_RXPTR_Pos 0
    05932 #define TWI_RPR_RXPTR_Msk (0xffffffffu << TWI_RPR_RXPTR_Pos) /**< \brief (TWI_RPR) Receive Pointer Register */
    05933 #define TWI_RPR_RXPTR(value) ((TWI_RPR_RXPTR_Msk & ((value) << TWI_RPR_RXPTR_Pos)))
    05934 /* -------- TWI_RCR : (TWI Offset: 0x104) Receive Counter Register -------- */
    05935 #define TWI_RCR_RXCTR_Pos 0
    05936 #define TWI_RCR_RXCTR_Msk (0xffffu << TWI_RCR_RXCTR_Pos) /**< \brief (TWI_RCR) Receive Counter Register */
    05937 #define TWI_RCR_RXCTR(value) ((TWI_RCR_RXCTR_Msk & ((value) << TWI_RCR_RXCTR_Pos)))
    05938 /* -------- TWI_TPR : (TWI Offset: 0x108) Transmit Pointer Register -------- */
    05939 #define TWI_TPR_TXPTR_Pos 0
    05940 #define TWI_TPR_TXPTR_Msk (0xffffffffu << TWI_TPR_TXPTR_Pos) /**< \brief (TWI_TPR) Transmit Counter Register */
    05941 #define TWI_TPR_TXPTR(value) ((TWI_TPR_TXPTR_Msk & ((value) << TWI_TPR_TXPTR_Pos)))
    05942 /* -------- TWI_TCR : (TWI Offset: 0x10C) Transmit Counter Register -------- */
    05943 #define TWI_TCR_TXCTR_Pos 0
    05944 #define TWI_TCR_TXCTR_Msk (0xffffu << TWI_TCR_TXCTR_Pos) /**< \brief (TWI_TCR) Transmit Counter Register */
    05945 #define TWI_TCR_TXCTR(value) ((TWI_TCR_TXCTR_Msk & ((value) << TWI_TCR_TXCTR_Pos)))
    05946 /* -------- TWI_RNPR : (TWI Offset: 0x110) Receive Next Pointer Register -------- */
    05947 #define TWI_RNPR_RXNPTR_Pos 0
    05948 #define TWI_RNPR_RXNPTR_Msk (0xffffffffu << TWI_RNPR_RXNPTR_Pos) /**< \brief (TWI_RNPR) Receive Next Pointer */
    05949 #define TWI_RNPR_RXNPTR(value) ((TWI_RNPR_RXNPTR_Msk & ((value) << TWI_RNPR_RXNPTR_Pos)))
    05950 /* -------- TWI_RNCR : (TWI Offset: 0x114) Receive Next Counter Register -------- */
    05951 #define TWI_RNCR_RXNCTR_Pos 0
    05952 #define TWI_RNCR_RXNCTR_Msk (0xffffu << TWI_RNCR_RXNCTR_Pos) /**< \brief (TWI_RNCR) Receive Next Counter */
    05953 #define TWI_RNCR_RXNCTR(value) ((TWI_RNCR_RXNCTR_Msk & ((value) << TWI_RNCR_RXNCTR_Pos)))
    05954 /* -------- TWI_TNPR : (TWI Offset: 0x118) Transmit Next Pointer Register -------- */
    05955 #define TWI_TNPR_TXNPTR_Pos 0
    05956 #define TWI_TNPR_TXNPTR_Msk (0xffffffffu << TWI_TNPR_TXNPTR_Pos) /**< \brief (TWI_TNPR) Transmit Next Pointer */
    05957 #define TWI_TNPR_TXNPTR(value) ((TWI_TNPR_TXNPTR_Msk & ((value) << TWI_TNPR_TXNPTR_Pos)))
    05958 /* -------- TWI_TNCR : (TWI Offset: 0x11C) Transmit Next Counter Register -------- */
    05959 #define TWI_TNCR_TXNCTR_Pos 0
    05960 #define TWI_TNCR_TXNCTR_Msk (0xffffu << TWI_TNCR_TXNCTR_Pos) /**< \brief (TWI_TNCR) Transmit Counter Next */
    05961 #define TWI_TNCR_TXNCTR(value) ((TWI_TNCR_TXNCTR_Msk & ((value) << TWI_TNCR_TXNCTR_Pos)))
    05962 /* -------- TWI_PTCR : (TWI Offset: 0x120) Transfer Control Register -------- */
    05963 #define TWI_PTCR_RXTEN (0x1u << 0) /**< \brief (TWI_PTCR) Receiver Transfer Enable */
    05964 #define TWI_PTCR_RXTDIS (0x1u << 1) /**< \brief (TWI_PTCR) Receiver Transfer Disable */
    05965 #define TWI_PTCR_TXTEN (0x1u << 8) /**< \brief (TWI_PTCR) Transmitter Transfer Enable */
    05966 #define TWI_PTCR_TXTDIS (0x1u << 9) /**< \brief (TWI_PTCR) Transmitter Transfer Disable */
    05967 /* -------- TWI_PTSR : (TWI Offset: 0x124) Transfer Status Register -------- */
    05968 #define TWI_PTSR_RXTEN (0x1u << 0) /**< \brief (TWI_PTSR) Receiver Transfer Enable */
    05969 #define TWI_PTSR_TXTEN (0x1u << 8) /**< \brief (TWI_PTSR) Transmitter Transfer Enable */
    05970
    05971 /*@}*/
    05972
    05973 /* ============================================================================= */
    05974 /**  SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */
    05975 /* ============================================================================= */
    05976 /** \addtogroup SAM3S8_UART Universal Asynchronous Receiver Transmitter */
    05977 /*@{*/
    05978
    05979 #ifndef __ASSEMBLY__
    05980 /** \brief Uart hardware registers */
    05981 typedef struct {
    05982   WoReg UART_CR;       /**< \brief (Uart Offset: 0x0000) Control Register */
    05983   RwReg UART_MR;       /**< \brief (Uart Offset: 0x0004) Mode Register */
    05984   WoReg UART_IER;      /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */
    05985   WoReg UART_IDR;      /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */
    05986   RoReg UART_IMR;      /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */
    05987   RoReg UART_SR;       /**< \brief (Uart Offset: 0x0014) Status Register */
    05988   RoReg UART_RHR;      /**< \brief (Uart Offset: 0x0018) Receive Holding Register */
    05989   WoReg UART_THR;      /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */
    05990   RwReg UART_BRGR;     /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */
    05991   RoReg Reserved1[55];
    05992   RwReg UART_RPR;      /**< \brief (Uart Offset: 0x100) Receive Pointer Register */
    05993   RwReg UART_RCR;      /**< \brief (Uart Offset: 0x104) Receive Counter Register */
    05994   RwReg UART_TPR;      /**< \brief (Uart Offset: 0x108) Transmit Pointer Register */
    05995   RwReg UART_TCR;      /**< \brief (Uart Offset: 0x10C) Transmit Counter Register */
    05996   RwReg UART_RNPR;     /**< \brief (Uart Offset: 0x110) Receive Next Pointer Register */
    05997   RwReg UART_RNCR;     /**< \brief (Uart Offset: 0x114) Receive Next Counter Register */
    05998   RwReg UART_TNPR;     /**< \brief (Uart Offset: 0x118) Transmit Next Pointer Register */
    05999   RwReg UART_TNCR;     /**< \brief (Uart Offset: 0x11C) Transmit Next Counter Register */
    06000   WoReg UART_PTCR;     /**< \brief (Uart Offset: 0x120) Transfer Control Register */
    06001   RoReg UART_PTSR;     /**< \brief (Uart Offset: 0x124) Transfer Status Register */
    06002 } Uart;
    06003 #endif /* __ASSEMBLY__ */
    06004 /* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */
    06005 #define UART_CR_RSTRX (0x1u << 2) /**< \brief (UART_CR) Reset Receiver */
    06006 #define UART_CR_RSTTX (0x1u << 3) /**< \brief (UART_CR) Reset Transmitter */
    06007 #define UART_CR_RXEN (0x1u << 4) /**< \brief (UART_CR) Receiver Enable */
    06008 #define UART_CR_RXDIS (0x1u << 5) /**< \brief (UART_CR) Receiver Disable */
    06009 #define UART_CR_TXEN (0x1u << 6) /**< \brief (UART_CR) Transmitter Enable */
    06010 #define UART_CR_TXDIS (0x1u << 7) /**< \brief (UART_CR) Transmitter Disable */
    06011 #define UART_CR_RSTSTA (0x1u << 8) /**< \brief (UART_CR) Reset Status Bits */
    06012 /* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */
    06013 #define UART_MR_PAR_Pos 9
    06014 #define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos) /**< \brief (UART_MR) Parity Type */
    06015 #define   UART_MR_PAR_EVEN (0x0u << 9) /**< \brief (UART_MR) Even parity */
    06016 #define   UART_MR_PAR_ODD (0x1u << 9) /**< \brief (UART_MR) Odd parity */
    06017 #define   UART_MR_PAR_SPACE (0x2u << 9) /**< \brief (UART_MR) Space: parity forced to 0 */
    06018 #define   UART_MR_PAR_MARK (0x3u << 9) /**< \brief (UART_MR) Mark: parity forced to 1 */
    06019 #define   UART_MR_PAR_NO (0x4u << 9) /**< \brief (UART_MR) No parity */
    06020 #define UART_MR_CHMODE_Pos 14
    06021 #define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos) /**< \brief (UART_MR) Channel Mode */
    06022 #define   UART_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (UART_MR) Normal Mode */
    06023 #define   UART_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (UART_MR) Automatic Echo */
    06024 #define   UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (UART_MR) Local Loopback */
    06025 #define   UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (UART_MR) Remote Loopback */
    06026 /* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */
    06027 #define UART_IER_RXRDY (0x1u << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */
    06028 #define UART_IER_TXRDY (0x1u << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */
    06029 #define UART_IER_ENDRX (0x1u << 3) /**< \brief (UART_IER) Enable End of Receive Transfer Interrupt */
    06030 #define UART_IER_ENDTX (0x1u << 4) /**< \brief (UART_IER) Enable End of Transmit Interrupt */
    06031 #define UART_IER_OVRE (0x1u << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */
    06032 #define UART_IER_FRAME (0x1u << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */
    06033 #define UART_IER_PARE (0x1u << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */
    06034 #define UART_IER_TXEMPTY (0x1u << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */
    06035 #define UART_IER_TXBUFE (0x1u << 11) /**< \brief (UART_IER) Enable Buffer Empty Interrupt */
    06036 #define UART_IER_RXBUFF (0x1u << 12) /**< \brief (UART_IER) Enable Buffer Full Interrupt */
    06037 /* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */
    06038 #define UART_IDR_RXRDY (0x1u << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */
    06039 #define UART_IDR_TXRDY (0x1u << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */
    06040 #define UART_IDR_ENDRX (0x1u << 3) /**< \brief (UART_IDR) Disable End of Receive Transfer Interrupt */
    06041 #define UART_IDR_ENDTX (0x1u << 4) /**< \brief (UART_IDR) Disable End of Transmit Interrupt */
    06042 #define UART_IDR_OVRE (0x1u << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */
    06043 #define UART_IDR_FRAME (0x1u << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */
    06044 #define UART_IDR_PARE (0x1u << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */
    06045 #define UART_IDR_TXEMPTY (0x1u << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */
    06046 #define UART_IDR_TXBUFE (0x1u << 11) /**< \brief (UART_IDR) Disable Buffer Empty Interrupt */
    06047 #define UART_IDR_RXBUFF (0x1u << 12) /**< \brief (UART_IDR) Disable Buffer Full Interrupt */
    06048 /* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */
    06049 #define UART_IMR_RXRDY (0x1u << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */
    06050 #define UART_IMR_TXRDY (0x1u << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */
    06051 #define UART_IMR_ENDRX (0x1u << 3) /**< \brief (UART_IMR) Mask End of Receive Transfer Interrupt */
    06052 #define UART_IMR_ENDTX (0x1u << 4) /**< \brief (UART_IMR) Mask End of Transmit Interrupt */
    06053 #define UART_IMR_OVRE (0x1u << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */
    06054 #define UART_IMR_FRAME (0x1u << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */
    06055 #define UART_IMR_PARE (0x1u << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */
    06056 #define UART_IMR_TXEMPTY (0x1u << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */
    06057 #define UART_IMR_TXBUFE (0x1u << 11) /**< \brief (UART_IMR) Mask TXBUFE Interrupt */
    06058 #define UART_IMR_RXBUFF (0x1u << 12) /**< \brief (UART_IMR) Mask RXBUFF Interrupt */
    06059 /* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */
    06060 #define UART_SR_RXRDY (0x1u << 0) /**< \brief (UART_SR) Receiver Ready */
    06061 #define UART_SR_TXRDY (0x1u << 1) /**< \brief (UART_SR) Transmitter Ready */
    06062 #define UART_SR_ENDRX (0x1u << 3) /**< \brief (UART_SR) End of Receiver Transfer */
    06063 #define UART_SR_ENDTX (0x1u << 4) /**< \brief (UART_SR) End of Transmitter Transfer */
    06064 #define UART_SR_OVRE (0x1u << 5) /**< \brief (UART_SR) Overrun Error */
    06065 #define UART_SR_FRAME (0x1u << 6) /**< \brief (UART_SR) Framing Error */
    06066 #define UART_SR_PARE (0x1u << 7) /**< \brief (UART_SR) Parity Error */
    06067 #define UART_SR_TXEMPTY (0x1u << 9) /**< \brief (UART_SR) Transmitter Empty */
    06068 #define UART_SR_TXBUFE (0x1u << 11) /**< \brief (UART_SR) Transmission Buffer Empty */
    06069 #define UART_SR_RXBUFF (0x1u << 12) /**< \brief (UART_SR) Receive Buffer Full */
    06070 /* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */
    06071 #define UART_RHR_RXCHR_Pos 0
    06072 #define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos) /**< \brief (UART_RHR) Received Character */
    06073 /* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */
    06074 #define UART_THR_TXCHR_Pos 0
    06075 #define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos) /**< \brief (UART_THR) Character to be Transmitted */
    06076 #define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos)))
    06077 /* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */
    06078 #define UART_BRGR_CD_Pos 0
    06079 #define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos) /**< \brief (UART_BRGR) Clock Divisor */
    06080 #define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos)))
    06081 /* -------- UART_RPR : (UART Offset: 0x100) Receive Pointer Register -------- */
    06082 #define UART_RPR_RXPTR_Pos 0
    06083 #define UART_RPR_RXPTR_Msk (0xffffffffu << UART_RPR_RXPTR_Pos) /**< \brief (UART_RPR) Receive Pointer Register */
    06084 #define UART_RPR_RXPTR(value) ((UART_RPR_RXPTR_Msk & ((value) << UART_RPR_RXPTR_Pos)))
    06085 /* -------- UART_RCR : (UART Offset: 0x104) Receive Counter Register -------- */
    06086 #define UART_RCR_RXCTR_Pos 0
    06087 #define UART_RCR_RXCTR_Msk (0xffffu << UART_RCR_RXCTR_Pos) /**< \brief (UART_RCR) Receive Counter Register */
    06088 #define UART_RCR_RXCTR(value) ((UART_RCR_RXCTR_Msk & ((value) << UART_RCR_RXCTR_Pos)))
    06089 /* -------- UART_TPR : (UART Offset: 0x108) Transmit Pointer Register -------- */
    06090 #define UART_TPR_TXPTR_Pos 0
    06091 #define UART_TPR_TXPTR_Msk (0xffffffffu << UART_TPR_TXPTR_Pos) /**< \brief (UART_TPR) Transmit Counter Register */
    06092 #define UART_TPR_TXPTR(value) ((UART_TPR_TXPTR_Msk & ((value) << UART_TPR_TXPTR_Pos)))
    06093 /* -------- UART_TCR : (UART Offset: 0x10C) Transmit Counter Register -------- */
    06094 #define UART_TCR_TXCTR_Pos 0
    06095 #define UART_TCR_TXCTR_Msk (0xffffu << UART_TCR_TXCTR_Pos) /**< \brief (UART_TCR) Transmit Counter Register */
    06096 #define UART_TCR_TXCTR(value) ((UART_TCR_TXCTR_Msk & ((value) << UART_TCR_TXCTR_Pos)))
    06097 /* -------- UART_RNPR : (UART Offset: 0x110) Receive Next Pointer Register -------- */
    06098 #define UART_RNPR_RXNPTR_Pos 0
    06099 #define UART_RNPR_RXNPTR_Msk (0xffffffffu << UART_RNPR_RXNPTR_Pos) /**< \brief (UART_RNPR) Receive Next Pointer */
    06100 #define UART_RNPR_RXNPTR(value) ((UART_RNPR_RXNPTR_Msk & ((value) << UART_RNPR_RXNPTR_Pos)))
    06101 /* -------- UART_RNCR : (UART Offset: 0x114) Receive Next Counter Register -------- */
    06102 #define UART_RNCR_RXNCTR_Pos 0
    06103 #define UART_RNCR_RXNCTR_Msk (0xffffu << UART_RNCR_RXNCTR_Pos) /**< \brief (UART_RNCR) Receive Next Counter */
    06104 #define UART_RNCR_RXNCTR(value) ((UART_RNCR_RXNCTR_Msk & ((value) << UART_RNCR_RXNCTR_Pos)))
    06105 /* -------- UART_TNPR : (UART Offset: 0x118) Transmit Next Pointer Register -------- */
    06106 #define UART_TNPR_TXNPTR_Pos 0
    06107 #define UART_TNPR_TXNPTR_Msk (0xffffffffu << UART_TNPR_TXNPTR_Pos) /**< \brief (UART_TNPR) Transmit Next Pointer */
    06108 #define UART_TNPR_TXNPTR(value) ((UART_TNPR_TXNPTR_Msk & ((value) << UART_TNPR_TXNPTR_Pos)))
    06109 /* -------- UART_TNCR : (UART Offset: 0x11C) Transmit Next Counter Register -------- */
    06110 #define UART_TNCR_TXNCTR_Pos 0
    06111 #define UART_TNCR_TXNCTR_Msk (0xffffu << UART_TNCR_TXNCTR_Pos) /**< \brief (UART_TNCR) Transmit Counter Next */
    06112 #define UART_TNCR_TXNCTR(value) ((UART_TNCR_TXNCTR_Msk & ((value) << UART_TNCR_TXNCTR_Pos)))
    06113 /* -------- UART_PTCR : (UART Offset: 0x120) Transfer Control Register -------- */
    06114 #define UART_PTCR_RXTEN (0x1u << 0) /**< \brief (UART_PTCR) Receiver Transfer Enable */
    06115 #define UART_PTCR_RXTDIS (0x1u << 1) /**< \brief (UART_PTCR) Receiver Transfer Disable */
    06116 #define UART_PTCR_TXTEN (0x1u << 8) /**< \brief (UART_PTCR) Transmitter Transfer Enable */
    06117 #define UART_PTCR_TXTDIS (0x1u << 9) /**< \brief (UART_PTCR) Transmitter Transfer Disable */
    06118 /* -------- UART_PTSR : (UART Offset: 0x124) Transfer Status Register -------- */
    06119 #define UART_PTSR_RXTEN (0x1u << 0) /**< \brief (UART_PTSR) Receiver Transfer Enable */
    06120 #define UART_PTSR_TXTEN (0x1u << 8) /**< \brief (UART_PTSR) Transmitter Transfer Enable */
    06121
    06122 /*@}*/
    06123
    06124 /* ============================================================================= */
    06125 /**  SOFTWARE API DEFINITION FOR USB Device Port */
    06126 /* ============================================================================= */
    06127 /** \addtogroup SAM3S8_UDP USB Device Port */
    06128 /*@{*/
    06129
    06130 #ifndef __ASSEMBLY__
    06131 /** \brief Udp hardware registers */
    06132 typedef struct {
    06133   RoReg UDP_FRM_NUM;  /**< \brief (Udp Offset: 0x000) Frame Number Register */
    06134   RwReg UDP_GLB_STAT; /**< \brief (Udp Offset: 0x004) Global State Register */
    06135   RwReg UDP_FADDR;    /**< \brief (Udp Offset: 0x008) Function Address Register */
    06136   RoReg Reserved1[1];
    06137   WoReg UDP_IER;      /**< \brief (Udp Offset: 0x010) Interrupt Enable Register */
    06138   WoReg UDP_IDR;      /**< \brief (Udp Offset: 0x014) Interrupt Disable Register */
    06139   RoReg UDP_IMR;      /**< \brief (Udp Offset: 0x018) Interrupt Mask Register */
    06140   RoReg UDP_ISR;      /**< \brief (Udp Offset: 0x01C) Interrupt Status Register */
    06141   WoReg UDP_ICR;      /**< \brief (Udp Offset: 0x020) Interrupt Clear Register */
    06142   RoReg Reserved2[1];
    06143   RwReg UDP_RST_EP;   /**< \brief (Udp Offset: 0x028) Reset Endpoint Register */
    06144   RoReg Reserved3[1];
    06145   RwReg UDP_CSR[8];   /**< \brief (Udp Offset: 0x030) Endpoint Control and Status Register */
    06146   RwReg UDP_FDR[8];   /**< \brief (Udp Offset: 0x050) Endpoint FIFO Data Register */
    06147   RoReg Reserved4[1];
    06148   RwReg UDP_TXVC;     /**< \brief (Udp Offset: 0x074) Transceiver Control Register */
    06149 } Udp;
    06150 #endif /* __ASSEMBLY__ */
    06151 /* -------- UDP_FRM_NUM : (UDP Offset: 0x000) Frame Number Register -------- */
    06152 #define UDP_FRM_NUM_FRM_NUM_Pos 0
    06153 #define UDP_FRM_NUM_FRM_NUM_Msk (0x7ffu << UDP_FRM_NUM_FRM_NUM_Pos) /**< \brief (UDP_FRM_NUM) Frame Number as Defined in the Packet Field Formats */
    06154 #define UDP_FRM_NUM_FRM_ERR (0x1u << 16) /**< \brief (UDP_FRM_NUM) Frame Error */
    06155 #define UDP_FRM_NUM_FRM_OK (0x1u << 17) /**< \brief (UDP_FRM_NUM) Frame OK */
    06156 /* -------- UDP_GLB_STAT : (UDP Offset: 0x004) Global State Register -------- */
    06157 #define UDP_GLB_STAT_FADDEN (0x1u << 0) /**< \brief (UDP_GLB_STAT) Function Address Enable */
    06158 #define UDP_GLB_STAT_CONFG (0x1u << 1) /**< \brief (UDP_GLB_STAT) Configured */
    06159 #define UDP_GLB_STAT_ESR (0x1u << 2) /**< \brief (UDP_GLB_STAT) Enable Send Resume */
    06160 #define UDP_GLB_STAT_RSMINPR (0x1u << 3) /**< \brief (UDP_GLB_STAT)  */
    06161 #define UDP_GLB_STAT_RMWUPE (0x1u << 4) /**< \brief (UDP_GLB_STAT) Remote Wake Up Enable */
    06162 /* -------- UDP_FADDR : (UDP Offset: 0x008) Function Address Register -------- */
    06163 #define UDP_FADDR_FADD_Pos 0
    06164 #define UDP_FADDR_FADD_Msk (0x7fu << UDP_FADDR_FADD_Pos) /**< \brief (UDP_FADDR) Function Address Value */
    06165 #define UDP_FADDR_FADD(value) ((UDP_FADDR_FADD_Msk & ((value) << UDP_FADDR_FADD_Pos)))
    06166 #define UDP_FADDR_FEN (0x1u << 8) /**< \brief (UDP_FADDR) Function Enable */
    06167 /* -------- UDP_IER : (UDP Offset: 0x010) Interrupt Enable Register -------- */
    06168 #define UDP_IER_EP0INT (0x1u << 0) /**< \brief (UDP_IER) Enable Endpoint 0 Interrupt */
    06169 #define UDP_IER_EP1INT (0x1u << 1) /**< \brief (UDP_IER) Enable Endpoint 1 Interrupt */
    06170 #define UDP_IER_EP2INT (0x1u << 2) /**< \brief (UDP_IER) Enable Endpoint 2Interrupt */
    06171 #define UDP_IER_EP3INT (0x1u << 3) /**< \brief (UDP_IER) Enable Endpoint 3 Interrupt */
    06172 #define UDP_IER_EP4INT (0x1u << 4) /**< \brief (UDP_IER) Enable Endpoint 4 Interrupt */
    06173 #define UDP_IER_EP5INT (0x1u << 5) /**< \brief (UDP_IER) Enable Endpoint 5 Interrupt */
    06174 #define UDP_IER_EP6INT (0x1u << 6) /**< \brief (UDP_IER) Enable Endpoint 6 Interrupt */
    06175 #define UDP_IER_EP7INT (0x1u << 7) /**< \brief (UDP_IER) Enable Endpoint 7 Interrupt */
    06176 #define UDP_IER_RXSUSP (0x1u << 8) /**< \brief (UDP_IER) Enable UDP Suspend Interrupt */
    06177 #define UDP_IER_RXRSM (0x1u << 9) /**< \brief (UDP_IER) Enable UDP Resume Interrupt */
    06178 #define UDP_IER_EXTRSM (0x1u << 10) /**< \brief (UDP_IER)  */
    06179 #define UDP_IER_SOFINT (0x1u << 11) /**< \brief (UDP_IER) Enable Start Of Frame Interrupt */
    06180 #define UDP_IER_WAKEUP (0x1u << 13) /**< \brief (UDP_IER) Enable UDP bus Wakeup Interrupt */
    06181 /* -------- UDP_IDR : (UDP Offset: 0x014) Interrupt Disable Register -------- */
    06182 #define UDP_IDR_EP0INT (0x1u << 0) /**< \brief (UDP_IDR) Disable Endpoint 0 Interrupt */
    06183 #define UDP_IDR_EP1INT (0x1u << 1) /**< \brief (UDP_IDR) Disable Endpoint 1 Interrupt */
    06184 #define UDP_IDR_EP2INT (0x1u << 2) /**< \brief (UDP_IDR) Disable Endpoint 2 Interrupt */
    06185 #define UDP_IDR_EP3INT (0x1u << 3) /**< \brief (UDP_IDR) Disable Endpoint 3 Interrupt */
    06186 #define UDP_IDR_EP4INT (0x1u << 4) /**< \brief (UDP_IDR) Disable Endpoint 4 Interrupt */
    06187 #define UDP_IDR_EP5INT (0x1u << 5) /**< \brief (UDP_IDR) Disable Endpoint 5 Interrupt */
    06188 #define UDP_IDR_EP6INT (0x1u << 6) /**< \brief (UDP_IDR) Disable Endpoint 6 Interrupt */
    06189 #define UDP_IDR_EP7INT (0x1u << 7) /**< \brief (UDP_IDR) Disable Endpoint 7 Interrupt */
    06190 #define UDP_IDR_RXSUSP (0x1u << 8) /**< \brief (UDP_IDR) Disable UDP Suspend Interrupt */
    06191 #define UDP_IDR_RXRSM (0x1u << 9) /**< \brief (UDP_IDR) Disable UDP Resume Interrupt */
    06192 #define UDP_IDR_EXTRSM (0x1u << 10) /**< \brief (UDP_IDR)  */
    06193 #define UDP_IDR_SOFINT (0x1u << 11) /**< \brief (UDP_IDR) Disable Start Of Frame Interrupt */
    06194 #define UDP_IDR_WAKEUP (0x1u << 13) /**< \brief (UDP_IDR) Disable USB Bus Interrupt */
    06195 /* -------- UDP_IMR : (UDP Offset: 0x018) Interrupt Mask Register -------- */
    06196 #define UDP_IMR_EP0INT (0x1u << 0) /**< \brief (UDP_IMR) Mask Endpoint 0 Interrupt */
    06197 #define UDP_IMR_EP1INT (0x1u << 1) /**< \brief (UDP_IMR) Mask Endpoint 1 Interrupt */
    06198 #define UDP_IMR_EP2INT (0x1u << 2) /**< \brief (UDP_IMR) Mask Endpoint 2 Interrupt */
    06199 #define UDP_IMR_EP3INT (0x1u << 3) /**< \brief (UDP_IMR) Mask Endpoint 3 Interrupt */
    06200 #define UDP_IMR_EP4INT (0x1u << 4) /**< \brief (UDP_IMR) Mask Endpoint 4 Interrupt */
    06201 #define UDP_IMR_EP5INT (0x1u << 5) /**< \brief (UDP_IMR) Mask Endpoint 5 Interrupt */
    06202 #define UDP_IMR_EP6INT (0x1u << 6) /**< \brief (UDP_IMR) Mask Endpoint 6 Interrupt */
    06203 #define UDP_IMR_EP7INT (0x1u << 7) /**< \brief (UDP_IMR) Mask Endpoint 7 Interrupt */
    06204 #define UDP_IMR_RXSUSP (0x1u << 8) /**< \brief (UDP_IMR) Mask UDP Suspend Interrupt */
    06205 #define UDP_IMR_RXRSM (0x1u << 9) /**< \brief (UDP_IMR) Mask UDP Resume Interrupt. */
    06206 #define UDP_IMR_EXTRSM (0x1u << 10) /**< \brief (UDP_IMR)  */
    06207 #define UDP_IMR_SOFINT (0x1u << 11) /**< \brief (UDP_IMR) Mask Start Of Frame Interrupt */
    06208 #define UDP_IMR_BIT12 (0x1u << 12) /**< \brief (UDP_IMR) UDP_IMR Bit 12 */
    06209 #define UDP_IMR_WAKEUP (0x1u << 13) /**< \brief (UDP_IMR) USB Bus WAKEUP Interrupt */
    06210 /* -------- UDP_ISR : (UDP Offset: 0x01C) Interrupt Status Register -------- */
    06211 #define UDP_ISR_EP0INT (0x1u << 0) /**< \brief (UDP_ISR) Endpoint 0 Interrupt Status */
    06212 #define UDP_ISR_EP1INT (0x1u << 1) /**< \brief (UDP_ISR) Endpoint 1 Interrupt Status */
    06213 #define UDP_ISR_EP2INT (0x1u << 2) /**< \brief (UDP_ISR) Endpoint 2 Interrupt Status */
    06214 #define UDP_ISR_EP3INT (0x1u << 3) /**< \brief (UDP_ISR) Endpoint 3 Interrupt Status */
    06215 #define UDP_ISR_EP4INT (0x1u << 4) /**< \brief (UDP_ISR) Endpoint 4 Interrupt Status */
    06216 #define UDP_ISR_EP5INT (0x1u << 5) /**< \brief (UDP_ISR) Endpoint 5 Interrupt Status */
    06217 #define UDP_ISR_EP6INT (0x1u << 6) /**< \brief (UDP_ISR) Endpoint 6 Interrupt Status */
    06218 #define UDP_ISR_EP7INT (0x1u << 7) /**< \brief (UDP_ISR) Endpoint 7Interrupt Status */
    06219 #define UDP_ISR_RXSUSP (0x1u << 8) /**< \brief (UDP_ISR) UDP Suspend Interrupt Status */
    06220 #define UDP_ISR_RXRSM (0x1u << 9) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */
    06221 #define UDP_ISR_EXTRSM (0x1u << 10) /**< \brief (UDP_ISR)  */
    06222 #define UDP_ISR_SOFINT (0x1u << 11) /**< \brief (UDP_ISR) Start of Frame Interrupt Status */
    06223 #define UDP_ISR_ENDBUSRES (0x1u << 12) /**< \brief (UDP_ISR) End of BUS Reset Interrupt Status */
    06224 #define UDP_ISR_WAKEUP (0x1u << 13) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */
    06225 /* -------- UDP_ICR : (UDP Offset: 0x020) Interrupt Clear Register -------- */
    06226 #define UDP_ICR_RXSUSP (0x1u << 8) /**< \brief (UDP_ICR) Clear UDP Suspend Interrupt */
    06227 #define UDP_ICR_RXRSM (0x1u << 9) /**< \brief (UDP_ICR) Clear UDP Resume Interrupt */
    06228 #define UDP_ICR_EXTRSM (0x1u << 10) /**< \brief (UDP_ICR)  */
    06229 #define UDP_ICR_SOFINT (0x1u << 11) /**< \brief (UDP_ICR) Clear Start Of Frame Interrupt */
    06230 #define UDP_ICR_ENDBUSRES (0x1u << 12) /**< \brief (UDP_ICR) Clear End of Bus Reset Interrupt */
    06231 #define UDP_ICR_WAKEUP (0x1u << 13) /**< \brief (UDP_ICR) Clear Wakeup Interrupt */
    06232 /* -------- UDP_RST_EP : (UDP Offset: 0x028) Reset Endpoint Register -------- */
    06233 #define UDP_RST_EP_EP0 (0x1u << 0) /**< \brief (UDP_RST_EP) Reset Endpoint 0 */
    06234 #define UDP_RST_EP_EP1 (0x1u << 1) /**< \brief (UDP_RST_EP) Reset Endpoint 1 */
    06235 #define UDP_RST_EP_EP2 (0x1u << 2) /**< \brief (UDP_RST_EP) Reset Endpoint 2 */
    06236 #define UDP_RST_EP_EP3 (0x1u << 3) /**< \brief (UDP_RST_EP) Reset Endpoint 3 */
    06237 #define UDP_RST_EP_EP4 (0x1u << 4) /**< \brief (UDP_RST_EP) Reset Endpoint 4 */
    06238 #define UDP_RST_EP_EP5 (0x1u << 5) /**< \brief (UDP_RST_EP) Reset Endpoint 5 */
    06239 #define UDP_RST_EP_EP6 (0x1u << 6) /**< \brief (UDP_RST_EP) Reset Endpoint 6 */
    06240 #define UDP_RST_EP_EP7 (0x1u << 7) /**< \brief (UDP_RST_EP) Reset Endpoint 7 */
    06241 /* -------- UDP_CSR[8] : (UDP Offset: 0x030) Endpoint Control and Status Register -------- */
    06242 #define UDP_CSR_TXCOMP (0x1u << 0) /**< \brief (UDP_CSR[8]) Generates an IN Packet with Data Previously Written in the DPR */
    06243 #define UDP_CSR_RX_DATA_BK0 (0x1u << 1) /**< \brief (UDP_CSR[8]) Receive Data Bank 0 */
    06244 #define UDP_CSR_RXSETUP (0x1u << 2) /**< \brief (UDP_CSR[8]) Received Setup */
    06245 #define UDP_CSR_STALLSENT (0x1u << 3) /**< \brief (UDP_CSR[8]) Stall Sent (Control, Bulk Interrupt Endpoints)/ISOERROR (Isochronous Endpoints) */
    06246 #define UDP_CSR_ISOERROR (0x1u << 3) /**< \brief (UDP_CSR[8]) Stall Sent (Control, Bulk Interrupt Endpoints)/ISOERROR (Isochronous Endpoints) */
    06247 #define UDP_CSR_TXPKTRDY (0x1u << 4) /**< \brief (UDP_CSR[8]) Transmit Packet Ready */
    06248 #define UDP_CSR_FORCESTALL (0x1u << 5) /**< \brief (UDP_CSR[8]) Force Stall (used by Control, Bulk and Isochronous Endpoints) */
    06249 #define UDP_CSR_RX_DATA_BK1 (0x1u << 6) /**< \brief (UDP_CSR[8]) Receive Data Bank 1 (only used by endpoints with ping-pong attributes) */
    06250 #define UDP_CSR_DIR (0x1u << 7) /**< \brief (UDP_CSR[8]) Transfer Direction (only available for control endpoints) */
    06251 #define UDP_CSR_EPTYPE_Pos 8
    06252 #define UDP_CSR_EPTYPE_Msk (0x7u << UDP_CSR_EPTYPE_Pos) /**< \brief (UDP_CSR[8]) Endpoint Type */
    06253 #define   UDP_CSR_EPTYPE_CTRL (0x0u << 8) /**< \brief (UDP_CSR[8]) Control */
    06254 #define   UDP_CSR_EPTYPE_ISO_OUT (0x1u << 8) /**< \brief (UDP_CSR[8]) Isochronous OUT */
    06255 #define   UDP_CSR_EPTYPE_BULK_OUT (0x2u << 8) /**< \brief (UDP_CSR[8]) Bulk OUT */
    06256 #define   UDP_CSR_EPTYPE_INT_OUT (0x3u << 8) /**< \brief (UDP_CSR[8]) Interrupt OUT */
    06257 #define   UDP_CSR_EPTYPE_ISO_IN (0x5u << 8) /**< \brief (UDP_CSR[8]) Isochronous IN */
    06258 #define   UDP_CSR_EPTYPE_BULK_IN (0x6u << 8) /**< \brief (UDP_CSR[8]) Bulk IN */
    06259 #define   UDP_CSR_EPTYPE_INT_IN (0x7u << 8) /**< \brief (UDP_CSR[8]) Interrupt IN */
    06260 #define UDP_CSR_DTGLE (0x1u << 11) /**< \brief (UDP_CSR[8]) Data Toggle */
    06261 #define UDP_CSR_EPEDS (0x1u << 15) /**< \brief (UDP_CSR[8]) Endpoint Enable Disable */
    06262 #define UDP_CSR_RXBYTECNT_Pos 16
    06263 #define UDP_CSR_RXBYTECNT_Msk (0x7ffu << UDP_CSR_RXBYTECNT_Pos) /**< \brief (UDP_CSR[8]) Number of Bytes Available in the FIFO */
    06264 #define UDP_CSR_RXBYTECNT(value) ((UDP_CSR_RXBYTECNT_Msk & ((value) << UDP_CSR_RXBYTECNT_Pos)))
    06265 /* -------- UDP_FDR[8] : (UDP Offset: 0x050) Endpoint FIFO Data Register -------- */
    06266 #define UDP_FDR_FIFO_DATA_Pos 0
    06267 #define UDP_FDR_FIFO_DATA_Msk (0xffu << UDP_FDR_FIFO_DATA_Pos) /**< \brief (UDP_FDR[8]) FIFO Data Value */
    06268 #define UDP_FDR_FIFO_DATA(value) ((UDP_FDR_FIFO_DATA_Msk & ((value) << UDP_FDR_FIFO_DATA_Pos)))
    06269 /* -------- UDP_TXVC : (UDP Offset: 0x074) Transceiver Control Register -------- */
    06270 #define UDP_TXVC_TXVDIS (0x1u << 8) /**< \brief (UDP_TXVC) Transceiver Disable */
    06271 #define UDP_TXVC_PUON (0x1u << 9) /**< \brief (UDP_TXVC) Pullup On */
    06272
    06273 /*@}*/
    06274
    06275 /* ============================================================================= */
    06276 /**  SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */
    06277 /* ============================================================================= */
    06278 /** \addtogroup SAM3S8_USART Universal Synchronous Asynchronous Receiver Transmitter */
    06279 /*@{*/
    06280
    06281 #ifndef __ASSEMBLY__
    06282 /** \brief Usart hardware registers */
    06283 typedef struct {
    06284   WoReg US_CR;         /**< \brief (Usart Offset: 0x0000) Control Register */
    06285   RwReg US_MR;         /**< \brief (Usart Offset: 0x0004) Mode Register */
    06286   WoReg US_IER;        /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */
    06287   WoReg US_IDR;        /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */
    06288   RoReg US_IMR;        /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */
    06289   RoReg US_CSR;        /**< \brief (Usart Offset: 0x0014) Channel Status Register */
    06290   RoReg US_RHR;        /**< \brief (Usart Offset: 0x0018) Receiver Holding Register */
    06291   WoReg US_THR;        /**< \brief (Usart Offset: 0x001C) Transmitter Holding Register */
    06292   RwReg US_BRGR;       /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */
    06293   RwReg US_RTOR;       /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */
    06294   RwReg US_TTGR;       /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */
    06295   RoReg Reserved1[5];
    06296   RwReg US_FIDI;       /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */
    06297   RoReg US_NER;        /**< \brief (Usart Offset: 0x0044) Number of Errors Register */
    06298   RoReg Reserved2[1];
    06299   RwReg US_IF;         /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */
    06300   RwReg US_MAN;        /**< \brief (Usart Offset: 0x0050) Manchester Encoder Decoder Register */
    06301   RoReg Reserved3[36];
    06302   RwReg US_WPMR;       /**< \brief (Usart Offset: 0xE4) Write Protect Mode Register */
    06303   RoReg US_WPSR;       /**< \brief (Usart Offset: 0xE8) Write Protect Status Register */
    06304   RoReg Reserved4[4];
    06305   RoReg US_VERSION;    /**< \brief (Usart Offset: 0xFC) Version Register */
    06306   RwReg US_RPR;        /**< \brief (Usart Offset: 0x100) Receive Pointer Register */
    06307   RwReg US_RCR;        /**< \brief (Usart Offset: 0x104) Receive Counter Register */
    06308   RwReg US_TPR;        /**< \brief (Usart Offset: 0x108) Transmit Pointer Register */
    06309   RwReg US_TCR;        /**< \brief (Usart Offset: 0x10C) Transmit Counter Register */
    06310   RwReg US_RNPR;       /**< \brief (Usart Offset: 0x110) Receive Next Pointer Register */
    06311   RwReg US_RNCR;       /**< \brief (Usart Offset: 0x114) Receive Next Counter Register */
    06312   RwReg US_TNPR;       /**< \brief (Usart Offset: 0x118) Transmit Next Pointer Register */
    06313   RwReg US_TNCR;       /**< \brief (Usart Offset: 0x11C) Transmit Next Counter Register */
    06314   WoReg US_PTCR;       /**< \brief (Usart Offset: 0x120) Transfer Control Register */
    06315   RoReg US_PTSR;       /**< \brief (Usart Offset: 0x124) Transfer Status Register */
    06316 } Usart;
    06317 #endif /* __ASSEMBLY__ */
    06318 /* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */
    06319 #define US_CR_RSTRX (0x1u << 2) /**< \brief (US_CR) Reset Receiver */
    06320 #define US_CR_RSTTX (0x1u << 3) /**< \brief (US_CR) Reset Transmitter */
    06321 #define US_CR_RXEN (0x1u << 4) /**< \brief (US_CR) Receiver Enable */
    06322 #define US_CR_RXDIS (0x1u << 5) /**< \brief (US_CR) Receiver Disable */
    06323 #define US_CR_TXEN (0x1u << 6) /**< \brief (US_CR) Transmitter Enable */
    06324 #define US_CR_TXDIS (0x1u << 7) /**< \brief (US_CR) Transmitter Disable */
    06325 #define US_CR_RSTSTA (0x1u << 8) /**< \brief (US_CR) Reset Status Bits */
    06326 #define US_CR_STTBRK (0x1u << 9) /**< \brief (US_CR) Start Break */
    06327 #define US_CR_STPBRK (0x1u << 10) /**< \brief (US_CR) Stop Break */
    06328 #define US_CR_STTTO (0x1u << 11) /**< \brief (US_CR) Start Time-out */
    06329 #define US_CR_SENDA (0x1u << 12) /**< \brief (US_CR) Send Address */
    06330 #define US_CR_RSTIT (0x1u << 13) /**< \brief (US_CR) Reset Iterations */
    06331 #define US_CR_RSTNACK (0x1u << 14) /**< \brief (US_CR) Reset Non Acknowledge */
    06332 #define US_CR_RETTO (0x1u << 15) /**< \brief (US_CR) Rearm Time-out */
    06333 #define US_CR_DTREN (0x1u << 16) /**< \brief (US_CR) Data Terminal Ready Enable */
    06334 #define US_CR_DTRDIS (0x1u << 17) /**< \brief (US_CR) Data Terminal Ready Disable */
    06335 #define US_CR_RTSEN (0x1u << 18) /**< \brief (US_CR) Request to Send Enable */
    06336 #define US_CR_FCS (0x1u << 18) /**< \brief (US_CR) Force SPI Chip Select */
    06337 #define US_CR_RTSDIS (0x1u << 19) /**< \brief (US_CR) Request to Send Disable */
    06338 #define US_CR_RCS (0x1u << 19) /**< \brief (US_CR) Release SPI Chip Select */
    06339 /* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */
    06340 #define US_MR_USART_MODE_Pos 0
    06341 #define US_MR_USART_MODE_Msk (0xfu << US_MR_USART_MODE_Pos) /**< \brief (US_MR)  */
    06342 #define   US_MR_USART_MODE_NORMAL (0x0u << 0) /**< \brief (US_MR) Normal mode */
    06343 #define   US_MR_USART_MODE_RS485 (0x1u << 0) /**< \brief (US_MR) RS485 */
    06344 #define   US_MR_USART_MODE_HW_HANDSHAKING (0x2u << 0) /**< \brief (US_MR) Hardware Handshaking */
    06345 #define   US_MR_USART_MODE_MODEM (0x3u << 0) /**< \brief (US_MR) Modem */
    06346 #define   US_MR_USART_MODE_IS07816_T_0 (0x4u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 0 */
    06347 #define   US_MR_USART_MODE_IS07816_T_1 (0x6u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 1 */
    06348 #define   US_MR_USART_MODE_IRDA (0x8u << 0) /**< \brief (US_MR) IrDA */
    06349 #define   US_MR_USART_MODE_SPI_MASTER (0xEu << 0) /**< \brief (US_MR) SPI Master */
    06350 #define   US_MR_USART_MODE_SPI_SLAVE (0xFu << 0) /**< \brief (US_MR) SPI Slave */
    06351 #define US_MR_USCLKS_Pos 4
    06352 #define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos) /**< \brief (US_MR) Clock Selection */
    06353 #define   US_MR_USCLKS_MCK (0x0u << 4) /**< \brief (US_MR) Master Clock MCK is selected */
    06354 #define   US_MR_USCLKS_DIV (0x1u << 4) /**< \brief (US_MR) Internal Clock Divided MCK/DIV (DIV=8) is selected */
    06355 #define   US_MR_USCLKS_SCK (0x3u << 4) /**< \brief (US_MR) Serial Clock SLK is selected */
    06356 #define US_MR_CHRL_Pos 6
    06357 #define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos) /**< \brief (US_MR) Character Length. */
    06358 #define   US_MR_CHRL_5_BIT (0x0u << 6) /**< \brief (US_MR) Character length is 5 bits */
    06359 #define   US_MR_CHRL_6_BIT (0x1u << 6) /**< \brief (US_MR) Character length is 6 bits */
    06360 #define   US_MR_CHRL_7_BIT (0x2u << 6) /**< \brief (US_MR) Character length is 7 bits */
    06361 #define   US_MR_CHRL_8_BIT (0x3u << 6) /**< \brief (US_MR) Character length is 8 bits */
    06362 #define US_MR_SYNC (0x1u << 8) /**< \brief (US_MR) Synchronous Mode Select */
    06363 #define US_MR_CPHA (0x1u << 8) /**< \brief (US_MR) SPI Clock Phase */
    06364 #define US_MR_PAR_Pos 9
    06365 #define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos) /**< \brief (US_MR) Parity Type */
    06366 #define   US_MR_PAR_EVEN (0x0u << 9) /**< \brief (US_MR) Even parity */
    06367 #define   US_MR_PAR_ODD (0x1u << 9) /**< \brief (US_MR) Odd parity */
    06368 #define   US_MR_PAR_SPACE (0x2u << 9) /**< \brief (US_MR) Parity forced to 0 (Space) */
    06369 #define   US_MR_PAR_MARK (0x3u << 9) /**< \brief (US_MR) Parity forced to 1 (Mark) */
    06370 #define   US_MR_PAR_NO (0x4u << 9) /**< \brief (US_MR) No parity */
    06371 #define   US_MR_PAR_MULTIDROP (0x6u << 9) /**< \brief (US_MR) Multidrop mode */
    06372 #define US_MR_NBSTOP_Pos 12
    06373 #define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos) /**< \brief (US_MR) Number of Stop Bits */
    06374 #define   US_MR_NBSTOP_1_BIT (0x0u << 12) /**< \brief (US_MR) 1 stop bit */
    06375 #define   US_MR_NBSTOP_1_5_BIT (0x1u << 12) /**< \brief (US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) */
    06376 #define   US_MR_NBSTOP_2_BIT (0x2u << 12) /**< \brief (US_MR) 2 stop bits */
    06377 #define US_MR_CHMODE_Pos 14
    06378 #define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos) /**< \brief (US_MR) Channel Mode */
    06379 #define   US_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (US_MR) Normal Mode */
    06380 #define   US_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. */
    06381 #define   US_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. */
    06382 #define   US_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. */
    06383 #define US_MR_MSBF (0x1u << 16) /**< \brief (US_MR) Bit Order */
    06384 #define US_MR_CPOL (0x1u << 16) /**< \brief (US_MR) SPI Clock Polarity */
    06385 #define US_MR_MODE9 (0x1u << 17) /**< \brief (US_MR) 9-bit Character Length */
    06386 #define US_MR_CLKO (0x1u << 18) /**< \brief (US_MR) Clock Output Select */
    06387 #define US_MR_OVER (0x1u << 19) /**< \brief (US_MR) Oversampling Mode */
    06388 #define US_MR_INACK (0x1u << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */
    06389 #define US_MR_DSNACK (0x1u << 21) /**< \brief (US_MR) Disable Successive NACK */
    06390 #define US_MR_VAR_SYNC (0x1u << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */
    06391 #define US_MR_INVDATA (0x1u << 23) /**< \brief (US_MR) INverted Data */
    06392 #define US_MR_MAX_ITERATION_Pos 24
    06393 #define US_MR_MAX_ITERATION_Msk (0x7u << US_MR_MAX_ITERATION_Pos) /**< \brief (US_MR)  */
    06394 #define US_MR_MAX_ITERATION(value) ((US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos)))
    06395 #define US_MR_FILTER (0x1u << 28) /**< \brief (US_MR) Infrared Receive Line Filter */
    06396 #define US_MR_MAN (0x1u << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */
    06397 #define US_MR_MODSYNC (0x1u << 30) /**< \brief (US_MR) Manchester Synchronization Mode */
    06398 #define US_MR_ONEBIT (0x1u << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */
    06399 /* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */
    06400 #define US_IER_RXRDY (0x1u << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */
    06401 #define US_IER_TXRDY (0x1u << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */
    06402 #define US_IER_RXBRK (0x1u << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */
    06403 #define US_IER_ENDRX (0x1u << 3) /**< \brief (US_IER) End of Receive Transfer Interrupt Enable */
    06404 #define US_IER_ENDTX (0x1u << 4) /**< \brief (US_IER) End of Transmit Interrupt Enable */
    06405 #define US_IER_OVRE (0x1u << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */
    06406 #define US_IER_FRAME (0x1u << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */
    06407 #define US_IER_PARE (0x1u << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */
    06408 #define US_IER_TIMEOUT (0x1u << 8) /**< \brief (US_IER) Time-out Interrupt Enable */
    06409 #define US_IER_TXEMPTY (0x1u << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */
    06410 #define US_IER_ITER (0x1u << 10) /**< \brief (US_IER) Max number of Repetitions Reached */
    06411 #define US_IER_UNRE (0x1u << 10) /**< \brief (US_IER) SPI Underrun Error */
    06412 #define US_IER_TXBUFE (0x1u << 11) /**< \brief (US_IER) Buffer Empty Interrupt Enable */
    06413 #define US_IER_RXBUFF (0x1u << 12) /**< \brief (US_IER) Buffer Full Interrupt Enable */
    06414 #define US_IER_NACK (0x1u << 13) /**< \brief (US_IER) Non AcknowledgeInterrupt Enable */
    06415 #define US_IER_RIIC (0x1u << 16) /**< \brief (US_IER) Ring Indicator Input Change Enable */
    06416 #define US_IER_DSRIC (0x1u << 17) /**< \brief (US_IER) Data Set Ready Input Change Enable */
    06417 #define US_IER_DCDIC (0x1u << 18) /**< \brief (US_IER) Data Carrier Detect Input Change Interrupt Enable */
    06418 #define US_IER_CTSIC (0x1u << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */
    06419 #define US_IER_MANE (0x1u << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */
    06420 /* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */
    06421 #define US_IDR_RXRDY (0x1u << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */
    06422 #define US_IDR_TXRDY (0x1u << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */
    06423 #define US_IDR_RXBRK (0x1u << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */
    06424 #define US_IDR_ENDRX (0x1u << 3) /**< \brief (US_IDR) End of Receive Transfer Interrupt Disable */
    06425 #define US_IDR_ENDTX (0x1u << 4) /**< \brief (US_IDR) End of Transmit Interrupt Disable */
    06426 #define US_IDR_OVRE (0x1u << 5) /**< \brief (US_IDR) Overrun Error Interrupt Disable */
    06427 #define US_IDR_FRAME (0x1u << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */
    06428 #define US_IDR_PARE (0x1u << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */
    06429 #define US_IDR_TIMEOUT (0x1u << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */
    06430 #define US_IDR_TXEMPTY (0x1u << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */
    06431 #define US_IDR_ITER (0x1u << 10) /**< \brief (US_IDR) Max number of Repetitions Reached Disable */
    06432 #define US_IDR_UNRE (0x1u << 10) /**< \brief (US_IDR) SPI Underrun Error Disable */
    06433 #define US_IDR_TXBUFE (0x1u << 11) /**< \brief (US_IDR) Buffer Empty Interrupt Disable */
    06434 #define US_IDR_RXBUFF (0x1u << 12) /**< \brief (US_IDR) Buffer Full Interrupt Disable */
    06435 #define US_IDR_NACK (0x1u << 13) /**< \brief (US_IDR) Non AcknowledgeInterrupt Disable */
    06436 #define US_IDR_RIIC (0x1u << 16) /**< \brief (US_IDR) Ring Indicator Input Change Disable */
    06437 #define US_IDR_DSRIC (0x1u << 17) /**< \brief (US_IDR) Data Set Ready Input Change Disable */
    06438 #define US_IDR_DCDIC (0x1u << 18) /**< \brief (US_IDR) Data Carrier Detect Input Change Interrupt Disable */
    06439 #define US_IDR_CTSIC (0x1u << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */
    06440 #define US_IDR_MANE (0x1u << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */
    06441 /* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */
    06442 #define US_IMR_RXRDY (0x1u << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */
    06443 #define US_IMR_TXRDY (0x1u << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */
    06444 #define US_IMR_RXBRK (0x1u << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */
    06445 #define US_IMR_ENDRX (0x1u << 3) /**< \brief (US_IMR) End of Receive Transfer Interrupt Mask */
    06446 #define US_IMR_ENDTX (0x1u << 4) /**< \brief (US_IMR) End of Transmit Interrupt Mask */
    06447 #define US_IMR_OVRE (0x1u << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */
    06448 #define US_IMR_FRAME (0x1u << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */
    06449 #define US_IMR_PARE (0x1u << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */
    06450 #define US_IMR_TIMEOUT (0x1u << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */
    06451 #define US_IMR_TXEMPTY (0x1u << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */
    06452 #define US_IMR_ITER (0x1u << 10) /**< \brief (US_IMR) Max number of Repetitions Reached Mask */
    06453 #define US_IMR_UNRE (0x1u << 10) /**< \brief (US_IMR) SPI Underrun Error Mask */
    06454 #define US_IMR_TXBUFE (0x1u << 11) /**< \brief (US_IMR) Buffer Empty Interrupt Mask */
    06455 #define US_IMR_RXBUFF (0x1u << 12) /**< \brief (US_IMR) Buffer Full Interrupt Mask */
    06456 #define US_IMR_NACK (0x1u << 13) /**< \brief (US_IMR) Non AcknowledgeInterrupt Mask */
    06457 #define US_IMR_RIIC (0x1u << 16) /**< \brief (US_IMR) Ring Indicator Input Change Mask */
    06458 #define US_IMR_DSRIC (0x1u << 17) /**< \brief (US_IMR) Data Set Ready Input Change Mask */
    06459 #define US_IMR_DCDIC (0x1u << 18) /**< \brief (US_IMR) Data Carrier Detect Input Change Interrupt Mask */
    06460 #define US_IMR_CTSIC (0x1u << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */
    06461 #define US_IMR_MANE (0x1u << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */
    06462 /* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */
    06463 #define US_CSR_RXRDY (0x1u << 0) /**< \brief (US_CSR) Receiver Ready */
    06464 #define US_CSR_TXRDY (0x1u << 1) /**< \brief (US_CSR) Transmitter Ready */
    06465 #define US_CSR_RXBRK (0x1u << 2) /**< \brief (US_CSR) Break Received/End of Break */
    06466 #define US_CSR_ENDRX (0x1u << 3) /**< \brief (US_CSR) End of Receiver Transfer */
    06467 #define US_CSR_ENDTX (0x1u << 4) /**< \brief (US_CSR) End of Transmitter Transfer */
    06468 #define US_CSR_OVRE (0x1u << 5) /**< \brief (US_CSR) Overrun Error */
    06469 #define US_CSR_FRAME (0x1u << 6) /**< \brief (US_CSR) Framing Error */
    06470 #define US_CSR_PARE (0x1u << 7) /**< \brief (US_CSR) Parity Error */
    06471 #define US_CSR_TIMEOUT (0x1u << 8) /**< \brief (US_CSR) Receiver Time-out */
    06472 #define US_CSR_TXEMPTY (0x1u << 9) /**< \brief (US_CSR) Transmitter Empty */
    06473 #define US_CSR_ITER (0x1u << 10) /**< \brief (US_CSR) Max number of Repetitions Reached */
    06474 #define US_CSR_UNRE (0x1u << 10) /**< \brief (US_CSR) SPI Underrun Error */
    06475 #define US_CSR_TXBUFE (0x1u << 11) /**< \brief (US_CSR) Transmission Buffer Empty */
    06476 #define US_CSR_RXBUFF (0x1u << 12) /**< \brief (US_CSR) Reception Buffer Full */
    06477 #define US_CSR_NACK (0x1u << 13) /**< \brief (US_CSR) Non AcknowledgeInterrupt */
    06478 #define US_CSR_RIIC (0x1u << 16) /**< \brief (US_CSR) Ring Indicator Input Change Flag */
    06479 #define US_CSR_DSRIC (0x1u << 17) /**< \brief (US_CSR) Data Set Ready Input Change Flag */
    06480 #define US_CSR_DCDIC (0x1u << 18) /**< \brief (US_CSR) Data Carrier Detect Input Change Flag */
    06481 #define US_CSR_CTSIC (0x1u << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag */
    06482 #define US_CSR_RI (0x1u << 20) /**< \brief (US_CSR) Image of RI Input */
    06483 #define US_CSR_DSR (0x1u << 21) /**< \brief (US_CSR) Image of DSR Input */
    06484 #define US_CSR_DCD (0x1u << 22) /**< \brief (US_CSR) Image of DCD Input */
    06485 #define US_CSR_CTS (0x1u << 23) /**< \brief (US_CSR) Image of CTS Input */
    06486 #define US_CSR_MANERR (0x1u << 24) /**< \brief (US_CSR) Manchester Error */
    06487 /* -------- US_RHR : (USART Offset: 0x0018) Receiver Holding Register -------- */
    06488 #define US_RHR_RXCHR_Pos 0
    06489 #define US_RHR_RXCHR_Msk (0x1ffu << US_RHR_RXCHR_Pos) /**< \brief (US_RHR) Received Character */
    06490 #define US_RHR_RXSYNH (0x1u << 15) /**< \brief (US_RHR) Received Sync */
    06491 /* -------- US_THR : (USART Offset: 0x001C) Transmitter Holding Register -------- */
    06492 #define US_THR_TXCHR_Pos 0
    06493 #define US_THR_TXCHR_Msk (0x1ffu << US_THR_TXCHR_Pos) /**< \brief (US_THR) Character to be Transmitted */
    06494 #define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos)))
    06495 #define US_THR_TXSYNH (0x1u << 15) /**< \brief (US_THR) Sync Field to be transmitted */
    06496 /* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */
    06497 #define US_BRGR_CD_Pos 0
    06498 #define US_BRGR_CD_Msk (0xffffu << US_BRGR_CD_Pos) /**< \brief (US_BRGR) Clock Divider */
    06499 #define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos)))
    06500 #define US_BRGR_FP_Pos 16
    06501 #define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos) /**< \brief (US_BRGR) Fractional Part */
    06502 #define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos)))
    06503 /* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */
    06504 #define US_RTOR_TO_Pos 0
    06505 #define US_RTOR_TO_Msk (0xffffu << US_RTOR_TO_Pos) /**< \brief (US_RTOR) Time-out Value */
    06506 #define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos)))
    06507 /* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */
    06508 #define US_TTGR_TG_Pos 0
    06509 #define US_TTGR_TG_Msk (0xffu << US_TTGR_TG_Pos) /**< \brief (US_TTGR) Timeguard Value */
    06510 #define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos)))
    06511 /* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */
    06512 #define US_FIDI_FI_DI_RATIO_Pos 0
    06513 #define US_FIDI_FI_DI_RATIO_Msk (0x7ffu << US_FIDI_FI_DI_RATIO_Pos) /**< \brief (US_FIDI) FI Over DI Ratio Value */
    06514 #define US_FIDI_FI_DI_RATIO(value) ((US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos)))
    06515 /* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */
    06516 #define US_NER_NB_ERRORS_Pos 0
    06517 #define US_NER_NB_ERRORS_Msk (0xffu << US_NER_NB_ERRORS_Pos) /**< \brief (US_NER) Number of Errors */
    06518 /* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */
    06519 #define US_IF_IRDA_FILTER_Pos 0
    06520 #define US_IF_IRDA_FILTER_Msk (0xffu << US_IF_IRDA_FILTER_Pos) /**< \brief (US_IF) IrDA Filter */
    06521 #define US_IF_IRDA_FILTER(value) ((US_IF_IRDA_FILTER_Msk & ((value) << US_IF_IRDA_FILTER_Pos)))
    06522 /* -------- US_MAN : (USART Offset: 0x0050) Manchester Encoder Decoder Register -------- */
    06523 #define US_MAN_TX_PL_Pos 0
    06524 #define US_MAN_TX_PL_Msk (0xfu << US_MAN_TX_PL_Pos) /**< \brief (US_MAN) Transmitter Preamble Length */
    06525 #define US_MAN_TX_PL(value) ((US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos)))
    06526 #define US_MAN_TX_PP_Pos 8
    06527 #define US_MAN_TX_PP_Msk (0x3u << US_MAN_TX_PP_Pos) /**< \brief (US_MAN) Transmitter Preamble Pattern */
    06528 #define   US_MAN_TX_PP_ALL_ONE (0x0u << 8) /**< \brief (US_MAN) The preamble is composed of '1's */
    06529 #define   US_MAN_TX_PP_ALL_ZERO (0x1u << 8) /**< \brief (US_MAN) The preamble is composed of '0's */
    06530 #define   US_MAN_TX_PP_ZERO_ONE (0x2u << 8) /**< \brief (US_MAN) The preamble is composed of '01's */
    06531 #define   US_MAN_TX_PP_ONE_ZERO (0x3u << 8) /**< \brief (US_MAN) The preamble is composed of '10's */
    06532 #define US_MAN_TX_MPOL (0x1u << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */
    06533 #define US_MAN_RX_PL_Pos 16
    06534 #define US_MAN_RX_PL_Msk (0xfu << US_MAN_RX_PL_Pos) /**< \brief (US_MAN) Receiver Preamble Length */
    06535 #define US_MAN_RX_PL(value) ((US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos)))
    06536 #define US_MAN_RX_PP_Pos 24
    06537 #define US_MAN_RX_PP_Msk (0x3u << US_MAN_RX_PP_Pos) /**< \brief (US_MAN) Receiver Preamble Pattern detected */
    06538 #define   US_MAN_RX_PP_ALL_ONE (0x0u << 24) /**< \brief (US_MAN) The preamble is composed of '1's */
    06539 #define   US_MAN_RX_PP_ALL_ZERO (0x1u << 24) /**< \brief (US_MAN) The preamble is composed of '0's */
    06540 #define   US_MAN_RX_PP_ZERO_ONE (0x2u << 24) /**< \brief (US_MAN) The preamble is composed of '01's */
    06541 #define   US_MAN_RX_PP_ONE_ZERO (0x3u << 24) /**< \brief (US_MAN) The preamble is composed of '10's */
    06542 #define US_MAN_RX_MPOL (0x1u << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */
    06543 #define US_MAN_STUCKTO1 (0x1u << 29) /**< \brief (US_MAN)  */
    06544 #define US_MAN_DRIFT (0x1u << 30) /**< \brief (US_MAN) Drift compensation */
    06545 /* -------- US_WPMR : (USART Offset: 0xE4) Write Protect Mode Register -------- */
    06546 #define US_WPMR_WPEN (0x1u << 0) /**< \brief (US_WPMR) Write Protect Enable */
    06547 #define US_WPMR_WPKEY_Pos 8
    06548 #define US_WPMR_WPKEY_Msk (0xffffffu << US_WPMR_WPKEY_Pos) /**< \brief (US_WPMR) Write Protect KEY */
    06549 #define US_WPMR_WPKEY(value) ((US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos)))
    06550 /* -------- US_WPSR : (USART Offset: 0xE8) Write Protect Status Register -------- */
    06551 #define US_WPSR_WPVS (0x1u << 0) /**< \brief (US_WPSR) Write Protect Violation Status */
    06552 #define US_WPSR_WPVSRC_Pos 8
    06553 #define US_WPSR_WPVSRC_Msk (0xffffu << US_WPSR_WPVSRC_Pos) /**< \brief (US_WPSR) Write Protect Violation Source */
    06554 /* -------- US_VERSION : (USART Offset: 0xFC) Version Register -------- */
    06555 #define US_VERSION_VERSION_Pos 0
    06556 #define US_VERSION_VERSION_Msk (0xfffu << US_VERSION_VERSION_Pos) /**< \brief (US_VERSION)  */
    06557 #define US_VERSION_MFN_Pos 16
    06558 #define US_VERSION_MFN_Msk (0x7u << US_VERSION_MFN_Pos) /**< \brief (US_VERSION)  */
    06559 /* -------- US_RPR : (USART Offset: 0x100) Receive Pointer Register -------- */
    06560 #define US_RPR_RXPTR_Pos 0
    06561 #define US_RPR_RXPTR_Msk (0xffffffffu << US_RPR_RXPTR_Pos) /**< \brief (US_RPR) Receive Pointer Register */
    06562 #define US_RPR_RXPTR(value) ((US_RPR_RXPTR_Msk & ((value) << US_RPR_RXPTR_Pos)))
    06563 /* -------- US_RCR : (USART Offset: 0x104) Receive Counter Register -------- */
    06564 #define US_RCR_RXCTR_Pos 0
    06565 #define US_RCR_RXCTR_Msk (0xffffu << US_RCR_RXCTR_Pos) /**< \brief (US_RCR) Receive Counter Register */
    06566 #define US_RCR_RXCTR(value) ((US_RCR_RXCTR_Msk & ((value) << US_RCR_RXCTR_Pos)))
    06567 /* -------- US_TPR : (USART Offset: 0x108) Transmit Pointer Register -------- */
    06568 #define US_TPR_TXPTR_Pos 0
    06569 #define US_TPR_TXPTR_Msk (0xffffffffu << US_TPR_TXPTR_Pos) /**< \brief (US_TPR) Transmit Counter Register */
    06570 #define US_TPR_TXPTR(value) ((US_TPR_TXPTR_Msk & ((value) << US_TPR_TXPTR_Pos)))
    06571 /* -------- US_TCR : (USART Offset: 0x10C) Transmit Counter Register -------- */
    06572 #define US_TCR_TXCTR_Pos 0
    06573 #define US_TCR_TXCTR_Msk (0xffffu << US_TCR_TXCTR_Pos) /**< \brief (US_TCR) Transmit Counter Register */
    06574 #define US_TCR_TXCTR(value) ((US_TCR_TXCTR_Msk & ((value) << US_TCR_TXCTR_Pos)))
    06575 /* -------- US_RNPR : (USART Offset: 0x110) Receive Next Pointer Register -------- */
    06576 #define US_RNPR_RXNPTR_Pos 0
    06577 #define US_RNPR_RXNPTR_Msk (0xffffffffu << US_RNPR_RXNPTR_Pos) /**< \brief (US_RNPR) Receive Next Pointer */
    06578 #define US_RNPR_RXNPTR(value) ((US_RNPR_RXNPTR_Msk & ((value) << US_RNPR_RXNPTR_Pos)))
    06579 /* -------- US_RNCR : (USART Offset: 0x114) Receive Next Counter Register -------- */
    06580 #define US_RNCR_RXNCTR_Pos 0
    06581 #define US_RNCR_RXNCTR_Msk (0xffffu << US_RNCR_RXNCTR_Pos) /**< \brief (US_RNCR) Receive Next Counter */
    06582 #define US_RNCR_RXNCTR(value) ((US_RNCR_RXNCTR_Msk & ((value) << US_RNCR_RXNCTR_Pos)))
    06583 /* -------- US_TNPR : (USART Offset: 0x118) Transmit Next Pointer Register -------- */
    06584 #define US_TNPR_TXNPTR_Pos 0
    06585 #define US_TNPR_TXNPTR_Msk (0xffffffffu << US_TNPR_TXNPTR_Pos) /**< \brief (US_TNPR) Transmit Next Pointer */
    06586 #define US_TNPR_TXNPTR(value) ((US_TNPR_TXNPTR_Msk & ((value) << US_TNPR_TXNPTR_Pos)))
    06587 /* -------- US_TNCR : (USART Offset: 0x11C) Transmit Next Counter Register -------- */
    06588 #define US_TNCR_TXNCTR_Pos 0
    06589 #define US_TNCR_TXNCTR_Msk (0xffffu << US_TNCR_TXNCTR_Pos) /**< \brief (US_TNCR) Transmit Counter Next */
    06590 #define US_TNCR_TXNCTR(value) ((US_TNCR_TXNCTR_Msk & ((value) << US_TNCR_TXNCTR_Pos)))
    06591 /* -------- US_PTCR : (USART Offset: 0x120) Transfer Control Register -------- */
    06592 #define US_PTCR_RXTEN (0x1u << 0) /**< \brief (US_PTCR) Receiver Transfer Enable */
    06593 #define US_PTCR_RXTDIS (0x1u << 1) /**< \brief (US_PTCR) Receiver Transfer Disable */
    06594 #define US_PTCR_TXTEN (0x1u << 8) /**< \brief (US_PTCR) Transmitter Transfer Enable */
    06595 #define US_PTCR_TXTDIS (0x1u << 9) /**< \brief (US_PTCR) Transmitter Transfer Disable */
    06596 /* -------- US_PTSR : (USART Offset: 0x124) Transfer Status Register -------- */
    06597 #define US_PTSR_RXTEN (0x1u << 0) /**< \brief (US_PTSR) Receiver Transfer Enable */
    06598 #define US_PTSR_TXTEN (0x1u << 8) /**< \brief (US_PTSR) Transmitter Transfer Enable */
    06599
    06600 /*@}*/
    06601
    06602 /* ============================================================================= */
    06603 /**  SOFTWARE API DEFINITION FOR Watchdog Timer */
    06604 /* ============================================================================= */
    06605 /** \addtogroup SAM3S8_WDT Watchdog Timer */
    06606 /*@{*/
    06607
    06608 #ifndef __ASSEMBLY__
    06609 /** \brief Wdt hardware registers */
    06610 typedef struct {
    06611   WoReg WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */
    06612   RwReg WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */
    06613   RoReg WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */
    06614 } Wdt;
    06615 #endif /* __ASSEMBLY__ */
    06616 /* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */
    06617 #define WDT_CR_WDRSTT (0x1u << 0) /**< \brief (WDT_CR) Watchdog Restart */
    06618 #define WDT_CR_KEY_Pos 24
    06619 #define WDT_CR_KEY_Msk (0xffu << WDT_CR_KEY_Pos) /**< \brief (WDT_CR) Password */
    06620 #define WDT_CR_KEY(value) ((WDT_CR_KEY_Msk & ((value) << WDT_CR_KEY_Pos)))
    06621 /* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */
    06622 #define WDT_MR_WDV_Pos 0
    06623 #define WDT_MR_WDV_Msk (0xfffu << WDT_MR_WDV_Pos) /**< \brief (WDT_MR) Watchdog Counter Value */
    06624 #define WDT_MR_WDV(value) ((WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos)))
    06625 #define WDT_MR_WDFIEN (0x1u << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */
    06626 #define WDT_MR_WDRSTEN (0x1u << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */
    06627 #define WDT_MR_WDRPROC (0x1u << 14) /**< \brief (WDT_MR) Watchdog Reset Processor */
    06628 #define WDT_MR_WDDIS (0x1u << 15) /**< \brief (WDT_MR) Watchdog Disable */
    06629 #define WDT_MR_WDD_Pos 16
    06630 #define WDT_MR_WDD_Msk (0xfffu << WDT_MR_WDD_Pos) /**< \brief (WDT_MR) Watchdog Delta Value */
    06631 #define WDT_MR_WDD(value) ((WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos)))
    06632 #define WDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */
    06633 #define WDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */
    06634 /* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */
    06635 #define WDT_SR_WDUNF (0x1u << 0) /**< \brief (WDT_SR) Watchdog Underflow */
    06636 #define WDT_SR_WDERR (0x1u << 1) /**< \brief (WDT_SR) Watchdog Error */
    06637
    06638 /*@}*/
    06639
    06640 /*@}*/
    06641
    06642 /* ************************************************************************** */
    06643 /*   REGISTER ACCESS DEFINITIONS FOR SAM3S8 */
    06644 /* ************************************************************************** */
    06645 /** \addtogroup SAM3S8_reg Registers Access Definitions */
    06646 /*@{*/
    06647
    06648 /* ========== Register definition for HSMCI peripheral ========== */
    06649 #define REG_HSMCI_CR        REG_ACCESS(WoReg, 0x40000000U) /**< \brief (HSMCI) Control Register */
    06650 #define REG_HSMCI_MR        REG_ACCESS(RwReg, 0x40000004U) /**< \brief (HSMCI) Mode Register */
    06651 #define REG_HSMCI_DTOR      REG_ACCESS(RwReg, 0x40000008U) /**< \brief (HSMCI) Data Timeout Register */
    06652 #define REG_HSMCI_SDCR      REG_ACCESS(RwReg, 0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */
    06653 #define REG_HSMCI_ARGR      REG_ACCESS(RwReg, 0x40000010U) /**< \brief (HSMCI) Argument Register */
    06654 #define REG_HSMCI_CMDR      REG_ACCESS(WoReg, 0x40000014U) /**< \brief (HSMCI) Command Register */
    06655 #define REG_HSMCI_BLKR      REG_ACCESS(RwReg, 0x40000018U) /**< \brief (HSMCI) Block Register */
    06656 #define REG_HSMCI_CSTOR     REG_ACCESS(RwReg, 0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */
    06657 #define REG_HSMCI_RSPR      REG_ACCESS(RoReg, 0x40000020U) /**< \brief (HSMCI) Response Register */
    06658 #define REG_HSMCI_RDR       REG_ACCESS(RoReg, 0x40000030U) /**< \brief (HSMCI) Receive Data Register */
    06659 #define REG_HSMCI_TDR       REG_ACCESS(WoReg, 0x40000034U) /**< \brief (HSMCI) Transmit Data Register */
    06660 #define REG_HSMCI_SR        REG_ACCESS(RoReg, 0x40000040U) /**< \brief (HSMCI) Status Register */
    06661 #define REG_HSMCI_IER       REG_ACCESS(WoReg, 0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */
    06662 #define REG_HSMCI_IDR       REG_ACCESS(WoReg, 0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */
    06663 #define REG_HSMCI_IMR       REG_ACCESS(RoReg, 0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */
    06664 #define REG_HSMCI_CFG       REG_ACCESS(RwReg, 0x40000054U) /**< \brief (HSMCI) Configuration Register */
    06665 #define REG_HSMCI_WPMR      REG_ACCESS(RwReg, 0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */
    06666 #define REG_HSMCI_WPSR      REG_ACCESS(RoReg, 0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */
    06667 #define REG_HSMCI_RPR       REG_ACCESS(RwReg, 0x40000100U) /**< \brief (HSMCI) Receive Pointer Register */
    06668 #define REG_HSMCI_RCR       REG_ACCESS(RwReg, 0x40000104U) /**< \brief (HSMCI) Receive Counter Register */
    06669 #define REG_HSMCI_TPR       REG_ACCESS(RwReg, 0x40000108U) /**< \brief (HSMCI) Transmit Pointer Register */
    06670 #define REG_HSMCI_TCR       REG_ACCESS(RwReg, 0x4000010CU) /**< \brief (HSMCI) Transmit Counter Register */
    06671 #define REG_HSMCI_RNPR      REG_ACCESS(RwReg, 0x40000110U) /**< \brief (HSMCI) Receive Next Pointer Register */
    06672 #define REG_HSMCI_RNCR      REG_ACCESS(RwReg, 0x40000114U) /**< \brief (HSMCI) Receive Next Counter Register */
    06673 #define REG_HSMCI_TNPR      REG_ACCESS(RwReg, 0x40000118U) /**< \brief (HSMCI) Transmit Next Pointer Register */
    06674 #define REG_HSMCI_TNCR      REG_ACCESS(RwReg, 0x4000011CU) /**< \brief (HSMCI) Transmit Next Counter Register */
    06675 #define REG_HSMCI_PTCR      REG_ACCESS(WoReg, 0x40000120U) /**< \brief (HSMCI) Transfer Control Register */
    06676 #define REG_HSMCI_PTSR      REG_ACCESS(RoReg, 0x40000124U) /**< \brief (HSMCI) Transfer Status Register */
    06677 #define REG_HSMCI_FIFO      REG_ACCESS(RwReg, 0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */
    06678 /* ========== Register definition for SSC peripheral ========== */
    06679 #define REG_SSC_CR          REG_ACCESS(WoReg, 0x40004000U) /**< \brief (SSC) Control Register */
    06680 #define REG_SSC_CMR         REG_ACCESS(RwReg, 0x40004004U) /**< \brief (SSC) Clock Mode Register */
    06681 #define REG_SSC_RCMR        REG_ACCESS(RwReg, 0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */
    06682 #define REG_SSC_RFMR        REG_ACCESS(RwReg, 0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */
    06683 #define REG_SSC_TCMR        REG_ACCESS(RwReg, 0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */
    06684 #define REG_SSC_TFMR        REG_ACCESS(RwReg, 0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */
    06685 #define REG_SSC_RHR         REG_ACCESS(RoReg, 0x40004020U) /**< \brief (SSC) Receive Holding Register */
    06686 #define REG_SSC_THR         REG_ACCESS(WoReg, 0x40004024U) /**< \brief (SSC) Transmit Holding Register */
    06687 #define REG_SSC_RSHR        REG_ACCESS(RoReg, 0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */
    06688 #define REG_SSC_TSHR        REG_ACCESS(RwReg, 0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */
    06689 #define REG_SSC_RC0R        REG_ACCESS(RwReg, 0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */
    06690 #define REG_SSC_RC1R        REG_ACCESS(RwReg, 0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */
    06691 #define REG_SSC_SR          REG_ACCESS(RoReg, 0x40004040U) /**< \brief (SSC) Status Register */
    06692 #define REG_SSC_IER         REG_ACCESS(WoReg, 0x40004044U) /**< \brief (SSC) Interrupt Enable Register */
    06693 #define REG_SSC_IDR         REG_ACCESS(WoReg, 0x40004048U) /**< \brief (SSC) Interrupt Disable Register */
    06694 #define REG_SSC_IMR         REG_ACCESS(RoReg, 0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */
    06695 #define REG_SSC_WPMR        REG_ACCESS(RwReg, 0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */
    06696 #define REG_SSC_WPSR        REG_ACCESS(RoReg, 0x400040E8U) /**< \brief (SSC) Write Protect Status Register */
    06697 #define REG_SSC_RPR         REG_ACCESS(RwReg, 0x40004100U) /**< \brief (SSC) Receive Pointer Register */
    06698 #define REG_SSC_RCR         REG_ACCESS(RwReg, 0x40004104U) /**< \brief (SSC) Receive Counter Register */
    06699 #define REG_SSC_TPR         REG_ACCESS(RwReg, 0x40004108U) /**< \brief (SSC) Transmit Pointer Register */
    06700 #define REG_SSC_TCR         REG_ACCESS(RwReg, 0x4000410CU) /**< \brief (SSC) Transmit Counter Register */
    06701 #define REG_SSC_RNPR        REG_ACCESS(RwReg, 0x40004110U) /**< \brief (SSC) Receive Next Pointer Register */
    06702 #define REG_SSC_RNCR        REG_ACCESS(RwReg, 0x40004114U) /**< \brief (SSC) Receive Next Counter Register */
    06703 #define REG_SSC_TNPR        REG_ACCESS(RwReg, 0x40004118U) /**< \brief (SSC) Transmit Next Pointer Register */
    06704 #define REG_SSC_TNCR        REG_ACCESS(RwReg, 0x4000411CU) /**< \brief (SSC) Transmit Next Counter Register */
    06705 #define REG_SSC_PTCR        REG_ACCESS(WoReg, 0x40004120U) /**< \brief (SSC) Transfer Control Register */
    06706 #define REG_SSC_PTSR        REG_ACCESS(RoReg, 0x40004124U) /**< \brief (SSC) Transfer Status Register */
    06707 /* ========== Register definition for SPI peripheral ========== */
    06708 #define REG_SPI_CR          REG_ACCESS(WoReg, 0x40008000U) /**< \brief (SPI) Control Register */
    06709 #define REG_SPI_MR          REG_ACCESS(RwReg, 0x40008004U) /**< \brief (SPI) Mode Register */
    06710 #define REG_SPI_RDR         REG_ACCESS(RoReg, 0x40008008U) /**< \brief (SPI) Receive Data Register */
    06711 #define REG_SPI_TDR         REG_ACCESS(WoReg, 0x4000800CU) /**< \brief (SPI) Transmit Data Register */
    06712 #define REG_SPI_SR          REG_ACCESS(RoReg, 0x40008010U) /**< \brief (SPI) Status Register */
    06713 #define REG_SPI_IER         REG_ACCESS(WoReg, 0x40008014U) /**< \brief (SPI) Interrupt Enable Register */
    06714 #define REG_SPI_IDR         REG_ACCESS(WoReg, 0x40008018U) /**< \brief (SPI) Interrupt Disable Register */
    06715 #define REG_SPI_IMR         REG_ACCESS(RoReg, 0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */
    06716 #define REG_SPI_CSR         REG_ACCESS(RwReg, 0x40008030U) /**< \brief (SPI) Chip Select Register */
    06717 #define REG_SPI_WPMR        REG_ACCESS(RwReg, 0x400080E4U) /**< \brief (SPI) Write Protection Control Register */
    06718 #define REG_SPI_WPSR        REG_ACCESS(RoReg, 0x400080E8U) /**< \brief (SPI) Write Protection Status Register */
    06719 #define REG_SPI_RPR         REG_ACCESS(RwReg, 0x40008100U) /**< \brief (SPI) Receive Pointer Register */
    06720 #define REG_SPI_RCR         REG_ACCESS(RwReg, 0x40008104U) /**< \brief (SPI) Receive Counter Register */
    06721 #define REG_SPI_TPR         REG_ACCESS(RwReg, 0x40008108U) /**< \brief (SPI) Transmit Pointer Register */
    06722 #define REG_SPI_TCR         REG_ACCESS(RwReg, 0x4000810CU) /**< \brief (SPI) Transmit Counter Register */
    06723 #define REG_SPI_RNPR        REG_ACCESS(RwReg, 0x40008110U) /**< \brief (SPI) Receive Next Pointer Register */
    06724 #define REG_SPI_RNCR        REG_ACCESS(RwReg, 0x40008114U) /**< \brief (SPI) Receive Next Counter Register */
    06725 #define REG_SPI_TNPR        REG_ACCESS(RwReg, 0x40008118U) /**< \brief (SPI) Transmit Next Pointer Register */
    06726 #define REG_SPI_TNCR        REG_ACCESS(RwReg, 0x4000811CU) /**< \brief (SPI) Transmit Next Counter Register */
    06727 #define REG_SPI_PTCR        REG_ACCESS(WoReg, 0x40008120U) /**< \brief (SPI) Transfer Control Register */
    06728 #define REG_SPI_PTSR        REG_ACCESS(RoReg, 0x40008124U) /**< \brief (SPI) Transfer Status Register */
    06729 /* ========== Register definition for TC0 peripheral ========== */
    06730 #define REG_TC0_CCR0        REG_ACCESS(WoReg, 0x40010000U) /**< \brief (TC0) Channel Control Register (channel = 0) */
    06731 #define REG_TC0_CMR0        REG_ACCESS(RwReg, 0x40010004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */
    06732 #define REG_TC0_SMMR0       REG_ACCESS(RwReg, 0x40010008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */
    06733 #define REG_TC0_CV0         REG_ACCESS(RoReg, 0x40010010U) /**< \brief (TC0) Counter Value (channel = 0) */
    06734 #define REG_TC0_RA0         REG_ACCESS(RwReg, 0x40010014U) /**< \brief (TC0) Register A (channel = 0) */
    06735 #define REG_TC0_RB0         REG_ACCESS(RwReg, 0x40010018U) /**< \brief (TC0) Register B (channel = 0) */
    06736 #define REG_TC0_RC0         REG_ACCESS(RwReg, 0x4001001CU) /**< \brief (TC0) Register C (channel = 0) */
    06737 #define REG_TC0_SR0         REG_ACCESS(RoReg, 0x40010020U) /**< \brief (TC0) Status Register (channel = 0) */
    06738 #define REG_TC0_IER0        REG_ACCESS(WoReg, 0x40010024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */
    06739 #define REG_TC0_IDR0        REG_ACCESS(WoReg, 0x40010028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */
    06740 #define REG_TC0_IMR0        REG_ACCESS(RoReg, 0x4001002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */
    06741 #define REG_TC0_CCR1        REG_ACCESS(WoReg, 0x40010040U) /**< \brief (TC0) Channel Control Register (channel = 1) */
    06742 #define REG_TC0_CMR1        REG_ACCESS(RwReg, 0x40010044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */
    06743 #define REG_TC0_SMMR1       REG_ACCESS(RwReg, 0x40010048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */
    06744 #define REG_TC0_CV1         REG_ACCESS(RoReg, 0x40010050U) /**< \brief (TC0) Counter Value (channel = 1) */
    06745 #define REG_TC0_RA1         REG_ACCESS(RwReg, 0x40010054U) /**< \brief (TC0) Register A (channel = 1) */
    06746 #define REG_TC0_RB1         REG_ACCESS(RwReg, 0x40010058U) /**< \brief (TC0) Register B (channel = 1) */
    06747 #define REG_TC0_RC1         REG_ACCESS(RwReg, 0x4001005CU) /**< \brief (TC0) Register C (channel = 1) */
    06748 #define REG_TC0_SR1         REG_ACCESS(RoReg, 0x40010060U) /**< \brief (TC0) Status Register (channel = 1) */
    06749 #define REG_TC0_IER1        REG_ACCESS(WoReg, 0x40010064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */
    06750 #define REG_TC0_IDR1        REG_ACCESS(WoReg, 0x40010068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */
    06751 #define REG_TC0_IMR1        REG_ACCESS(RoReg, 0x4001006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */
    06752 #define REG_TC0_CCR2        REG_ACCESS(WoReg, 0x40010080U) /**< \brief (TC0) Channel Control Register (channel = 2) */
    06753 #define REG_TC0_CMR2        REG_ACCESS(RwReg, 0x40010084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */
    06754 #define REG_TC0_SMMR2       REG_ACCESS(RwReg, 0x40010088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */
    06755 #define REG_TC0_CV2         REG_ACCESS(RoReg, 0x40010090U) /**< \brief (TC0) Counter Value (channel = 2) */
    06756 #define REG_TC0_RA2         REG_ACCESS(RwReg, 0x40010094U) /**< \brief (TC0) Register A (channel = 2) */
    06757 #define REG_TC0_RB2         REG_ACCESS(RwReg, 0x40010098U) /**< \brief (TC0) Register B (channel = 2) */
    06758 #define REG_TC0_RC2         REG_ACCESS(RwReg, 0x4001009CU) /**< \brief (TC0) Register C (channel = 2) */
    06759 #define REG_TC0_SR2         REG_ACCESS(RoReg, 0x400100A0U) /**< \brief (TC0) Status Register (channel = 2) */
    06760 #define REG_TC0_IER2        REG_ACCESS(WoReg, 0x400100A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */
    06761 #define REG_TC0_IDR2        REG_ACCESS(WoReg, 0x400100A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */
    06762 #define REG_TC0_IMR2        REG_ACCESS(RoReg, 0x400100ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */
    06763 #define REG_TC0_BCR         REG_ACCESS(WoReg, 0x400100C0U) /**< \brief (TC0) Block Control Register */
    06764 #define REG_TC0_BMR         REG_ACCESS(RwReg, 0x400100C4U) /**< \brief (TC0) Block Mode Register */
    06765 #define REG_TC0_QIER        REG_ACCESS(WoReg, 0x400100C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */
    06766 #define REG_TC0_QIDR        REG_ACCESS(WoReg, 0x400100CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */
    06767 #define REG_TC0_QIMR        REG_ACCESS(RoReg, 0x400100D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */
    06768 #define REG_TC0_QISR        REG_ACCESS(RoReg, 0x400100D4U) /**< \brief (TC0) QDEC Interrupt Status Register */
    06769 #define REG_TC0_FMR         REG_ACCESS(RwReg, 0x400100D8U) /**< \brief (TC0) Fault Mode Register */
    06770 #define REG_TC0_WPMR        REG_ACCESS(RwReg, 0x400100E4U) /**< \brief (TC0) Write Protect Mode Register */
    06771 /* ========== Register definition for TC1 peripheral ========== */
    06772 #define REG_TC1_CCR0        REG_ACCESS(WoReg, 0x40014000U) /**< \brief (TC1) Channel Control Register (channel = 0) */
    06773 #define REG_TC1_CMR0        REG_ACCESS(RwReg, 0x40014004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */
    06774 #define REG_TC1_SMMR0       REG_ACCESS(RwReg, 0x40014008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */
    06775 #define REG_TC1_CV0         REG_ACCESS(RoReg, 0x40014010U) /**< \brief (TC1) Counter Value (channel = 0) */
    06776 #define REG_TC1_RA0         REG_ACCESS(RwReg, 0x40014014U) /**< \brief (TC1) Register A (channel = 0) */
    06777 #define REG_TC1_RB0         REG_ACCESS(RwReg, 0x40014018U) /**< \brief (TC1) Register B (channel = 0) */
    06778 #define REG_TC1_RC0         REG_ACCESS(RwReg, 0x4001401CU) /**< \brief (TC1) Register C (channel = 0) */
    06779 #define REG_TC1_SR0         REG_ACCESS(RoReg, 0x40014020U) /**< \brief (TC1) Status Register (channel = 0) */
    06780 #define REG_TC1_IER0        REG_ACCESS(WoReg, 0x40014024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */
    06781 #define REG_TC1_IDR0        REG_ACCESS(WoReg, 0x40014028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */
    06782 #define REG_TC1_IMR0        REG_ACCESS(RoReg, 0x4001402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */
    06783 #define REG_TC1_CCR1        REG_ACCESS(WoReg, 0x40014040U) /**< \brief (TC1) Channel Control Register (channel = 1) */
    06784 #define REG_TC1_CMR1        REG_ACCESS(RwReg, 0x40014044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */
    06785 #define REG_TC1_SMMR1       REG_ACCESS(RwReg, 0x40014048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */
    06786 #define REG_TC1_CV1         REG_ACCESS(RoReg, 0x40014050U) /**< \brief (TC1) Counter Value (channel = 1) */
    06787 #define REG_TC1_RA1         REG_ACCESS(RwReg, 0x40014054U) /**< \brief (TC1) Register A (channel = 1) */
    06788 #define REG_TC1_RB1         REG_ACCESS(RwReg, 0x40014058U) /**< \brief (TC1) Register B (channel = 1) */
    06789 #define REG_TC1_RC1         REG_ACCESS(RwReg, 0x4001405CU) /**< \brief (TC1) Register C (channel = 1) */
    06790 #define REG_TC1_SR1         REG_ACCESS(RoReg, 0x40014060U) /**< \brief (TC1) Status Register (channel = 1) */
    06791 #define REG_TC1_IER1        REG_ACCESS(WoReg, 0x40014064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */
    06792 #define REG_TC1_IDR1        REG_ACCESS(WoReg, 0x40014068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */
    06793 #define REG_TC1_IMR1        REG_ACCESS(RoReg, 0x4001406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */
    06794 #define REG_TC1_CCR2        REG_ACCESS(WoReg, 0x40014080U) /**< \brief (TC1) Channel Control Register (channel = 2) */
    06795 #define REG_TC1_CMR2        REG_ACCESS(RwReg, 0x40014084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */
    06796 #define REG_TC1_SMMR2       REG_ACCESS(RwReg, 0x40014088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */
    06797 #define REG_TC1_CV2         REG_ACCESS(RoReg, 0x40014090U) /**< \brief (TC1) Counter Value (channel = 2) */
    06798 #define REG_TC1_RA2         REG_ACCESS(RwReg, 0x40014094U) /**< \brief (TC1) Register A (channel = 2) */
    06799 #define REG_TC1_RB2         REG_ACCESS(RwReg, 0x40014098U) /**< \brief (TC1) Register B (channel = 2) */
    06800 #define REG_TC1_RC2         REG_ACCESS(RwReg, 0x4001409CU) /**< \brief (TC1) Register C (channel = 2) */
    06801 #define REG_TC1_SR2         REG_ACCESS(RoReg, 0x400140A0U) /**< \brief (TC1) Status Register (channel = 2) */
    06802 #define REG_TC1_IER2        REG_ACCESS(WoReg, 0x400140A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */
    06803 #define REG_TC1_IDR2        REG_ACCESS(WoReg, 0x400140A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */
    06804 #define REG_TC1_IMR2        REG_ACCESS(RoReg, 0x400140ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */
    06805 #define REG_TC1_BCR         REG_ACCESS(WoReg, 0x400140C0U) /**< \brief (TC1) Block Control Register */
    06806 #define REG_TC1_BMR         REG_ACCESS(RwReg, 0x400140C4U) /**< \brief (TC1) Block Mode Register */
    06807 #define REG_TC1_QIER        REG_ACCESS(WoReg, 0x400140C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */
    06808 #define REG_TC1_QIDR        REG_ACCESS(WoReg, 0x400140CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */
    06809 #define REG_TC1_QIMR        REG_ACCESS(RoReg, 0x400140D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */
    06810 #define REG_TC1_QISR        REG_ACCESS(RoReg, 0x400140D4U) /**< \brief (TC1) QDEC Interrupt Status Register */
    06811 #define REG_TC1_FMR         REG_ACCESS(RwReg, 0x400140D8U) /**< \brief (TC1) Fault Mode Register */
    06812 #define REG_TC1_WPMR        REG_ACCESS(RwReg, 0x400140E4U) /**< \brief (TC1) Write Protect Mode Register */
    06813 /* ========== Register definition for TWI0 peripheral ========== */
    06814 #define REG_TWI0_CR         REG_ACCESS(WoReg, 0x40018000U) /**< \brief (TWI0) Control Register */
    06815 #define REG_TWI0_MMR        REG_ACCESS(RwReg, 0x40018004U) /**< \brief (TWI0) Master Mode Register */
    06816 #define REG_TWI0_SMR        REG_ACCESS(RwReg, 0x40018008U) /**< \brief (TWI0) Slave Mode Register */
    06817 #define REG_TWI0_IADR       REG_ACCESS(RwReg, 0x4001800CU) /**< \brief (TWI0) Internal Address Register */
    06818 #define REG_TWI0_CWGR       REG_ACCESS(RwReg, 0x40018010U) /**< \brief (TWI0) Clock Waveform Generator Register */
    06819 #define REG_TWI0_SR         REG_ACCESS(RoReg, 0x40018020U) /**< \brief (TWI0) Status Register */
    06820 #define REG_TWI0_IER        REG_ACCESS(WoReg, 0x40018024U) /**< \brief (TWI0) Interrupt Enable Register */
    06821 #define REG_TWI0_IDR        REG_ACCESS(WoReg, 0x40018028U) /**< \brief (TWI0) Interrupt Disable Register */
    06822 #define REG_TWI0_IMR        REG_ACCESS(RoReg, 0x4001802CU) /**< \brief (TWI0) Interrupt Mask Register */
    06823 #define REG_TWI0_RHR        REG_ACCESS(RoReg, 0x40018030U) /**< \brief (TWI0) Receive Holding Register */
    06824 #define REG_TWI0_THR        REG_ACCESS(WoReg, 0x40018034U) /**< \brief (TWI0) Transmit Holding Register */
    06825 #define REG_TWI0_RPR        REG_ACCESS(RwReg, 0x40018100U) /**< \brief (TWI0) Receive Pointer Register */
    06826 #define REG_TWI0_RCR        REG_ACCESS(RwReg, 0x40018104U) /**< \brief (TWI0) Receive Counter Register */
    06827 #define REG_TWI0_TPR        REG_ACCESS(RwReg, 0x40018108U) /**< \brief (TWI0) Transmit Pointer Register */
    06828 #define REG_TWI0_TCR        REG_ACCESS(RwReg, 0x4001810CU) /**< \brief (TWI0) Transmit Counter Register */
    06829 #define REG_TWI0_RNPR       REG_ACCESS(RwReg, 0x40018110U) /**< \brief (TWI0) Receive Next Pointer Register */
    06830 #define REG_TWI0_RNCR       REG_ACCESS(RwReg, 0x40018114U) /**< \brief (TWI0) Receive Next Counter Register */
    06831 #define REG_TWI0_TNPR       REG_ACCESS(RwReg, 0x40018118U) /**< \brief (TWI0) Transmit Next Pointer Register */
    06832 #define REG_TWI0_TNCR       REG_ACCESS(RwReg, 0x4001811CU) /**< \brief (TWI0) Transmit Next Counter Register */
    06833 #define REG_TWI0_PTCR       REG_ACCESS(WoReg, 0x40018120U) /**< \brief (TWI0) Transfer Control Register */
    06834 #define REG_TWI0_PTSR       REG_ACCESS(RoReg, 0x40018124U) /**< \brief (TWI0) Transfer Status Register */
    06835 /* ========== Register definition for TWI1 peripheral ========== */
    06836 #define REG_TWI1_CR         REG_ACCESS(WoReg, 0x4001C000U) /**< \brief (TWI1) Control Register */
    06837 #define REG_TWI1_MMR        REG_ACCESS(RwReg, 0x4001C004U) /**< \brief (TWI1) Master Mode Register */
    06838 #define REG_TWI1_SMR        REG_ACCESS(RwReg, 0x4001C008U) /**< \brief (TWI1) Slave Mode Register */
    06839 #define REG_TWI1_IADR       REG_ACCESS(RwReg, 0x4001C00CU) /**< \brief (TWI1) Internal Address Register */
    06840 #define REG_TWI1_CWGR       REG_ACCESS(RwReg, 0x4001C010U) /**< \brief (TWI1) Clock Waveform Generator Register */
    06841 #define REG_TWI1_SR         REG_ACCESS(RoReg, 0x4001C020U) /**< \brief (TWI1) Status Register */
    06842 #define REG_TWI1_IER        REG_ACCESS(WoReg, 0x4001C024U) /**< \brief (TWI1) Interrupt Enable Register */
    06843 #define REG_TWI1_IDR        REG_ACCESS(WoReg, 0x4001C028U) /**< \brief (TWI1) Interrupt Disable Register */
    06844 #define REG_TWI1_IMR        REG_ACCESS(RoReg, 0x4001C02CU) /**< \brief (TWI1) Interrupt Mask Register */
    06845 #define REG_TWI1_RHR        REG_ACCESS(RoReg, 0x4001C030U) /**< \brief (TWI1) Receive Holding Register */
    06846 #define REG_TWI1_THR        REG_ACCESS(WoReg, 0x4001C034U) /**< \brief (TWI1) Transmit Holding Register */
    06847 #define REG_TWI1_RPR        REG_ACCESS(RwReg, 0x4001C100U) /**< \brief (TWI1) Receive Pointer Register */
    06848 #define REG_TWI1_RCR        REG_ACCESS(RwReg, 0x4001C104U) /**< \brief (TWI1) Receive Counter Register */
    06849 #define REG_TWI1_TPR        REG_ACCESS(RwReg, 0x4001C108U) /**< \brief (TWI1) Transmit Pointer Register */
    06850 #define REG_TWI1_TCR        REG_ACCESS(RwReg, 0x4001C10CU) /**< \brief (TWI1) Transmit Counter Register */
    06851 #define REG_TWI1_RNPR       REG_ACCESS(RwReg, 0x4001C110U) /**< \brief (TWI1) Receive Next Pointer Register */
    06852 #define REG_TWI1_RNCR       REG_ACCESS(RwReg, 0x4001C114U) /**< \brief (TWI1) Receive Next Counter Register */
    06853 #define REG_TWI1_TNPR       REG_ACCESS(RwReg, 0x4001C118U) /**< \brief (TWI1) Transmit Next Pointer Register */
    06854 #define REG_TWI1_TNCR       REG_ACCESS(RwReg, 0x4001C11CU) /**< \brief (TWI1) Transmit Next Counter Register */
    06855 #define REG_TWI1_PTCR       REG_ACCESS(WoReg, 0x4001C120U) /**< \brief (TWI1) Transfer Control Register */
    06856 #define REG_TWI1_PTSR       REG_ACCESS(RoReg, 0x4001C124U) /**< \brief (TWI1) Transfer Status Register */
    06857 /* ========== Register definition for PWM peripheral ========== */
    06858 #define REG_PWM_CLK         REG_ACCESS(RwReg, 0x40020000U) /**< \brief (PWM) PWM Clock Register */
    06859 #define REG_PWM_ENA         REG_ACCESS(WoReg, 0x40020004U) /**< \brief (PWM) PWM Enable Register */
    06860 #define REG_PWM_DIS         REG_ACCESS(WoReg, 0x40020008U) /**< \brief (PWM) PWM Disable Register */
    06861 #define REG_PWM_SR          REG_ACCESS(RoReg, 0x4002000CU) /**< \brief (PWM) PWM Status Register */
    06862 #define REG_PWM_IER1        REG_ACCESS(WoReg, 0x40020010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */
    06863 #define REG_PWM_IDR1        REG_ACCESS(WoReg, 0x40020014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */
    06864 #define REG_PWM_IMR1        REG_ACCESS(RoReg, 0x40020018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */
    06865 #define REG_PWM_ISR1        REG_ACCESS(RoReg, 0x4002001CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */
    06866 #define REG_PWM_SCM         REG_ACCESS(RwReg, 0x40020020U) /**< \brief (PWM) PWM Sync Channels Mode Register */
    06867 #define REG_PWM_SCUC        REG_ACCESS(RwReg, 0x40020028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */
    06868 #define REG_PWM_SCUP        REG_ACCESS(RwReg, 0x4002002CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */
    06869 #define REG_PWM_SCUPUPD     REG_ACCESS(WoReg, 0x40020030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */
    06870 #define REG_PWM_IER2        REG_ACCESS(WoReg, 0x40020034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */
    06871 #define REG_PWM_IDR2        REG_ACCESS(WoReg, 0x40020038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */
    06872 #define REG_PWM_IMR2        REG_ACCESS(RoReg, 0x4002003CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */
    06873 #define REG_PWM_ISR2        REG_ACCESS(RoReg, 0x40020040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */
    06874 #define REG_PWM_OOV         REG_ACCESS(RwReg, 0x40020044U) /**< \brief (PWM) PWM Output Override Value Register */
    06875 #define REG_PWM_OS          REG_ACCESS(RwReg, 0x40020048U) /**< \brief (PWM) PWM Output Selection Register */
    06876 #define REG_PWM_OSS         REG_ACCESS(WoReg, 0x4002004CU) /**< \brief (PWM) PWM Output Selection Set Register */
    06877 #define REG_PWM_OSC         REG_ACCESS(WoReg, 0x40020050U) /**< \brief (PWM) PWM Output Selection Clear Register */
    06878 #define REG_PWM_OSSUPD      REG_ACCESS(WoReg, 0x40020054U) /**< \brief (PWM) PWM Output Selection Set Update Register */
    06879 #define REG_PWM_OSCUPD      REG_ACCESS(WoReg, 0x40020058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */
    06880 #define REG_PWM_FMR         REG_ACCESS(RwReg, 0x4002005CU) /**< \brief (PWM) PWM Fault Mode Register */
    06881 #define REG_PWM_FSR         REG_ACCESS(RoReg, 0x40020060U) /**< \brief (PWM) PWM Fault Status Register */
    06882 #define REG_PWM_FCR         REG_ACCESS(WoReg, 0x40020064U) /**< \brief (PWM) PWM Fault Clear Register */
    06883 #define REG_PWM_FPV         REG_ACCESS(RwReg, 0x40020068U) /**< \brief (PWM) PWM Fault Protection Value Register */
    06884 #define REG_PWM_FPE         REG_ACCESS(RwReg, 0x4002006CU) /**< \brief (PWM) PWM Fault Protection Enable Register */
    06885 #define REG_PWM_ELMR        REG_ACCESS(RwReg, 0x4002007CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */
    06886 #define REG_PWM_SMMR        REG_ACCESS(RwReg, 0x400200B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */
    06887 #define REG_PWM_WPCR        REG_ACCESS(WoReg, 0x400200E4U) /**< \brief (PWM) PWM Write Protect Control Register */
    06888 #define REG_PWM_WPSR        REG_ACCESS(RoReg, 0x400200E8U) /**< \brief (PWM) PWM Write Protect Status Register */
    06889 #define REG_PWM_RPR         REG_ACCESS(RwReg, 0x40020100U) /**< \brief (PWM) Receive Pointer Register */
    06890 #define REG_PWM_RCR         REG_ACCESS(RwReg, 0x40020104U) /**< \brief (PWM) Receive Counter Register */
    06891 #define REG_PWM_TPR         REG_ACCESS(RwReg, 0x40020108U) /**< \brief (PWM) Transmit Pointer Register */
    06892 #define REG_PWM_TCR         REG_ACCESS(RwReg, 0x4002010CU) /**< \brief (PWM) Transmit Counter Register */
    06893 #define REG_PWM_RNPR        REG_ACCESS(RwReg, 0x40020110U) /**< \brief (PWM) Receive Next Pointer Register */
    06894 #define REG_PWM_RNCR        REG_ACCESS(RwReg, 0x40020114U) /**< \brief (PWM) Receive Next Counter Register */
    06895 #define REG_PWM_TNPR        REG_ACCESS(RwReg, 0x40020118U) /**< \brief (PWM) Transmit Next Pointer Register */
    06896 #define REG_PWM_TNCR        REG_ACCESS(RwReg, 0x4002011CU) /**< \brief (PWM) Transmit Next Counter Register */
    06897 #define REG_PWM_PTCR        REG_ACCESS(WoReg, 0x40020120U) /**< \brief (PWM) Transfer Control Register */
    06898 #define REG_PWM_PTSR        REG_ACCESS(RoReg, 0x40020124U) /**< \brief (PWM) Transfer Status Register */
    06899 #define REG_PWM_CMPV0       REG_ACCESS(RwReg, 0x40020130U) /**< \brief (PWM) PWM Comparison 0 Value Register */
    06900 #define REG_PWM_CMPVUPD0    REG_ACCESS(WoReg, 0x40020134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */
    06901 #define REG_PWM_CMPM0       REG_ACCESS(RwReg, 0x40020138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */
    06902 #define REG_PWM_CMPMUPD0    REG_ACCESS(WoReg, 0x4002013CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */
    06903 #define REG_PWM_CMPV1       REG_ACCESS(RwReg, 0x40020140U) /**< \brief (PWM) PWM Comparison 1 Value Register */
    06904 #define REG_PWM_CMPVUPD1    REG_ACCESS(WoReg, 0x40020144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */
    06905 #define REG_PWM_CMPM1       REG_ACCESS(RwReg, 0x40020148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */
    06906 #define REG_PWM_CMPMUPD1    REG_ACCESS(WoReg, 0x4002014CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */
    06907 #define REG_PWM_CMPV2       REG_ACCESS(RwReg, 0x40020150U) /**< \brief (PWM) PWM Comparison 2 Value Register */
    06908 #define REG_PWM_CMPVUPD2    REG_ACCESS(WoReg, 0x40020154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */
    06909 #define REG_PWM_CMPM2       REG_ACCESS(RwReg, 0x40020158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */
    06910 #define REG_PWM_CMPMUPD2    REG_ACCESS(WoReg, 0x4002015CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */
    06911 #define REG_PWM_CMPV3       REG_ACCESS(RwReg, 0x40020160U) /**< \brief (PWM) PWM Comparison 3 Value Register */
    06912 #define REG_PWM_CMPVUPD3    REG_ACCESS(WoReg, 0x40020164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */
    06913 #define REG_PWM_CMPM3       REG_ACCESS(RwReg, 0x40020168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */
    06914 #define REG_PWM_CMPMUPD3    REG_ACCESS(WoReg, 0x4002016CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */
    06915 #define REG_PWM_CMPV4       REG_ACCESS(RwReg, 0x40020170U) /**< \brief (PWM) PWM Comparison 4 Value Register */
    06916 #define REG_PWM_CMPVUPD4    REG_ACCESS(WoReg, 0x40020174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */
    06917 #define REG_PWM_CMPM4       REG_ACCESS(RwReg, 0x40020178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */
    06918 #define REG_PWM_CMPMUPD4    REG_ACCESS(WoReg, 0x4002017CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */
    06919 #define REG_PWM_CMPV5       REG_ACCESS(RwReg, 0x40020180U) /**< \brief (PWM) PWM Comparison 5 Value Register */
    06920 #define REG_PWM_CMPVUPD5    REG_ACCESS(WoReg, 0x40020184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */
    06921 #define REG_PWM_CMPM5       REG_ACCESS(RwReg, 0x40020188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */
    06922 #define REG_PWM_CMPMUPD5    REG_ACCESS(WoReg, 0x4002018CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */
    06923 #define REG_PWM_CMPV6       REG_ACCESS(RwReg, 0x40020190U) /**< \brief (PWM) PWM Comparison 6 Value Register */
    06924 #define REG_PWM_CMPVUPD6    REG_ACCESS(WoReg, 0x40020194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */
    06925 #define REG_PWM_CMPM6       REG_ACCESS(RwReg, 0x40020198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */
    06926 #define REG_PWM_CMPMUPD6    REG_ACCESS(WoReg, 0x4002019CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */
    06927 #define REG_PWM_CMPV7       REG_ACCESS(RwReg, 0x400201A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */
    06928 #define REG_PWM_CMPVUPD7    REG_ACCESS(WoReg, 0x400201A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */
    06929 #define REG_PWM_CMPM7       REG_ACCESS(RwReg, 0x400201A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */
    06930 #define REG_PWM_CMPMUPD7    REG_ACCESS(WoReg, 0x400201ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */
    06931 #define REG_PWM_CMR0        REG_ACCESS(RwReg, 0x40020200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */
    06932 #define REG_PWM_CDTY0       REG_ACCESS(RwReg, 0x40020204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */
    06933 #define REG_PWM_CDTYUPD0    REG_ACCESS(WoReg, 0x40020208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */
    06934 #define REG_PWM_CPRD0       REG_ACCESS(RwReg, 0x4002020CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */
    06935 #define REG_PWM_CPRDUPD0    REG_ACCESS(WoReg, 0x40020210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */
    06936 #define REG_PWM_CCNT0       REG_ACCESS(RoReg, 0x40020214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */
    06937 #define REG_PWM_DT0         REG_ACCESS(RwReg, 0x40020218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */
    06938 #define REG_PWM_DTUPD0      REG_ACCESS(WoReg, 0x4002021CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */
    06939 #define REG_PWM_CMR1        REG_ACCESS(RwReg, 0x40020220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */
    06940 #define REG_PWM_CDTY1       REG_ACCESS(RwReg, 0x40020224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */
    06941 #define REG_PWM_CDTYUPD1    REG_ACCESS(WoReg, 0x40020228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */
    06942 #define REG_PWM_CPRD1       REG_ACCESS(RwReg, 0x4002022CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */
    06943 #define REG_PWM_CPRDUPD1    REG_ACCESS(WoReg, 0x40020230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */
    06944 #define REG_PWM_CCNT1       REG_ACCESS(RoReg, 0x40020234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */
    06945 #define REG_PWM_DT1         REG_ACCESS(RwReg, 0x40020238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */
    06946 #define REG_PWM_DTUPD1      REG_ACCESS(WoReg, 0x4002023CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */
    06947 #define REG_PWM_CMR2        REG_ACCESS(RwReg, 0x40020240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */
    06948 #define REG_PWM_CDTY2       REG_ACCESS(RwReg, 0x40020244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */
    06949 #define REG_PWM_CDTYUPD2    REG_ACCESS(WoReg, 0x40020248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */
    06950 #define REG_PWM_CPRD2       REG_ACCESS(RwReg, 0x4002024CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */
    06951 #define REG_PWM_CPRDUPD2    REG_ACCESS(WoReg, 0x40020250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */
    06952 #define REG_PWM_CCNT2       REG_ACCESS(RoReg, 0x40020254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */
    06953 #define REG_PWM_DT2         REG_ACCESS(RwReg, 0x40020258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */
    06954 #define REG_PWM_DTUPD2      REG_ACCESS(WoReg, 0x4002025CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */
    06955 #define REG_PWM_CMR3        REG_ACCESS(RwReg, 0x40020260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */
    06956 #define REG_PWM_CDTY3       REG_ACCESS(RwReg, 0x40020264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */
    06957 #define REG_PWM_CDTYUPD3    REG_ACCESS(WoReg, 0x40020268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */
    06958 #define REG_PWM_CPRD3       REG_ACCESS(RwReg, 0x4002026CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */
    06959 #define REG_PWM_CPRDUPD3    REG_ACCESS(WoReg, 0x40020270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */
    06960 #define REG_PWM_CCNT3       REG_ACCESS(RoReg, 0x40020274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */
    06961 #define REG_PWM_DT3         REG_ACCESS(RwReg, 0x40020278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */
    06962 #define REG_PWM_DTUPD3      REG_ACCESS(WoReg, 0x4002027CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */
    06963 /* ========== Register definition for USART0 peripheral ========== */
    06964 #define REG_USART0_CR       REG_ACCESS(WoReg, 0x40024000U) /**< \brief (USART0) Control Register */
    06965 #define REG_USART0_MR       REG_ACCESS(RwReg, 0x40024004U) /**< \brief (USART0) Mode Register */
    06966 #define REG_USART0_IER      REG_ACCESS(WoReg, 0x40024008U) /**< \brief (USART0) Interrupt Enable Register */
    06967 #define REG_USART0_IDR      REG_ACCESS(WoReg, 0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */
    06968 #define REG_USART0_IMR      REG_ACCESS(RoReg, 0x40024010U) /**< \brief (USART0) Interrupt Mask Register */
    06969 #define REG_USART0_CSR      REG_ACCESS(RoReg, 0x40024014U) /**< \brief (USART0) Channel Status Register */
    06970 #define REG_USART0_RHR      REG_ACCESS(RoReg, 0x40024018U) /**< \brief (USART0) Receiver Holding Register */
    06971 #define REG_USART0_THR      REG_ACCESS(WoReg, 0x4002401CU) /**< \brief (USART0) Transmitter Holding Register */
    06972 #define REG_USART0_BRGR     REG_ACCESS(RwReg, 0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */
    06973 #define REG_USART0_RTOR     REG_ACCESS(RwReg, 0x40024024U) /**< \brief (USART0) Receiver Time-out Register */
    06974 #define REG_USART0_TTGR     REG_ACCESS(RwReg, 0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */
    06975 #define REG_USART0_FIDI     REG_ACCESS(RwReg, 0x40024040U) /**< \brief (USART0) FI DI Ratio Register */
    06976 #define REG_USART0_NER      REG_ACCESS(RoReg, 0x40024044U) /**< \brief (USART0) Number of Errors Register */
    06977 #define REG_USART0_IF       REG_ACCESS(RwReg, 0x4002404CU) /**< \brief (USART0) IrDA Filter Register */
    06978 #define REG_USART0_MAN      REG_ACCESS(RwReg, 0x40024050U) /**< \brief (USART0) Manchester Encoder Decoder Register */
    06979 #define REG_USART0_WPMR     REG_ACCESS(RwReg, 0x400240E4U) /**< \brief (USART0) Write Protect Mode Register */
    06980 #define REG_USART0_WPSR     REG_ACCESS(RoReg, 0x400240E8U) /**< \brief (USART0) Write Protect Status Register */
    06981 #define REG_USART0_VERSION  REG_ACCESS(RoReg, 0x400240FCU) /**< \brief (USART0) Version Register */
    06982 #define REG_USART0_RPR      REG_ACCESS(RwReg, 0x40024100U) /**< \brief (USART0) Receive Pointer Register */
    06983 #define REG_USART0_RCR      REG_ACCESS(RwReg, 0x40024104U) /**< \brief (USART0) Receive Counter Register */
    06984 #define REG_USART0_TPR      REG_ACCESS(RwReg, 0x40024108U) /**< \brief (USART0) Transmit Pointer Register */
    06985 #define REG_USART0_TCR      REG_ACCESS(RwReg, 0x4002410CU) /**< \brief (USART0) Transmit Counter Register */
    06986 #define REG_USART0_RNPR     REG_ACCESS(RwReg, 0x40024110U) /**< \brief (USART0) Receive Next Pointer Register */
    06987 #define REG_USART0_RNCR     REG_ACCESS(RwReg, 0x40024114U) /**< \brief (USART0) Receive Next Counter Register */
    06988 #define REG_USART0_TNPR     REG_ACCESS(RwReg, 0x40024118U) /**< \brief (USART0) Transmit Next Pointer Register */
    06989 #define REG_USART0_TNCR     REG_ACCESS(RwReg, 0x4002411CU) /**< \brief (USART0) Transmit Next Counter Register */
    06990 #define REG_USART0_PTCR     REG_ACCESS(WoReg, 0x40024120U) /**< \brief (USART0) Transfer Control Register */
    06991 #define REG_USART0_PTSR     REG_ACCESS(RoReg, 0x40024124U) /**< \brief (USART0) Transfer Status Register */
    06992 /* ========== Register definition for USART1 peripheral ========== */
    06993 #define REG_USART1_CR       REG_ACCESS(WoReg, 0x40028000U) /**< \brief (USART1) Control Register */
    06994 #define REG_USART1_MR       REG_ACCESS(RwReg, 0x40028004U) /**< \brief (USART1) Mode Register */
    06995 #define REG_USART1_IER      REG_ACCESS(WoReg, 0x40028008U) /**< \brief (USART1) Interrupt Enable Register */
    06996 #define REG_USART1_IDR      REG_ACCESS(WoReg, 0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */
    06997 #define REG_USART1_IMR      REG_ACCESS(RoReg, 0x40028010U) /**< \brief (USART1) Interrupt Mask Register */
    06998 #define REG_USART1_CSR      REG_ACCESS(RoReg, 0x40028014U) /**< \brief (USART1) Channel Status Register */
    06999 #define REG_USART1_RHR      REG_ACCESS(RoReg, 0x40028018U) /**< \brief (USART1) Receiver Holding Register */
    07000 #define REG_USART1_THR      REG_ACCESS(WoReg, 0x4002801CU) /**< \brief (USART1) Transmitter Holding Register */
    07001 #define REG_USART1_BRGR     REG_ACCESS(RwReg, 0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */
    07002 #define REG_USART1_RTOR     REG_ACCESS(RwReg, 0x40028024U) /**< \brief (USART1) Receiver Time-out Register */
    07003 #define REG_USART1_TTGR     REG_ACCESS(RwReg, 0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */
    07004 #define REG_USART1_FIDI     REG_ACCESS(RwReg, 0x40028040U) /**< \brief (USART1) FI DI Ratio Register */
    07005 #define REG_USART1_NER      REG_ACCESS(RoReg, 0x40028044U) /**< \brief (USART1) Number of Errors Register */
    07006 #define REG_USART1_IF       REG_ACCESS(RwReg, 0x4002804CU) /**< \brief (USART1) IrDA Filter Register */
    07007 #define REG_USART1_MAN      REG_ACCESS(RwReg, 0x40028050U) /**< \brief (USART1) Manchester Encoder Decoder Register */
    07008 #define REG_USART1_WPMR     REG_ACCESS(RwReg, 0x400280E4U) /**< \brief (USART1) Write Protect Mode Register */
    07009 #define REG_USART1_WPSR     REG_ACCESS(RoReg, 0x400280E8U) /**< \brief (USART1) Write Protect Status Register */
    07010 #define REG_USART1_VERSION  REG_ACCESS(RoReg, 0x400280FCU) /**< \brief (USART1) Version Register */
    07011 #define REG_USART1_RPR      REG_ACCESS(RwReg, 0x40028100U) /**< \brief (USART1) Receive Pointer Register */
    07012 #define REG_USART1_RCR      REG_ACCESS(RwReg, 0x40028104U) /**< \brief (USART1) Receive Counter Register */
    07013 #define REG_USART1_TPR      REG_ACCESS(RwReg, 0x40028108U) /**< \brief (USART1) Transmit Pointer Register */
    07014 #define REG_USART1_TCR      REG_ACCESS(RwReg, 0x4002810CU) /**< \brief (USART1) Transmit Counter Register */
    07015 #define REG_USART1_RNPR     REG_ACCESS(RwReg, 0x40028110U) /**< \brief (USART1) Receive Next Pointer Register */
    07016 #define REG_USART1_RNCR     REG_ACCESS(RwReg, 0x40028114U) /**< \brief (USART1) Receive Next Counter Register */
    07017 #define REG_USART1_TNPR     REG_ACCESS(RwReg, 0x40028118U) /**< \brief (USART1) Transmit Next Pointer Register */
    07018 #define REG_USART1_TNCR     REG_ACCESS(RwReg, 0x4002811CU) /**< \brief (USART1) Transmit Next Counter Register */
    07019 #define REG_USART1_PTCR     REG_ACCESS(WoReg, 0x40028120U) /**< \brief (USART1) Transfer Control Register */
    07020 #define REG_USART1_PTSR     REG_ACCESS(RoReg, 0x40028124U) /**< \brief (USART1) Transfer Status Register */
    07021 /* ========== Register definition for USART2 peripheral ========== */
    07022 #define REG_USART2_CR       REG_ACCESS(WoReg, 0x4002C000U) /**< \brief (USART2) Control Register */
    07023 #define REG_USART2_MR       REG_ACCESS(RwReg, 0x4002C004U) /**< \brief (USART2) Mode Register */
    07024 #define REG_USART2_IER      REG_ACCESS(WoReg, 0x4002C008U) /**< \brief (USART2) Interrupt Enable Register */
    07025 #define REG_USART2_IDR      REG_ACCESS(WoReg, 0x4002C00CU) /**< \brief (USART2) Interrupt Disable Register */
    07026 #define REG_USART2_IMR      REG_ACCESS(RoReg, 0x4002C010U) /**< \brief (USART2) Interrupt Mask Register */
    07027 #define REG_USART2_CSR      REG_ACCESS(RoReg, 0x4002C014U) /**< \brief (USART2) Channel Status Register */
    07028 #define REG_USART2_RHR      REG_ACCESS(RoReg, 0x4002C018U) /**< \brief (USART2) Receiver Holding Register */
    07029 #define REG_USART2_THR      REG_ACCESS(WoReg, 0x4002C01CU) /**< \brief (USART2) Transmitter Holding Register */
    07030 #define REG_USART2_BRGR     REG_ACCESS(RwReg, 0x4002C020U) /**< \brief (USART2) Baud Rate Generator Register */
    07031 #define REG_USART2_RTOR     REG_ACCESS(RwReg, 0x4002C024U) /**< \brief (USART2) Receiver Time-out Register */
    07032 #define REG_USART2_TTGR     REG_ACCESS(RwReg, 0x4002C028U) /**< \brief (USART2) Transmitter Timeguard Register */
    07033 #define REG_USART2_FIDI     REG_ACCESS(RwReg, 0x4002C040U) /**< \brief (USART2) FI DI Ratio Register */
    07034 #define REG_USART2_NER      REG_ACCESS(RoReg, 0x4002C044U) /**< \brief (USART2) Number of Errors Register */
    07035 #define REG_USART2_IF       REG_ACCESS(RwReg, 0x4002C04CU) /**< \brief (USART2) IrDA Filter Register */
    07036 #define REG_USART2_MAN      REG_ACCESS(RwReg, 0x4002C050U) /**< \brief (USART2) Manchester Encoder Decoder Register */
    07037 #define REG_USART2_WPMR     REG_ACCESS(RwReg, 0x4002C0E4U) /**< \brief (USART2) Write Protect Mode Register */
    07038 #define REG_USART2_WPSR     REG_ACCESS(RoReg, 0x4002C0E8U) /**< \brief (USART2) Write Protect Status Register */
    07039 #define REG_USART2_VERSION  REG_ACCESS(RoReg, 0x4002C0FCU) /**< \brief (USART2) Version Register */
    07040 #define REG_USART2_RPR      REG_ACCESS(RwReg, 0x4002C100U) /**< \brief (USART2) Receive Pointer Register */
    07041 #define REG_USART2_RCR      REG_ACCESS(RwReg, 0x4002C104U) /**< \brief (USART2) Receive Counter Register */
    07042 #define REG_USART2_TPR      REG_ACCESS(RwReg, 0x4002C108U) /**< \brief (USART2) Transmit Pointer Register */
    07043 #define REG_USART2_TCR      REG_ACCESS(RwReg, 0x4002C10CU) /**< \brief (USART2) Transmit Counter Register */
    07044 #define REG_USART2_RNPR     REG_ACCESS(RwReg, 0x4002C110U) /**< \brief (USART2) Receive Next Pointer Register */
    07045 #define REG_USART2_RNCR     REG_ACCESS(RwReg, 0x4002C114U) /**< \brief (USART2) Receive Next Counter Register */
    07046 #define REG_USART2_TNPR     REG_ACCESS(RwReg, 0x4002C118U) /**< \brief (USART2) Transmit Next Pointer Register */
    07047 #define REG_USART2_TNCR     REG_ACCESS(RwReg, 0x4002C11CU) /**< \brief (USART2) Transmit Next Counter Register */
    07048 #define REG_USART2_PTCR     REG_ACCESS(WoReg, 0x4002C120U) /**< \brief (USART2) Transfer Control Register */
    07049 #define REG_USART2_PTSR     REG_ACCESS(RoReg, 0x4002C124U) /**< \brief (USART2) Transfer Status Register */
    07050 /* ========== Register definition for UDP peripheral ========== */
    07051 #define REG_UDP_FRM_NUM     REG_ACCESS(RoReg, 0x40034000U) /**< \brief (UDP) Frame Number Register */
    07052 #define REG_UDP_GLB_STAT    REG_ACCESS(RwReg, 0x40034004U) /**< \brief (UDP) Global State Register */
    07053 #define REG_UDP_FADDR       REG_ACCESS(RwReg, 0x40034008U) /**< \brief (UDP) Function Address Register */
    07054 #define REG_UDP_IER         REG_ACCESS(WoReg, 0x40034010U) /**< \brief (UDP) Interrupt Enable Register */
    07055 #define REG_UDP_IDR         REG_ACCESS(WoReg, 0x40034014U) /**< \brief (UDP) Interrupt Disable Register */
    07056 #define REG_UDP_IMR         REG_ACCESS(RoReg, 0x40034018U) /**< \brief (UDP) Interrupt Mask Register */
    07057 #define REG_UDP_ISR         REG_ACCESS(RoReg, 0x4003401CU) /**< \brief (UDP) Interrupt Status Register */
    07058 #define REG_UDP_ICR         REG_ACCESS(WoReg, 0x40034020U) /**< \brief (UDP) Interrupt Clear Register */
    07059 #define REG_UDP_RST_EP      REG_ACCESS(RwReg, 0x40034028U) /**< \brief (UDP) Reset Endpoint Register */
    07060 #define REG_UDP_CSR         REG_ACCESS(RwReg, 0x40034030U) /**< \brief (UDP) Endpoint Control and Status Register */
    07061 #define REG_UDP_FDR         REG_ACCESS(RwReg, 0x40034050U) /**< \brief (UDP) Endpoint FIFO Data Register */
    07062 #define REG_UDP_TXVC        REG_ACCESS(RwReg, 0x40034074U) /**< \brief (UDP) Transceiver Control Register */
    07063 /* ========== Register definition for ADC peripheral ========== */
    07064 #define REG_ADC_CR          REG_ACCESS(WoReg, 0x40038000U) /**< \brief (ADC) Control Register */
    07065 #define REG_ADC_MR          REG_ACCESS(RwReg, 0x40038004U) /**< \brief (ADC) Mode Register */
    07066 #define REG_ADC_SEQR1       REG_ACCESS(RwReg, 0x40038008U) /**< \brief (ADC) Channel Sequence Register 1 */
    07067 #define REG_ADC_SEQR2       REG_ACCESS(RwReg, 0x4003800CU) /**< \brief (ADC) Channel Sequence Register 2 */
    07068 #define REG_ADC_CHER        REG_ACCESS(WoReg, 0x40038010U) /**< \brief (ADC) Channel Enable Register */
    07069 #define REG_ADC_CHDR        REG_ACCESS(WoReg, 0x40038014U) /**< \brief (ADC) Channel Disable Register */
    07070 #define REG_ADC_CHSR        REG_ACCESS(RoReg, 0x40038018U) /**< \brief (ADC) Channel Status Register */
    07071 #define REG_ADC_LCDR        REG_ACCESS(RoReg, 0x40038020U) /**< \brief (ADC) Last Converted Data Register */
    07072 #define REG_ADC_IER         REG_ACCESS(WoReg, 0x40038024U) /**< \brief (ADC) Interrupt Enable Register */
    07073 #define REG_ADC_IDR         REG_ACCESS(WoReg, 0x40038028U) /**< \brief (ADC) Interrupt Disable Register */
    07074 #define REG_ADC_IMR         REG_ACCESS(RoReg, 0x4003802CU) /**< \brief (ADC) Interrupt Mask Register */
    07075 #define REG_ADC_ISR         REG_ACCESS(RoReg, 0x40038030U) /**< \brief (ADC) Interrupt Status Register */
    07076 #define REG_ADC_OVER        REG_ACCESS(RoReg, 0x4003803CU) /**< \brief (ADC) Overrun Status Register */
    07077 #define REG_ADC_EMR         REG_ACCESS(RwReg, 0x40038040U) /**< \brief (ADC) Extended Mode Register */
    07078 #define REG_ADC_CWR         REG_ACCESS(RwReg, 0x40038044U) /**< \brief (ADC) Compare Window Register */
    07079 #define REG_ADC_CGR         REG_ACCESS(RwReg, 0x40038048U) /**< \brief (ADC) Channel Gain Register */
    07080 #define REG_ADC_COR         REG_ACCESS(RwReg, 0x4003804CU) /**< \brief (ADC) Channel Offset Register */
    07081 #define REG_ADC_CDR         REG_ACCESS(RoReg, 0x40038050U) /**< \brief (ADC) Channel Data Register */
    07082 #define REG_ADC_ACR         REG_ACCESS(RwReg, 0x40038094U) /**< \brief (ADC) Analog Control Register */
    07083 #define REG_ADC_WPMR        REG_ACCESS(RwReg, 0x400380E4U) /**< \brief (ADC) Write Protect Mode Register */
    07084 #define REG_ADC_WPSR        REG_ACCESS(RoReg, 0x400380E8U) /**< \brief (ADC) Write Protect Status Register */
    07085 #define REG_ADC_RPR         REG_ACCESS(RwReg, 0x40038100U) /**< \brief (ADC) Receive Pointer Register */
    07086 #define REG_ADC_RCR         REG_ACCESS(RwReg, 0x40038104U) /**< \brief (ADC) Receive Counter Register */
    07087 #define REG_ADC_TPR         REG_ACCESS(RwReg, 0x40038108U) /**< \brief (ADC) Transmit Pointer Register */
    07088 #define REG_ADC_TCR         REG_ACCESS(RwReg, 0x4003810CU) /**< \brief (ADC) Transmit Counter Register */
    07089 #define REG_ADC_RNPR        REG_ACCESS(RwReg, 0x40038110U) /**< \brief (ADC) Receive Next Pointer Register */
    07090 #define REG_ADC_RNCR        REG_ACCESS(RwReg, 0x40038114U) /**< \brief (ADC) Receive Next Counter Register */
    07091 #define REG_ADC_TNPR        REG_ACCESS(RwReg, 0x40038118U) /**< \brief (ADC) Transmit Next Pointer Register */
    07092 #define REG_ADC_TNCR        REG_ACCESS(RwReg, 0x4003811CU) /**< \brief (ADC) Transmit Next Counter Register */
    07093 #define REG_ADC_PTCR        REG_ACCESS(WoReg, 0x40038120U) /**< \brief (ADC) Transfer Control Register */
    07094 #define REG_ADC_PTSR        REG_ACCESS(RoReg, 0x40038124U) /**< \brief (ADC) Transfer Status Register */
    07095 /* ========== Register definition for DACC peripheral ========== */
    07096 #define REG_DACC_CR         REG_ACCESS(WoReg, 0x4003C000U) /**< \brief (DACC) Control Register */
    07097 #define REG_DACC_MR         REG_ACCESS(RwReg, 0x4003C004U) /**< \brief (DACC) Mode Register */
    07098 #define REG_DACC_CHER       REG_ACCESS(WoReg, 0x4003C010U) /**< \brief (DACC) Channel Enable Register */
    07099 #define REG_DACC_CHDR       REG_ACCESS(WoReg, 0x4003C014U) /**< \brief (DACC) Channel Disable Register */
    07100 #define REG_DACC_CHSR       REG_ACCESS(RoReg, 0x4003C018U) /**< \brief (DACC) Channel Status Register */
    07101 #define REG_DACC_CDR        REG_ACCESS(WoReg, 0x4003C020U) /**< \brief (DACC) Conversion Data Register */
    07102 #define REG_DACC_IER        REG_ACCESS(WoReg, 0x4003C024U) /**< \brief (DACC) Interrupt Enable Register */
    07103 #define REG_DACC_IDR        REG_ACCESS(WoReg, 0x4003C028U) /**< \brief (DACC) Interrupt Disable Register */
    07104 #define REG_DACC_IMR        REG_ACCESS(RoReg, 0x4003C02CU) /**< \brief (DACC) Interrupt Mask Register */
    07105 #define REG_DACC_ISR        REG_ACCESS(RoReg, 0x4003C030U) /**< \brief (DACC) Interrupt Status Register */
    07106 #define REG_DACC_ACR        REG_ACCESS(RwReg, 0x4003C094U) /**< \brief (DACC) Analog Current Register */
    07107 #define REG_DACC_WPMR       REG_ACCESS(RwReg, 0x4003C0E4U) /**< \brief (DACC) Write Protect Mode register */
    07108 #define REG_DACC_WPSR       REG_ACCESS(RoReg, 0x4003C0E8U) /**< \brief (DACC) Write Protect Status register */
    07109 #define REG_DACC_RPR        REG_ACCESS(RwReg, 0x4003C100U) /**< \brief (DACC) Receive Pointer Register */
    07110 #define REG_DACC_RCR        REG_ACCESS(RwReg, 0x4003C104U) /**< \brief (DACC) Receive Counter Register */
    07111 #define REG_DACC_TPR        REG_ACCESS(RwReg, 0x4003C108U) /**< \brief (DACC) Transmit Pointer Register */
    07112 #define REG_DACC_TCR        REG_ACCESS(RwReg, 0x4003C10CU) /**< \brief (DACC) Transmit Counter Register */
    07113 #define REG_DACC_RNPR       REG_ACCESS(RwReg, 0x4003C110U) /**< \brief (DACC) Receive Next Pointer Register */
    07114 #define REG_DACC_RNCR       REG_ACCESS(RwReg, 0x4003C114U) /**< \brief (DACC) Receive Next Counter Register */
    07115 #define REG_DACC_TNPR       REG_ACCESS(RwReg, 0x4003C118U) /**< \brief (DACC) Transmit Next Pointer Register */
    07116 #define REG_DACC_TNCR       REG_ACCESS(RwReg, 0x4003C11CU) /**< \brief (DACC) Transmit Next Counter Register */
    07117 #define REG_DACC_PTCR       REG_ACCESS(WoReg, 0x4003C120U) /**< \brief (DACC) Transfer Control Register */
    07118 #define REG_DACC_PTSR       REG_ACCESS(RoReg, 0x4003C124U) /**< \brief (DACC) Transfer Status Register */
    07119 /* ========== Register definition for ACC peripheral ========== */
    07120 #define REG_ACC_CR          REG_ACCESS(WoReg, 0x40040000U) /**< \brief (ACC) Control Register */
    07121 #define REG_ACC_MR          REG_ACCESS(RwReg, 0x40040004U) /**< \brief (ACC) Mode Register */
    07122 #define REG_ACC_IER         REG_ACCESS(WoReg, 0x40040024U) /**< \brief (ACC) Interrupt Enable Register */
    07123 #define REG_ACC_IDR         REG_ACCESS(WoReg, 0x40040028U) /**< \brief (ACC) Interrupt Disable Register */
    07124 #define REG_ACC_IMR         REG_ACCESS(RoReg, 0x4004002CU) /**< \brief (ACC) Interrupt Mask Register */
    07125 #define REG_ACC_ISR         REG_ACCESS(RoReg, 0x40040030U) /**< \brief (ACC) Interrupt Status Register */
    07126 #define REG_ACC_ACR         REG_ACCESS(RwReg, 0x40040094U) /**< \brief (ACC) Analog Control Register */
    07127 #define REG_ACC_WPMR        REG_ACCESS(RwReg, 0x400400E4U) /**< \brief (ACC) Write Protect Mode Register */
    07128 #define REG_ACC_WPSR        REG_ACCESS(RoReg, 0x400400E8U) /**< \brief (ACC) Write Protect Status Register */
    07129 /* ========== Register definition for CRCCU peripheral ========== */
    07130 #define REG_CRCCU_DSCR      REG_ACCESS(RwReg, 0x40044000U) /**< \brief (CRCCU) CRCCU Descriptor Base Register */
    07131 #define REG_CRCCU_DMA_EN    REG_ACCESS(WoReg, 0x40044008U) /**< \brief (CRCCU) CRCCU DMA Enable Register */
    07132 #define REG_CRCCU_DMA_DIS   REG_ACCESS(WoReg, 0x4004400CU) /**< \brief (CRCCU) CRCCU DMA Disable Register */
    07133 #define REG_CRCCU_DMA_SR    REG_ACCESS(RoReg, 0x40044010U) /**< \brief (CRCCU) CRCCU DMA Status Register */
    07134 #define REG_CRCCU_DMA_IER   REG_ACCESS(WoReg, 0x40044014U) /**< \brief (CRCCU) CRCCU DMA Interrupt Enable Register */
    07135 #define REG_CRCCU_DMA_IDR   REG_ACCESS(WoReg, 0x40044018U) /**< \brief (CRCCU) CRCCU DMA Interrupt Disable Register */
    07136 #define REG_CRCCU_DMA_IMR   REG_ACCESS(RoReg, 0x4004401CU) /**< \brief (CRCCU) CRCCU DMA Interrupt Mask Register */
    07137 #define REG_CRCCU_DMA_ISR   REG_ACCESS(RoReg, 0x40044020U) /**< \brief (CRCCU) CRCCU DMA Interrupt Status Register */
    07138 #define REG_CRCCU_CR        REG_ACCESS(WoReg, 0x40044034U) /**< \brief (CRCCU) CRCCU Control Register */
    07139 #define REG_CRCCU_MR        REG_ACCESS(RwReg, 0x40044038U) /**< \brief (CRCCU) CRCCU Mode Register */
    07140 #define REG_CRCCU_SR        REG_ACCESS(RoReg, 0x4004403CU) /**< \brief (CRCCU) CRCCU Status Register */
    07141 #define REG_CRCCU_IER       REG_ACCESS(WoReg, 0x40044040U) /**< \brief (CRCCU) CRCCU Interrupt Enable Register */
    07142 #define REG_CRCCU_IDR       REG_ACCESS(WoReg, 0x40044044U) /**< \brief (CRCCU) CRCCU Interrupt Disable Register */
    07143 #define REG_CRCCU_IMR       REG_ACCESS(RoReg, 0x40044048U) /**< \brief (CRCCU) CRCCU Interrupt Mask Register */
    07144 #define REG_CRCCU_ISR       REG_ACCESS(RoReg, 0x4004404CU) /**< \brief (CRCCU) CRCCU Interrupt Status Register */
    07145 /* ========== Register definition for SMC peripheral ========== */
    07146 #define REG_SMC_SETUP0      REG_ACCESS(RwReg, 0x400E0000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */
    07147 #define REG_SMC_PULSE0      REG_ACCESS(RwReg, 0x400E0004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */
    07148 #define REG_SMC_CYCLE0      REG_ACCESS(RwReg, 0x400E0008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */
    07149 #define REG_SMC_MODE0       REG_ACCESS(RwReg, 0x400E000CU) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */
    07150 #define REG_SMC_SETUP1      REG_ACCESS(RwReg, 0x400E0010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */
    07151 #define REG_SMC_PULSE1      REG_ACCESS(RwReg, 0x400E0014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */
    07152 #define REG_SMC_CYCLE1      REG_ACCESS(RwReg, 0x400E0018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */
    07153 #define REG_SMC_MODE1       REG_ACCESS(RwReg, 0x400E001CU) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */
    07154 #define REG_SMC_SETUP2      REG_ACCESS(RwReg, 0x400E0020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */
    07155 #define REG_SMC_PULSE2      REG_ACCESS(RwReg, 0x400E0024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */
    07156 #define REG_SMC_CYCLE2      REG_ACCESS(RwReg, 0x400E0028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */
    07157 #define REG_SMC_MODE2       REG_ACCESS(RwReg, 0x400E002CU) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */
    07158 #define REG_SMC_SETUP3      REG_ACCESS(RwReg, 0x400E0030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */
    07159 #define REG_SMC_PULSE3      REG_ACCESS(RwReg, 0x400E0034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */
    07160 #define REG_SMC_CYCLE3      REG_ACCESS(RwReg, 0x400E0038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */
    07161 #define REG_SMC_MODE3       REG_ACCESS(RwReg, 0x400E003CU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */
    07162 #define REG_SMC_SETUP4      REG_ACCESS(RwReg, 0x400E0040U) /**< \brief (SMC) SMC Setup Register (CS_number = 4) */
    07163 #define REG_SMC_PULSE4      REG_ACCESS(RwReg, 0x400E0044U) /**< \brief (SMC) SMC Pulse Register (CS_number = 4) */
    07164 #define REG_SMC_CYCLE4      REG_ACCESS(RwReg, 0x400E0048U) /**< \brief (SMC) SMC Cycle Register (CS_number = 4) */
    07165 #define REG_SMC_MODE4       REG_ACCESS(RwReg, 0x400E004CU) /**< \brief (SMC) SMC Mode Register (CS_number = 4) */
    07166 #define REG_SMC_OCMS        REG_ACCESS(RwReg, 0x400E0080U) /**< \brief (SMC) SMC OCMS MODE Register */
    07167 #define REG_SMC_KEY1        REG_ACCESS(WoReg, 0x400E0084U) /**< \brief (SMC) SMC OCMS KEY1 Register */
    07168 #define REG_SMC_KEY2        REG_ACCESS(WoReg, 0x400E0088U) /**< \brief (SMC) SMC OCMS KEY2 Register */
    07169 #define REG_SMC_WPMR        REG_ACCESS(RwReg, 0x400E00E4U) /**< \brief (SMC) SMC Write Protect Mode Register */
    07170 #define REG_SMC_WPSR        REG_ACCESS(RoReg, 0x400E00E8U) /**< \brief (SMC) SMC Write Protect Status Register */
    07171 /* ========== Register definition for MATRIX peripheral ========== */
    07172 #define REG_MATRIX_MCFG     REG_ACCESS(RwReg, 0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */
    07173 #define REG_MATRIX_SCFG     REG_ACCESS(RwReg, 0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */
    07174 #define REG_MATRIX_PRAS0    REG_ACCESS(RwReg, 0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */
    07175 #define REG_MATRIX_PRAS1    REG_ACCESS(RwReg, 0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */
    07176 #define REG_MATRIX_PRAS2    REG_ACCESS(RwReg, 0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */
    07177 #define REG_MATRIX_PRAS3    REG_ACCESS(RwReg, 0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */
    07178 #define REG_MATRIX_PRAS4    REG_ACCESS(RwReg, 0x400E02A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */
    07179 #define REG_CCFG_SYSIO      REG_ACCESS(RwReg, 0x400E0314U) /**< \brief (MATRIX) System I/O Configuration register */
    07180 #define REG_CCFG_SMCNFCS    REG_ACCESS(RwReg, 0x400E031CU) /**< \brief (MATRIX) SMC Chip Select NAND Flash Assignment Register */
    07181 #define REG_MATRIX_WPMR     REG_ACCESS(RwReg, 0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */
    07182 #define REG_MATRIX_WPSR     REG_ACCESS(RoReg, 0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */
    07183 /* ========== Register definition for PMC peripheral ========== */
    07184 #define REG_PMC_SCER        REG_ACCESS(WoReg, 0x400E0400U) /**< \brief (PMC) System Clock Enable Register */
    07185 #define REG_PMC_SCDR        REG_ACCESS(WoReg, 0x400E0404U) /**< \brief (PMC) System Clock Disable Register */
    07186 #define REG_PMC_SCSR        REG_ACCESS(RoReg, 0x400E0408U) /**< \brief (PMC) System Clock Status Register */
    07187 #define REG_PMC_PCER0       REG_ACCESS(WoReg, 0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */
    07188 #define REG_PMC_PCDR0       REG_ACCESS(WoReg, 0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */
    07189 #define REG_PMC_PCSR0       REG_ACCESS(RoReg, 0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */
    07190 #define REG_CKGR_MOR        REG_ACCESS(RwReg, 0x400E0420U) /**< \brief (PMC) Main Oscillator Register */
    07191 #define REG_CKGR_MCFR       REG_ACCESS(RoReg, 0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */
    07192 #define REG_CKGR_PLLAR      REG_ACCESS(RwReg, 0x400E0428U) /**< \brief (PMC) PLLA Register */
    07193 #define REG_CKGR_PLLBR      REG_ACCESS(RwReg, 0x400E042CU) /**< \brief (PMC) PLLB Register */
    07194 #define REG_PMC_MCKR        REG_ACCESS(RwReg, 0x400E0430U) /**< \brief (PMC) Master Clock Register */
    07195 #define REG_PMC_USB         REG_ACCESS(RwReg, 0x400E0438U) /**< \brief (PMC) USB Clock Register */
    07196 #define REG_PMC_PCK         REG_ACCESS(RwReg, 0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */
    07197 #define REG_PMC_IER         REG_ACCESS(WoReg, 0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */
    07198 #define REG_PMC_IDR         REG_ACCESS(WoReg, 0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */
    07199 #define REG_PMC_SR          REG_ACCESS(RoReg, 0x400E0468U) /**< \brief (PMC) Status Register */
    07200 #define REG_PMC_IMR         REG_ACCESS(RoReg, 0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */
    07201 #define REG_PMC_FSMR        REG_ACCESS(RwReg, 0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */
    07202 #define REG_PMC_FSPR        REG_ACCESS(RwReg, 0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */
    07203 #define REG_PMC_FOCR        REG_ACCESS(WoReg, 0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */
    07204 #define REG_PMC_WPMR        REG_ACCESS(RwReg, 0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */
    07205 #define REG_PMC_WPSR        REG_ACCESS(RoReg, 0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */
    07206 #define REG_PMC_PCER1       REG_ACCESS(WoReg, 0x400E0500U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */
    07207 #define REG_PMC_PCDR1       REG_ACCESS(WoReg, 0x400E0504U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */
    07208 #define REG_PMC_PCSR1       REG_ACCESS(RoReg, 0x400E0508U) /**< \brief (PMC) Peripheral Clock Status Register 1 */
    07209 #define REG_PMC_OCR         REG_ACCESS(RwReg, 0x400E0510U) /**< \brief (PMC) Oscillator Calibration Register */
    07210 /* ========== Register definition for UART0 peripheral ========== */
    07211 #define REG_UART0_CR        REG_ACCESS(WoReg, 0x400E0600U) /**< \brief (UART0) Control Register */
    07212 #define REG_UART0_MR        REG_ACCESS(RwReg, 0x400E0604U) /**< \brief (UART0) Mode Register */
    07213 #define REG_UART0_IER       REG_ACCESS(WoReg, 0x400E0608U) /**< \brief (UART0) Interrupt Enable Register */
    07214 #define REG_UART0_IDR       REG_ACCESS(WoReg, 0x400E060CU) /**< \brief (UART0) Interrupt Disable Register */
    07215 #define REG_UART0_IMR       REG_ACCESS(RoReg, 0x400E0610U) /**< \brief (UART0) Interrupt Mask Register */
    07216 #define REG_UART0_SR        REG_ACCESS(RoReg, 0x400E0614U) /**< \brief (UART0) Status Register */
    07217 #define REG_UART0_RHR       REG_ACCESS(RoReg, 0x400E0618U) /**< \brief (UART0) Receive Holding Register */
    07218 #define REG_UART0_THR       REG_ACCESS(WoReg, 0x400E061CU) /**< \brief (UART0) Transmit Holding Register */
    07219 #define REG_UART0_BRGR      REG_ACCESS(RwReg, 0x400E0620U) /**< \brief (UART0) Baud Rate Generator Register */
    07220 #define REG_UART0_RPR       REG_ACCESS(RwReg, 0x400E0700U) /**< \brief (UART0) Receive Pointer Register */
    07221 #define REG_UART0_RCR       REG_ACCESS(RwReg, 0x400E0704U) /**< \brief (UART0) Receive Counter Register */
    07222 #define REG_UART0_TPR       REG_ACCESS(RwReg, 0x400E0708U) /**< \brief (UART0) Transmit Pointer Register */
    07223 #define REG_UART0_TCR       REG_ACCESS(RwReg, 0x400E070CU) /**< \brief (UART0) Transmit Counter Register */
    07224 #define REG_UART0_RNPR      REG_ACCESS(RwReg, 0x400E0710U) /**< \brief (UART0) Receive Next Pointer Register */
    07225 #define REG_UART0_RNCR      REG_ACCESS(RwReg, 0x400E0714U) /**< \brief (UART0) Receive Next Counter Register */
    07226 #define REG_UART0_TNPR      REG_ACCESS(RwReg, 0x400E0718U) /**< \brief (UART0) Transmit Next Pointer Register */
    07227 #define REG_UART0_TNCR      REG_ACCESS(RwReg, 0x400E071CU) /**< \brief (UART0) Transmit Next Counter Register */
    07228 #define REG_UART0_PTCR      REG_ACCESS(WoReg, 0x400E0720U) /**< \brief (UART0) Transfer Control Register */
    07229 #define REG_UART0_PTSR      REG_ACCESS(RoReg, 0x400E0724U) /**< \brief (UART0) Transfer Status Register */
    07230 /* ========== Register definition for CHIPID peripheral ========== */
    07231 #define REG_CHIPID_CIDR     REG_ACCESS(RoReg, 0x400E0740U) /**< \brief (CHIPID) Chip ID Register */
    07232 #define REG_CHIPID_EXID     REG_ACCESS(RoReg, 0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */
    07233 /* ========== Register definition for UART1 peripheral ========== */
    07234 #define REG_UART1_CR        REG_ACCESS(WoReg, 0x400E0800U) /**< \brief (UART1) Control Register */
    07235 #define REG_UART1_MR        REG_ACCESS(RwReg, 0x400E0804U) /**< \brief (UART1) Mode Register */
    07236 #define REG_UART1_IER       REG_ACCESS(WoReg, 0x400E0808U) /**< \brief (UART1) Interrupt Enable Register */
    07237 #define REG_UART1_IDR       REG_ACCESS(WoReg, 0x400E080CU) /**< \brief (UART1) Interrupt Disable Register */
    07238 #define REG_UART1_IMR       REG_ACCESS(RoReg, 0x400E0810U) /**< \brief (UART1) Interrupt Mask Register */
    07239 #define REG_UART1_SR        REG_ACCESS(RoReg, 0x400E0814U) /**< \brief (UART1) Status Register */
    07240 #define REG_UART1_RHR       REG_ACCESS(RoReg, 0x400E0818U) /**< \brief (UART1) Receive Holding Register */
    07241 #define REG_UART1_THR       REG_ACCESS(WoReg, 0x400E081CU) /**< \brief (UART1) Transmit Holding Register */
    07242 #define REG_UART1_BRGR      REG_ACCESS(RwReg, 0x400E0820U) /**< \brief (UART1) Baud Rate Generator Register */
    07243 #define REG_UART1_RPR       REG_ACCESS(RwReg, 0x400E0900U) /**< \brief (UART1) Receive Pointer Register */
    07244 #define REG_UART1_RCR       REG_ACCESS(RwReg, 0x400E0904U) /**< \brief (UART1) Receive Counter Register */
    07245 #define REG_UART1_TPR       REG_ACCESS(RwReg, 0x400E0908U) /**< \brief (UART1) Transmit Pointer Register */
    07246 #define REG_UART1_TCR       REG_ACCESS(RwReg, 0x400E090CU) /**< \brief (UART1) Transmit Counter Register */
    07247 #define REG_UART1_RNPR      REG_ACCESS(RwReg, 0x400E0910U) /**< \brief (UART1) Receive Next Pointer Register */
    07248 #define REG_UART1_RNCR      REG_ACCESS(RwReg, 0x400E0914U) /**< \brief (UART1) Receive Next Counter Register */
    07249 #define REG_UART1_TNPR      REG_ACCESS(RwReg, 0x400E0918U) /**< \brief (UART1) Transmit Next Pointer Register */
    07250 #define REG_UART1_TNCR      REG_ACCESS(RwReg, 0x400E091CU) /**< \brief (UART1) Transmit Next Counter Register */
    07251 #define REG_UART1_PTCR      REG_ACCESS(WoReg, 0x400E0920U) /**< \brief (UART1) Transfer Control Register */
    07252 #define REG_UART1_PTSR      REG_ACCESS(RoReg, 0x400E0924U) /**< \brief (UART1) Transfer Status Register */
    07253 /* ========== Register definition for EFC peripheral ========== */
    07254 #define REG_EFC_FMR         REG_ACCESS(RwReg, 0x400E0A00U) /**< \brief (EFC) EEFC Flash Mode Register */
    07255 #define REG_EFC_FCR         REG_ACCESS(WoReg, 0x400E0A04U) /**< \brief (EFC) EEFC Flash Command Register */
    07256 #define REG_EFC_FSR         REG_ACCESS(RoReg, 0x400E0A08U) /**< \brief (EFC) EEFC Flash Status Register */
    07257 #define REG_EFC_FRR         REG_ACCESS(RoReg, 0x400E0A0CU) /**< \brief (EFC) EEFC Flash Result Register */
    07258 /* ========== Register definition for PIOA peripheral ========== */
    07259 #define REG_PIOA_PER        REG_ACCESS(WoReg, 0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */
    07260 #define REG_PIOA_PDR        REG_ACCESS(WoReg, 0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */
    07261 #define REG_PIOA_PSR        REG_ACCESS(RoReg, 0x400E0E08U) /**< \brief (PIOA) PIO Status Register */
    07262 #define REG_PIOA_OER        REG_ACCESS(WoReg, 0x400E0E10U) /**< \brief (PIOA) Output Enable Register */
    07263 #define REG_PIOA_ODR        REG_ACCESS(WoReg, 0x400E0E14U) /**< \brief (PIOA) Output Disable Register */
    07264 #define REG_PIOA_OSR        REG_ACCESS(RoReg, 0x400E0E18U) /**< \brief (PIOA) Output Status Register */
    07265 #define REG_PIOA_IFER       REG_ACCESS(WoReg, 0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */
    07266 #define REG_PIOA_IFDR       REG_ACCESS(WoReg, 0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */
    07267 #define REG_PIOA_IFSR       REG_ACCESS(RoReg, 0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */
    07268 #define REG_PIOA_SODR       REG_ACCESS(WoReg, 0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */
    07269 #define REG_PIOA_CODR       REG_ACCESS(WoReg, 0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */
    07270 #define REG_PIOA_ODSR       REG_ACCESS(RwReg, 0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */
    07271 #define REG_PIOA_PDSR       REG_ACCESS(RoReg, 0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */
    07272 #define REG_PIOA_IER        REG_ACCESS(WoReg, 0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */
    07273 #define REG_PIOA_IDR        REG_ACCESS(WoReg, 0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */
    07274 #define REG_PIOA_IMR        REG_ACCESS(RoReg, 0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */
    07275 #define REG_PIOA_ISR        REG_ACCESS(RoReg, 0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */
    07276 #define REG_PIOA_MDER       REG_ACCESS(WoReg, 0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */
    07277 #define REG_PIOA_MDDR       REG_ACCESS(WoReg, 0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */
    07278 #define REG_PIOA_MDSR       REG_ACCESS(RoReg, 0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */
    07279 #define REG_PIOA_PUDR       REG_ACCESS(WoReg, 0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */
    07280 #define REG_PIOA_PUER       REG_ACCESS(WoReg, 0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */
    07281 #define REG_PIOA_PUSR       REG_ACCESS(RoReg, 0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */
    07282 #define REG_PIOA_ABCDSR     REG_ACCESS(RwReg, 0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */
    07283 #define REG_PIOA_IFSCDR     REG_ACCESS(WoReg, 0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */
    07284 #define REG_PIOA_IFSCER     REG_ACCESS(WoReg, 0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */
    07285 #define REG_PIOA_IFSCSR     REG_ACCESS(RoReg, 0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */
    07286 #define REG_PIOA_SCDR       REG_ACCESS(RwReg, 0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */
    07287 #define REG_PIOA_PPDDR      REG_ACCESS(WoReg, 0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */
    07288 #define REG_PIOA_PPDER      REG_ACCESS(WoReg, 0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */
    07289 #define REG_PIOA_PPDSR      REG_ACCESS(RoReg, 0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */
    07290 #define REG_PIOA_OWER       REG_ACCESS(WoReg, 0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */
    07291 #define REG_PIOA_OWDR       REG_ACCESS(WoReg, 0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */
    07292 #define REG_PIOA_OWSR       REG_ACCESS(RoReg, 0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */
    07293 #define REG_PIOA_AIMER      REG_ACCESS(WoReg, 0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */
    07294 #define REG_PIOA_AIMDR      REG_ACCESS(WoReg, 0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */
    07295 #define REG_PIOA_AIMMR      REG_ACCESS(RoReg, 0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */
    07296 #define REG_PIOA_ESR        REG_ACCESS(WoReg, 0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */
    07297 #define REG_PIOA_LSR        REG_ACCESS(WoReg, 0x400E0EC4U) /**< \brief (PIOA) Level Select Register */
    07298 #define REG_PIOA_ELSR       REG_ACCESS(RoReg, 0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */
    07299 #define REG_PIOA_FELLSR     REG_ACCESS(WoReg, 0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */
    07300 #define REG_PIOA_REHLSR     REG_ACCESS(WoReg, 0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */
    07301 #define REG_PIOA_FRLHSR     REG_ACCESS(RoReg, 0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */
    07302 #define REG_PIOA_LOCKSR     REG_ACCESS(RoReg, 0x400E0EE0U) /**< \brief (PIOA) Lock Status */
    07303 #define REG_PIOA_WPMR       REG_ACCESS(RwReg, 0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */
    07304 #define REG_PIOA_WPSR       REG_ACCESS(RoReg, 0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */
    07305 #define REG_PIOA_SCHMITT    REG_ACCESS(RwReg, 0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */
    07306 #define REG_PIOA_PCMR       REG_ACCESS(RwReg, 0x400E0F50U) /**< \brief (PIOA) Parallel Capture Mode Register */
    07307 #define REG_PIOA_PCIER      REG_ACCESS(WoReg, 0x400E0F54U) /**< \brief (PIOA) Parallel Capture Interrupt Enable Register */
    07308 #define REG_PIOA_PCIDR      REG_ACCESS(WoReg, 0x400E0F58U) /**< \brief (PIOA) Parallel Capture Interrupt Disable Register */
    07309 #define REG_PIOA_PCIMR      REG_ACCESS(RoReg, 0x400E0F5CU) /**< \brief (PIOA) Parallel Capture Interrupt Mask Register */
    07310 #define REG_PIOA_PCISR      REG_ACCESS(RoReg, 0x400E0F60U) /**< \brief (PIOA) Parallel Capture Interrupt Status Register */
    07311 #define REG_PIOA_PCRHR      REG_ACCESS(RoReg, 0x400E0F64U) /**< \brief (PIOA) Parallel Capture Reception Holding Register */
    07312 #define REG_PIOA_RPR        REG_ACCESS(RwReg, 0x400E0F68U) /**< \brief (PIOA) Receive Pointer Register */
    07313 #define REG_PIOA_RCR        REG_ACCESS(RwReg, 0x400E0F6CU) /**< \brief (PIOA) Receive Counter Register */
    07314 #define REG_PIOA_TPR        REG_ACCESS(RwReg, 0x400E0F70U) /**< \brief (PIOA) Transmit Pointer Register */
    07315 #define REG_PIOA_TCR        REG_ACCESS(RwReg, 0x400E0F74U) /**< \brief (PIOA) Transmit Counter Register */
    07316 #define REG_PIOA_RNPR       REG_ACCESS(RwReg, 0x400E0F78U) /**< \brief (PIOA) Receive Next Pointer Register */
    07317 #define REG_PIOA_RNCR       REG_ACCESS(RwReg, 0x400E0F7CU) /**< \brief (PIOA) Receive Next Counter Register */
    07318 #define REG_PIOA_TNPR       REG_ACCESS(RwReg, 0x400E0F80U) /**< \brief (PIOA) Transmit Next Pointer Register */
    07319 #define REG_PIOA_TNCR       REG_ACCESS(RwReg, 0x400E0F84U) /**< \brief (PIOA) Transmit Next Counter Register */
    07320 #define REG_PIOA_PTCR       REG_ACCESS(WoReg, 0x400E0F88U) /**< \brief (PIOA) Transfer Control Register */
    07321 #define REG_PIOA_PTSR       REG_ACCESS(RoReg, 0x400E0F8CU) /**< \brief (PIOA) Transfer Status Register */
    07322 /* ========== Register definition for PIOB peripheral ========== */
    07323 #define REG_PIOB_PER        REG_ACCESS(WoReg, 0x400E1000U) /**< \brief (PIOB) PIO Enable Register */
    07324 #define REG_PIOB_PDR        REG_ACCESS(WoReg, 0x400E1004U) /**< \brief (PIOB) PIO Disable Register */
    07325 #define REG_PIOB_PSR        REG_ACCESS(RoReg, 0x400E1008U) /**< \brief (PIOB) PIO Status Register */
    07326 #define REG_PIOB_OER        REG_ACCESS(WoReg, 0x400E1010U) /**< \brief (PIOB) Output Enable Register */
    07327 #define REG_PIOB_ODR        REG_ACCESS(WoReg, 0x400E1014U) /**< \brief (PIOB) Output Disable Register */
    07328 #define REG_PIOB_OSR        REG_ACCESS(RoReg, 0x400E1018U) /**< \brief (PIOB) Output Status Register */
    07329 #define REG_PIOB_IFER       REG_ACCESS(WoReg, 0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */
    07330 #define REG_PIOB_IFDR       REG_ACCESS(WoReg, 0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */
    07331 #define REG_PIOB_IFSR       REG_ACCESS(RoReg, 0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */
    07332 #define REG_PIOB_SODR       REG_ACCESS(WoReg, 0x400E1030U) /**< \brief (PIOB) Set Output Data Register */
    07333 #define REG_PIOB_CODR       REG_ACCESS(WoReg, 0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */
    07334 #define REG_PIOB_ODSR       REG_ACCESS(RwReg, 0x400E1038U) /**< \brief (PIOB) Output Data Status Register */
    07335 #define REG_PIOB_PDSR       REG_ACCESS(RoReg, 0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */
    07336 #define REG_PIOB_IER        REG_ACCESS(WoReg, 0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */
    07337 #define REG_PIOB_IDR        REG_ACCESS(WoReg, 0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */
    07338 #define REG_PIOB_IMR        REG_ACCESS(RoReg, 0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */
    07339 #define REG_PIOB_ISR        REG_ACCESS(RoReg, 0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */
    07340 #define REG_PIOB_MDER       REG_ACCESS(WoReg, 0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */
    07341 #define REG_PIOB_MDDR       REG_ACCESS(WoReg, 0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */
    07342 #define REG_PIOB_MDSR       REG_ACCESS(RoReg, 0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */
    07343 #define REG_PIOB_PUDR       REG_ACCESS(WoReg, 0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */
    07344 #define REG_PIOB_PUER       REG_ACCESS(WoReg, 0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */
    07345 #define REG_PIOB_PUSR       REG_ACCESS(RoReg, 0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */
    07346 #define REG_PIOB_ABCDSR     REG_ACCESS(RwReg, 0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */
    07347 #define REG_PIOB_IFSCDR     REG_ACCESS(WoReg, 0x400E1080U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */
    07348 #define REG_PIOB_IFSCER     REG_ACCESS(WoReg, 0x400E1084U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */
    07349 #define REG_PIOB_IFSCSR     REG_ACCESS(RoReg, 0x400E1088U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */
    07350 #define REG_PIOB_SCDR       REG_ACCESS(RwReg, 0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */
    07351 #define REG_PIOB_PPDDR      REG_ACCESS(WoReg, 0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */
    07352 #define REG_PIOB_PPDER      REG_ACCESS(WoReg, 0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */
    07353 #define REG_PIOB_PPDSR      REG_ACCESS(RoReg, 0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */
    07354 #define REG_PIOB_OWER       REG_ACCESS(WoReg, 0x400E10A0U) /**< \brief (PIOB) Output Write Enable */
    07355 #define REG_PIOB_OWDR       REG_ACCESS(WoReg, 0x400E10A4U) /**< \brief (PIOB) Output Write Disable */
    07356 #define REG_PIOB_OWSR       REG_ACCESS(RoReg, 0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */
    07357 #define REG_PIOB_AIMER      REG_ACCESS(WoReg, 0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */
    07358 #define REG_PIOB_AIMDR      REG_ACCESS(WoReg, 0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */
    07359 #define REG_PIOB_AIMMR      REG_ACCESS(RoReg, 0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */
    07360 #define REG_PIOB_ESR        REG_ACCESS(WoReg, 0x400E10C0U) /**< \brief (PIOB) Edge Select Register */
    07361 #define REG_PIOB_LSR        REG_ACCESS(WoReg, 0x400E10C4U) /**< \brief (PIOB) Level Select Register */
    07362 #define REG_PIOB_ELSR       REG_ACCESS(RoReg, 0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */
    07363 #define REG_PIOB_FELLSR     REG_ACCESS(WoReg, 0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */
    07364 #define REG_PIOB_REHLSR     REG_ACCESS(WoReg, 0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */
    07365 #define REG_PIOB_FRLHSR     REG_ACCESS(RoReg, 0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */
    07366 #define REG_PIOB_LOCKSR     REG_ACCESS(RoReg, 0x400E10E0U) /**< \brief (PIOB) Lock Status */
    07367 #define REG_PIOB_WPMR       REG_ACCESS(RwReg, 0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */
    07368 #define REG_PIOB_WPSR       REG_ACCESS(RoReg, 0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */
    07369 #define REG_PIOB_SCHMITT    REG_ACCESS(RwReg, 0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */
    07370 #define REG_PIOB_PCMR       REG_ACCESS(RwReg, 0x400E1150U) /**< \brief (PIOB) Parallel Capture Mode Register */
    07371 #define REG_PIOB_PCIER      REG_ACCESS(WoReg, 0x400E1154U) /**< \brief (PIOB) Parallel Capture Interrupt Enable Register */
    07372 #define REG_PIOB_PCIDR      REG_ACCESS(WoReg, 0x400E1158U) /**< \brief (PIOB) Parallel Capture Interrupt Disable Register */
    07373 #define REG_PIOB_PCIMR      REG_ACCESS(RoReg, 0x400E115CU) /**< \brief (PIOB) Parallel Capture Interrupt Mask Register */
    07374 #define REG_PIOB_PCISR      REG_ACCESS(RoReg, 0x400E1160U) /**< \brief (PIOB) Parallel Capture Interrupt Status Register */
    07375 #define REG_PIOB_PCRHR      REG_ACCESS(RoReg, 0x400E1164U) /**< \brief (PIOB) Parallel Capture Reception Holding Register */
    07376 /* ========== Register definition for PIOC peripheral ========== */
    07377 #define REG_PIOC_PER        REG_ACCESS(WoReg, 0x400E1200U) /**< \brief (PIOC) PIO Enable Register */
    07378 #define REG_PIOC_PDR        REG_ACCESS(WoReg, 0x400E1204U) /**< \brief (PIOC) PIO Disable Register */
    07379 #define REG_PIOC_PSR        REG_ACCESS(RoReg, 0x400E1208U) /**< \brief (PIOC) PIO Status Register */
    07380 #define REG_PIOC_OER        REG_ACCESS(WoReg, 0x400E1210U) /**< \brief (PIOC) Output Enable Register */
    07381 #define REG_PIOC_ODR        REG_ACCESS(WoReg, 0x400E1214U) /**< \brief (PIOC) Output Disable Register */
    07382 #define REG_PIOC_OSR        REG_ACCESS(RoReg, 0x400E1218U) /**< \brief (PIOC) Output Status Register */
    07383 #define REG_PIOC_IFER       REG_ACCESS(WoReg, 0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */
    07384 #define REG_PIOC_IFDR       REG_ACCESS(WoReg, 0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */
    07385 #define REG_PIOC_IFSR       REG_ACCESS(RoReg, 0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */
    07386 #define REG_PIOC_SODR       REG_ACCESS(WoReg, 0x400E1230U) /**< \brief (PIOC) Set Output Data Register */
    07387 #define REG_PIOC_CODR       REG_ACCESS(WoReg, 0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */
    07388 #define REG_PIOC_ODSR       REG_ACCESS(RwReg, 0x400E1238U) /**< \brief (PIOC) Output Data Status Register */
    07389 #define REG_PIOC_PDSR       REG_ACCESS(RoReg, 0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */
    07390 #define REG_PIOC_IER        REG_ACCESS(WoReg, 0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */
    07391 #define REG_PIOC_IDR        REG_ACCESS(WoReg, 0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */
    07392 #define REG_PIOC_IMR        REG_ACCESS(RoReg, 0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */
    07393 #define REG_PIOC_ISR        REG_ACCESS(RoReg, 0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */
    07394 #define REG_PIOC_MDER       REG_ACCESS(WoReg, 0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */
    07395 #define REG_PIOC_MDDR       REG_ACCESS(WoReg, 0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */
    07396 #define REG_PIOC_MDSR       REG_ACCESS(RoReg, 0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */
    07397 #define REG_PIOC_PUDR       REG_ACCESS(WoReg, 0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */
    07398 #define REG_PIOC_PUER       REG_ACCESS(WoReg, 0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */
    07399 #define REG_PIOC_PUSR       REG_ACCESS(RoReg, 0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */
    07400 #define REG_PIOC_ABCDSR     REG_ACCESS(RwReg, 0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */
    07401 #define REG_PIOC_IFSCDR     REG_ACCESS(WoReg, 0x400E1280U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */
    07402 #define REG_PIOC_IFSCER     REG_ACCESS(WoReg, 0x400E1284U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */
    07403 #define REG_PIOC_IFSCSR     REG_ACCESS(RoReg, 0x400E1288U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */
    07404 #define REG_PIOC_SCDR       REG_ACCESS(RwReg, 0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */
    07405 #define REG_PIOC_PPDDR      REG_ACCESS(WoReg, 0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */
    07406 #define REG_PIOC_PPDER      REG_ACCESS(WoReg, 0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */
    07407 #define REG_PIOC_PPDSR      REG_ACCESS(RoReg, 0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */
    07408 #define REG_PIOC_OWER       REG_ACCESS(WoReg, 0x400E12A0U) /**< \brief (PIOC) Output Write Enable */
    07409 #define REG_PIOC_OWDR       REG_ACCESS(WoReg, 0x400E12A4U) /**< \brief (PIOC) Output Write Disable */
    07410 #define REG_PIOC_OWSR       REG_ACCESS(RoReg, 0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */
    07411 #define REG_PIOC_AIMER      REG_ACCESS(WoReg, 0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */
    07412 #define REG_PIOC_AIMDR      REG_ACCESS(WoReg, 0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */
    07413 #define REG_PIOC_AIMMR      REG_ACCESS(RoReg, 0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */
    07414 #define REG_PIOC_ESR        REG_ACCESS(WoReg, 0x400E12C0U) /**< \brief (PIOC) Edge Select Register */
    07415 #define REG_PIOC_LSR        REG_ACCESS(WoReg, 0x400E12C4U) /**< \brief (PIOC) Level Select Register */
    07416 #define REG_PIOC_ELSR       REG_ACCESS(RoReg, 0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */
    07417 #define REG_PIOC_FELLSR     REG_ACCESS(WoReg, 0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */
    07418 #define REG_PIOC_REHLSR     REG_ACCESS(WoReg, 0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */
    07419 #define REG_PIOC_FRLHSR     REG_ACCESS(RoReg, 0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */
    07420 #define REG_PIOC_LOCKSR     REG_ACCESS(RoReg, 0x400E12E0U) /**< \brief (PIOC) Lock Status */
    07421 #define REG_PIOC_WPMR       REG_ACCESS(RwReg, 0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */
    07422 #define REG_PIOC_WPSR       REG_ACCESS(RoReg, 0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */
    07423 #define REG_PIOC_SCHMITT    REG_ACCESS(RwReg, 0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */
    07424 #define REG_PIOC_PCMR       REG_ACCESS(RwReg, 0x400E1350U) /**< \brief (PIOC) Parallel Capture Mode Register */
    07425 #define REG_PIOC_PCIER      REG_ACCESS(WoReg, 0x400E1354U) /**< \brief (PIOC) Parallel Capture Interrupt Enable Register */
    07426 #define REG_PIOC_PCIDR      REG_ACCESS(WoReg, 0x400E1358U) /**< \brief (PIOC) Parallel Capture Interrupt Disable Register */
    07427 #define REG_PIOC_PCIMR      REG_ACCESS(RoReg, 0x400E135CU) /**< \brief (PIOC) Parallel Capture Interrupt Mask Register */
    07428 #define REG_PIOC_PCISR      REG_ACCESS(RoReg, 0x400E1360U) /**< \brief (PIOC) Parallel Capture Interrupt Status Register */
    07429 #define REG_PIOC_PCRHR      REG_ACCESS(RoReg, 0x400E1364U) /**< \brief (PIOC) Parallel Capture Reception Holding Register */
    07430 /* ========== Register definition for RSTC peripheral ========== */
    07431 #define REG_RSTC_CR         REG_ACCESS(WoReg, 0x400E1400U) /**< \brief (RSTC) Control Register */
    07432 #define REG_RSTC_SR         REG_ACCESS(RoReg, 0x400E1404U) /**< \brief (RSTC) Status Register */
    07433 #define REG_RSTC_MR         REG_ACCESS(RwReg, 0x400E1408U) /**< \brief (RSTC) Mode Register */
    07434 /* ========== Register definition for SUPC peripheral ========== */
    07435 #define REG_SUPC_CR         REG_ACCESS(WoReg, 0x400E1410U) /**< \brief (SUPC) Supply Controller Control Register */
    07436 #define REG_SUPC_SMMR       REG_ACCESS(RwReg, 0x400E1414U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */
    07437 #define REG_SUPC_MR         REG_ACCESS(RwReg, 0x400E1418U) /**< \brief (SUPC) Supply Controller Mode Register */
    07438 #define REG_SUPC_WUMR       REG_ACCESS(RwReg, 0x400E141CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */
    07439 #define REG_SUPC_WUIR       REG_ACCESS(RwReg, 0x400E1420U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */
    07440 #define REG_SUPC_SR         REG_ACCESS(RoReg, 0x400E1424U) /**< \brief (SUPC) Supply Controller Status Register */
    07441 /* ========== Register definition for RTT peripheral ========== */
    07442 #define REG_RTT_MR          REG_ACCESS(RwReg, 0x400E1430U) /**< \brief (RTT) Mode Register */
    07443 #define REG_RTT_AR          REG_ACCESS(RwReg, 0x400E1434U) /**< \brief (RTT) Alarm Register */
    07444 #define REG_RTT_VR          REG_ACCESS(RoReg, 0x400E1438U) /**< \brief (RTT) Value Register */
    07445 #define REG_RTT_SR          REG_ACCESS(RoReg, 0x400E143CU) /**< \brief (RTT) Status Register */
    07446 /* ========== Register definition for WDT peripheral ========== */
    07447 #define REG_WDT_CR          REG_ACCESS(WoReg, 0x400E1450U) /**< \brief (WDT) Control Register */
    07448 #define REG_WDT_MR          REG_ACCESS(RwReg, 0x400E1454U) /**< \brief (WDT) Mode Register */
    07449 #define REG_WDT_SR          REG_ACCESS(RoReg, 0x400E1458U) /**< \brief (WDT) Status Register */
    07450 /* ========== Register definition for RTC peripheral ========== */
    07451 #define REG_RTC_CR          REG_ACCESS(RwReg, 0x400E1460U) /**< \brief (RTC) Control Register */
    07452 #define REG_RTC_MR          REG_ACCESS(RwReg, 0x400E1464U) /**< \brief (RTC) Mode Register */
    07453 #define REG_RTC_TIMR        REG_ACCESS(RwReg, 0x400E1468U) /**< \brief (RTC) Time Register */
    07454 #define REG_RTC_CALR        REG_ACCESS(RwReg, 0x400E146CU) /**< \brief (RTC) Calendar Register */
    07455 #define REG_RTC_TIMALR      REG_ACCESS(RwReg, 0x400E1470U) /**< \brief (RTC) Time Alarm Register */
    07456 #define REG_RTC_CALALR      REG_ACCESS(RwReg, 0x400E1474U) /**< \brief (RTC) Calendar Alarm Register */
    07457 #define REG_RTC_SR          REG_ACCESS(RoReg, 0x400E1478U) /**< \brief (RTC) Status Register */
    07458 #define REG_RTC_SCCR        REG_ACCESS(WoReg, 0x400E147CU) /**< \brief (RTC) Status Clear Command Register */
    07459 #define REG_RTC_IER         REG_ACCESS(WoReg, 0x400E1480U) /**< \brief (RTC) Interrupt Enable Register */
    07460 #define REG_RTC_IDR         REG_ACCESS(WoReg, 0x400E1484U) /**< \brief (RTC) Interrupt Disable Register */
    07461 #define REG_RTC_IMR         REG_ACCESS(RoReg, 0x400E1488U) /**< \brief (RTC) Interrupt Mask Register */
    07462 #define REG_RTC_VER         REG_ACCESS(RoReg, 0x400E148CU) /**< \brief (RTC) Valid Entry Register */
    07463 /* ========== Register definition for GPBR peripheral ========== */
    07464 #define REG_GPBR_GPBR0      REG_ACCESS(RwReg, 0x400E1490U) /**< \brief (GPBR) General Purpose Backup Register 0 */
    07465 #define REG_GPBR_GPBR1      REG_ACCESS(RwReg, 0x400E1494U) /**< \brief (GPBR) General Purpose Backup Register 1 */
    07466 #define REG_GPBR_GPBR2      REG_ACCESS(RwReg, 0x400E1498U) /**< \brief (GPBR) General Purpose Backup Register 2 */
    07467 #define REG_GPBR_GPBR3      REG_ACCESS(RwReg, 0x400E149CU) /**< \brief (GPBR) General Purpose Backup Register 3 */
    07468 #define REG_GPBR_GPBR4      REG_ACCESS(RwReg, 0x400E14A0U) /**< \brief (GPBR) General Purpose Backup Register 4 */
    07469 #define REG_GPBR_GPBR5      REG_ACCESS(RwReg, 0x400E14A4U) /**< \brief (GPBR) General Purpose Backup Register 5 */
    07470 #define REG_GPBR_GPBR6      REG_ACCESS(RwReg, 0x400E14A8U) /**< \brief (GPBR) General Purpose Backup Register 6 */
    07471 #define REG_GPBR_GPBR7      REG_ACCESS(RwReg, 0x400E14ACU) /**< \brief (GPBR) General Purpose Backup Register 7 */
    07472 /*@}*/
    07473
    07474 /* ************************************************************************** */
    07475 /*   PERIPHERAL ID DEFINITIONS FOR SAM3S8 */
    07476 /* ************************************************************************** */
    07477 /** \addtogroup SAM3S8_id Peripheral Ids Definitions */
    07478 /*@{*/
    07479
    07480 #define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
    07481 #define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
    07482 #define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
    07483 #define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
    07484 #define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
    07485 #define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
    07486 #define ID_EFC    ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
    07487 #define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
    07488 #define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
    07489 #define ID_SMC    (10) /**< \brief Static Memory Controller (SMC) */
    07490 #define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
    07491 #define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
    07492 #define ID_PIOC   (13) /**< \brief Parallel I/O Controller C (PIOC) */
    07493 #define ID_USART0 (14) /**< \brief USART 0 (USART0) */
    07494 #define ID_USART1 (15) /**< \brief USART 1 (USART1) */
    07495 #define ID_USART2 (16) /**< \brief USART 2 (SAM3SD8 100 pins only) (USART2) */
    07496 #define ID_HSMCI  (18) /**< \brief Multimedia Card Interface (HSMCI) */
    07497 #define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
    07498 #define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
    07499 #define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
    07500 #define ID_SSC    (22) /**< \brief Synchronous Serial Controler (SSC) */
    07501 #define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
    07502 #define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
    07503 #define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
    07504 #define ID_TC3    (26) /**< \brief Timer/Counter 3 (TC3) */
    07505 #define ID_TC4    (27) /**< \brief Timer/Counter 4 (TC4) */
    07506 #define ID_TC5    (28) /**< \brief Timer/Counter 5 (TC5) */
    07507 #define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
    07508 #define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
    07509 #define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
    07510 #define ID_CRCCU  (32) /**< \brief CRC Calculation Unit (CRCCU) */
    07511 #define ID_ACC    (33) /**< \brief Analog Comparator (ACC) */
    07512 #define ID_UDP    (34) /**< \brief USB Device Port (UDP) */
    07513 /*@}*/
    07514
    07515 /* ************************************************************************** */
    07516 /*   BASE ADDRESS DEFINITIONS FOR SAM3S8 */
    07517 /* ************************************************************************** */
    07518 /** \addtogroup SAM3S8_base Peripheral Base Address Definitions */
    07519 /*@{*/
    07520
    07521 #define HSMCI      CAST(Hsmci     , 0x40000000U) /**< \brief (HSMCI     ) Base Address */
    07522 #define PDC_HSMCI  CAST(Pdc       , 0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
    07523 #define SSC        CAST(Ssc       , 0x40004000U) /**< \brief (SSC       ) Base Address */
    07524 #define PDC_SSC    CAST(Pdc       , 0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
    07525 #define SPI        CAST(Spi       , 0x40008000U) /**< \brief (SPI       ) Base Address */
    07526 #define PDC_SPI    CAST(Pdc       , 0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
    07527 #define TC0        CAST(Tc        , 0x40010000U) /**< \brief (TC0       ) Base Address */
    07528 #define TC1        CAST(Tc        , 0x40014000U) /**< \brief (TC1       ) Base Address */
    07529 #define TWI0       CAST(Twi       , 0x40018000U) /**< \brief (TWI0      ) Base Address */
    07530 #define PDC_TWI0   CAST(Pdc       , 0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
    07531 #define TWI1       CAST(Twi       , 0x4001C000U) /**< \brief (TWI1      ) Base Address */
    07532 #define PDC_TWI1   CAST(Pdc       , 0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
    07533 #define PWM        CAST(Pwm       , 0x40020000U) /**< \brief (PWM       ) Base Address */
    07534 #define PDC_PWM    CAST(Pdc       , 0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
    07535 #define USART0     CAST(Usart     , 0x40024000U) /**< \brief (USART0    ) Base Address */
    07536 #define PDC_USART0 CAST(Pdc       , 0x40024100U) /**< \brief (PDC_USART0) Base Address */
    07537 #define USART1     CAST(Usart     , 0x40028000U) /**< \brief (USART1    ) Base Address */
    07538 #define PDC_USART1 CAST(Pdc       , 0x40028100U) /**< \brief (PDC_USART1) Base Address */
    07539 #define USART2     CAST(Usart     , 0x4002C000U) /**< \brief (USART2    ) Base Address */
    07540 #define PDC_USART2 CAST(Pdc       , 0x4002C100U) /**< \brief (PDC_USART2) Base Address */
    07541 #define UDP        CAST(Udp       , 0x40034000U) /**< \brief (UDP       ) Base Address */
    07542 #define ADC        CAST(Adc       , 0x40038000U) /**< \brief (ADC       ) Base Address */
    07543 #define PDC_ADC    CAST(Pdc       , 0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
    07544 #define DACC       CAST(Dacc      , 0x4003C000U) /**< \brief (DACC      ) Base Address */
    07545 #define PDC_DACC   CAST(Pdc       , 0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
    07546 #define ACC        CAST(Acc       , 0x40040000U) /**< \brief (ACC       ) Base Address */
    07547 #define CRCCU      CAST(Crccu     , 0x40044000U) /**< \brief (CRCCU     ) Base Address */
    07548 #define SMC        CAST(Smc       , 0x400E0000U) /**< \brief (SMC       ) Base Address */
    07549 #define MATRIX     CAST(Matrix    , 0x400E0200U) /**< \brief (MATRIX    ) Base Address */
    07550 #define PMC        CAST(Pmc       , 0x400E0400U) /**< \brief (PMC       ) Base Address */
    07551 #define UART0      CAST(Uart      , 0x400E0600U) /**< \brief (UART0     ) Base Address */
    07552 #define PDC_UART0  CAST(Pdc       , 0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
    07553 #define CHIPID     CAST(Chipid    , 0x400E0740U) /**< \brief (CHIPID    ) Base Address */
    07554 #define UART1      CAST(Uart      , 0x400E0800U) /**< \brief (UART1     ) Base Address */
    07555 #define PDC_UART1  CAST(Pdc       , 0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
    07556 #define EFC        CAST(Efc       , 0x400E0A00U) /**< \brief (EFC       ) Base Address */
    07557 #define PIOA       CAST(Pio       , 0x400E0E00U) /**< \brief (PIOA      ) Base Address */
    07558 #define PDC_PIOA   CAST(Pdc       , 0x400E0F00U) /**< \brief (PDC_PIOA  ) Base Address */
    07559 #define PIOB       CAST(Pio       , 0x400E1000U) /**< \brief (PIOB      ) Base Address */
    07560 #define PIOC       CAST(Pio       , 0x400E1200U) /**< \brief (PIOC      ) Base Address */
    07561 #define RSTC       CAST(Rstc      , 0x400E1400U) /**< \brief (RSTC      ) Base Address */
    07562 #define SUPC       CAST(Supc      , 0x400E1410U) /**< \brief (SUPC      ) Base Address */
    07563 #define RTT        CAST(Rtt       , 0x400E1430U) /**< \brief (RTT       ) Base Address */
    07564 #define WDT        CAST(Wdt       , 0x400E1450U) /**< \brief (WDT       ) Base Address */
    07565 #define RTC        CAST(Rtc       , 0x400E1460U) /**< \brief (RTC       ) Base Address */
    07566 #define GPBR       CAST(Gpbr      , 0x400E1490U) /**< \brief (GPBR      ) Base Address */
    07567 /*@}*/
    07568
    07569 /* ************************************************************************** */
    07570 /*   PIO DEFINITIONS FOR SAM3S8 */
    07571 /* ************************************************************************** */
    07572 /** \addtogroup SAM3S8_pio Peripheral Pio Definitions */
    07573 /*@{*/
    07574
    07575 #define PIO_PA0                (1u << 0) /**< \brief Pin Controlled by PA0 */
    07576 #define PIO_PA1                (1u << 1) /**< \brief Pin Controlled by PA1 */
    07577 #define PIO_PA2                (1u << 2) /**< \brief Pin Controlled by PA2 */
    07578 #define PIO_PA3                (1u << 3) /**< \brief Pin Controlled by PA3 */
    07579 #define PIO_PA4                (1u << 4) /**< \brief Pin Controlled by PA4 */
    07580 #define PIO_PA5                (1u << 5) /**< \brief Pin Controlled by PA5 */
    07581 #define PIO_PA6                (1u << 6) /**< \brief Pin Controlled by PA6 */
    07582 #define PIO_PA7                (1u << 7) /**< \brief Pin Controlled by PA7 */
    07583 #define PIO_PA8                (1u << 8) /**< \brief Pin Controlled by PA8 */
    07584 #define PIO_PA9                (1u << 9) /**< \brief Pin Controlled by PA9 */
    07585 #define PIO_PA10               (1u << 10) /**< \brief Pin Controlled by PA10 */
    07586 #define PIO_PA11               (1u << 11) /**< \brief Pin Controlled by PA11 */
    07587 #define PIO_PA12               (1u << 12) /**< \brief Pin Controlled by PA12 */
    07588 #define PIO_PA13               (1u << 13) /**< \brief Pin Controlled by PA13 */
    07589 #define PIO_PA14               (1u << 14) /**< \brief Pin Controlled by PA14 */
    07590 #define PIO_PA15               (1u << 15) /**< \brief Pin Controlled by PA15 */
    07591 #define PIO_PA16               (1u << 16) /**< \brief Pin Controlled by PA16 */
    07592 #define PIO_PA17               (1u << 17) /**< \brief Pin Controlled by PA17 */
    07593 #define PIO_PA18               (1u << 18) /**< \brief Pin Controlled by PA18 */
    07594 #define PIO_PA19               (1u << 19) /**< \brief Pin Controlled by PA19 */
    07595 #define PIO_PA20               (1u << 20) /**< \brief Pin Controlled by PA20 */
    07596 #define PIO_PA21               (1u << 21) /**< \brief Pin Controlled by PA21 */
    07597 #define PIO_PA22               (1u << 22) /**< \brief Pin Controlled by PA22 */
    07598 #define PIO_PA23               (1u << 23) /**< \brief Pin Controlled by PA23 */
    07599 #define PIO_PA24               (1u << 24) /**< \brief Pin Controlled by PA24 */
    07600 #define PIO_PA25               (1u << 25) /**< \brief Pin Controlled by PA25 */
    07601 #define PIO_PA26               (1u << 26) /**< \brief Pin Controlled by PA26 */
    07602 #define PIO_PA27               (1u << 27) /**< \brief Pin Controlled by PA27 */
    07603 #define PIO_PA28               (1u << 28) /**< \brief Pin Controlled by PA28 */
    07604 #define PIO_PA29               (1u << 29) /**< \brief Pin Controlled by PA29 */
    07605 #define PIO_PA30               (1u << 30) /**< \brief Pin Controlled by PA30 */
    07606 #define PIO_PA31               (1u << 31) /**< \brief Pin Controlled by PA31 */
    07607 #define PIO_PB0                (1u << 0) /**< \brief Pin Controlled by PB0 */
    07608 #define PIO_PB1                (1u << 1) /**< \brief Pin Controlled by PB1 */
    07609 #define PIO_PB2                (1u << 2) /**< \brief Pin Controlled by PB2 */
    07610 #define PIO_PB3                (1u << 3) /**< \brief Pin Controlled by PB3 */
    07611 #define PIO_PB4                (1u << 4) /**< \brief Pin Controlled by PB4 */
    07612 #define PIO_PB5                (1u << 5) /**< \brief Pin Controlled by PB5 */
    07613 #define PIO_PB6                (1u << 6) /**< \brief Pin Controlled by PB6 */
    07614 #define PIO_PB7                (1u << 7) /**< \brief Pin Controlled by PB7 */
    07615 #define PIO_PB8                (1u << 8) /**< \brief Pin Controlled by PB8 */
    07616 #define PIO_PB9                (1u << 9) /**< \brief Pin Controlled by PB9 */
    07617 #define PIO_PB10               (1u << 10) /**< \brief Pin Controlled by PB10 */
    07618 #define PIO_PB11               (1u << 11) /**< \brief Pin Controlled by PB11 */
    07619 #define PIO_PB12               (1u << 12) /**< \brief Pin Controlled by PB12 */
    07620 #define PIO_PB13               (1u << 13) /**< \brief Pin Controlled by PB13 */
    07621 #define PIO_PB14               (1u << 14) /**< \brief Pin Controlled by PB14 */
    07622 #define PIO_PC0                (1u << 0) /**< \brief Pin Controlled by PC0 */
    07623 #define PIO_PC1                (1u << 1) /**< \brief Pin Controlled by PC1 */
    07624 #define PIO_PC2                (1u << 2) /**< \brief Pin Controlled by PC2 */
    07625 #define PIO_PC3                (1u << 3) /**< \brief Pin Controlled by PC3 */
    07626 #define PIO_PC4                (1u << 4) /**< \brief Pin Controlled by PC4 */
    07627 #define PIO_PC5                (1u << 5) /**< \brief Pin Controlled by PC5 */
    07628 #define PIO_PC6                (1u << 6) /**< \brief Pin Controlled by PC6 */
    07629 #define PIO_PC7                (1u << 7) /**< \brief Pin Controlled by PC7 */
    07630 #define PIO_PC8                (1u << 8) /**< \brief Pin Controlled by PC8 */
    07631 #define PIO_PC9                (1u << 9) /**< \brief Pin Controlled by PC9 */
    07632 #define PIO_PC10               (1u << 10) /**< \brief Pin Controlled by PC10 */
    07633 #define PIO_PC11               (1u << 11) /**< \brief Pin Controlled by PC11 */
    07634 #define PIO_PC12               (1u << 12) /**< \brief Pin Controlled by PC12 */
    07635 #define PIO_PC13               (1u << 13) /**< \brief Pin Controlled by PC13 */
    07636 #define PIO_PC14               (1u << 14) /**< \brief Pin Controlled by PC14 */
    07637 #define PIO_PC15               (1u << 15) /**< \brief Pin Controlled by PC15 */
    07638 #define PIO_PC16               (1u << 16) /**< \brief Pin Controlled by PC16 */
    07639 #define PIO_PC17               (1u << 17) /**< \brief Pin Controlled by PC17 */
    07640 #define PIO_PC18               (1u << 18) /**< \brief Pin Controlled by PC18 */
    07641 #define PIO_PC19               (1u << 19) /**< \brief Pin Controlled by PC19 */
    07642 #define PIO_PC20               (1u << 20) /**< \brief Pin Controlled by PC20 */
    07643 #define PIO_PC21               (1u << 21) /**< \brief Pin Controlled by PC21 */
    07644 #define PIO_PC22               (1u << 22) /**< \brief Pin Controlled by PC22 */
    07645 #define PIO_PC23               (1u << 23) /**< \brief Pin Controlled by PC23 */
    07646 #define PIO_PC24               (1u << 24) /**< \brief Pin Controlled by PC24 */
    07647 #define PIO_PC25               (1u << 25) /**< \brief Pin Controlled by PC25 */
    07648 #define PIO_PC26               (1u << 26) /**< \brief Pin Controlled by PC26 */
    07649 #define PIO_PC27               (1u << 27) /**< \brief Pin Controlled by PC27 */
    07650 #define PIO_PC28               (1u << 28) /**< \brief Pin Controlled by PC28 */
    07651 #define PIO_PC29               (1u << 29) /**< \brief Pin Controlled by PC29 */
    07652 #define PIO_PC30               (1u << 30) /**< \brief Pin Controlled by PC30 */
    07653 #define PIO_PC31               (1u << 31) /**< \brief Pin Controlled by PC31 */
    07654 /* ========== Pio definition for ADC peripheral ========== */
    07655 #define PIO_PA17X1_AD0       (1u << 17)  /**< \brief Adc signal: AD0 */
    07656 #define PIO_PA18X1_AD1       (1u << 18)  /**< \brief Adc signal: AD1 */
    07657 #define PIO_PC13X1_AD10      (1u << 13)  /**< \brief Adc signal: AD10 */
    07658 #define PIO_PC15X1_AD11      (1u << 15)  /**< \brief Adc signal: AD11 */
    07659 #define PIO_PC12X1_AD12      (1u << 12)  /**< \brief Adc signal: AD12 */
    07660 #define PIO_PC29X1_AD13      (1u << 29)  /**< \brief Adc signal: AD13 */
    07661 #define PIO_PC30X1_AD14      (1u << 30)  /**< \brief Adc signal: AD14 */
    07662 #define PIO_PA19X1_AD2_WKUP9 (1u << 19)  /**< \brief Adc signal: AD2/WKUP9 */
    07663 #define PIO_PA20X1_AD3_WKUP10 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
    07664 #define PIO_PB0X1_AD4_RTCOUT0 (1u << 0)  /**< \brief Adc signal: AD4/RTCOUT0 */
    07665 #define PIO_PB1X1_AD5_RTCOUT1 (1u << 1)  /**< \brief Adc signal: AD5/RTCOUT1 */
    07666 #define PIO_PB2X1_AD6_WKUP12 (1u << 2)   /**< \brief Adc signal: AD6/WKUP12 */
    07667 #define PIO_PB3X1_AD7        (1u << 3)   /**< \brief Adc signal: AD7 */
    07668 #define PIO_PA21X1_AD8       (1u << 21)  /**< \brief Adc signal: AD8 */
    07669 #define PIO_PA22X1_AD9       (1u << 22)  /**< \brief Adc signal: AD9 */
    07670 #define PIO_PA8B_ADTRG       (1u << 8)   /**< \brief Adc signal: ADTRG */
    07671 /* ========== Pio definition for DACC peripheral ========== */
    07672 #define PIO_PB13X1_DAC0      (1u << 13)  /**< \brief Dacc signal: DAC0 */
    07673 #define PIO_PB14X1_DAC1      (1u << 14)  /**< \brief Dacc signal: DAC1 */
    07674 #define PIO_PA2C_DATRG       (1u << 2)   /**< \brief Dacc signal: DATRG */
    07675 /* ========== Pio definition for EBI peripheral ========== */
    07676 #define PIO_PC18A_A0         (1u << 18)  /**< \brief Ebi signal: A0 */
    07677 #define PIO_PC19A_A1         (1u << 19)  /**< \brief Ebi signal: A1 */
    07678 #define PIO_PC28A_A10        (1u << 28)  /**< \brief Ebi signal: A10 */
    07679 #define PIO_PC29A_A11        (1u << 29)  /**< \brief Ebi signal: A11 */
    07680 #define PIO_PC30A_A12        (1u << 30)  /**< \brief Ebi signal: A12 */
    07681 #define PIO_PC31A_A13        (1u << 31)  /**< \brief Ebi signal: A13 */
    07682 #define PIO_PA18C_A14        (1u << 18)  /**< \brief Ebi signal: A14 */
    07683 #define PIO_PA19C_A15        (1u << 19)  /**< \brief Ebi signal: A15 */
    07684 #define PIO_PA20C_A16        (1u << 20)  /**< \brief Ebi signal: A16 */
    07685 #define PIO_PA0C_A17         (1u << 0)   /**< \brief Ebi signal: A17 */
    07686 #define PIO_PA1C_A18         (1u << 1)   /**< \brief Ebi signal: A18 */
    07687 #define PIO_PA23C_A19        (1u << 23)  /**< \brief Ebi signal: A19 */
    07688 #define PIO_PC20A_A2         (1u << 20)  /**< \brief Ebi signal: A2 */
    07689 #define PIO_PA24C_A20        (1u << 24)  /**< \brief Ebi signal: A20 */
    07690 #define PIO_PC16A_A21_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */
    07691 #define PIO_PC17A_A22_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */
    07692 #define PIO_PA25C_A23        (1u << 25)  /**< \brief Ebi signal: A23 */
    07693 #define PIO_PC21A_A3         (1u << 21)  /**< \brief Ebi signal: A3 */
    07694 #define PIO_PC22A_A4         (1u << 22)  /**< \brief Ebi signal: A4 */
    07695 #define PIO_PC23A_A5         (1u << 23)  /**< \brief Ebi signal: A5 */
    07696 #define PIO_PC24A_A6         (1u << 24)  /**< \brief Ebi signal: A6 */
    07697 #define PIO_PC25A_A7         (1u << 25)  /**< \brief Ebi signal: A7 */
    07698 #define PIO_PC26A_A8         (1u << 26)  /**< \brief Ebi signal: A8 */
    07699 #define PIO_PC27A_A9         (1u << 27)  /**< \brief Ebi signal: A9 */
    07700 #define PIO_PC0A_D0          (1u << 0)   /**< \brief Ebi signal: D0 */
    07701 #define PIO_PC1A_D1          (1u << 1)   /**< \brief Ebi signal: D1 */
    07702 #define PIO_PC2A_D2          (1u << 2)   /**< \brief Ebi signal: D2 */
    07703 #define PIO_PC3A_D3          (1u << 3)   /**< \brief Ebi signal: D3 */
    07704 #define PIO_PC4A_D4          (1u << 4)   /**< \brief Ebi signal: D4 */
    07705 #define PIO_PC5A_D5          (1u << 5)   /**< \brief Ebi signal: D5 */
    07706 #define PIO_PC6A_D6          (1u << 6)   /**< \brief Ebi signal: D6 */
    07707 #define PIO_PC7A_D7          (1u << 7)   /**< \brief Ebi signal: D7 */
    07708 #define PIO_PC9A_NANDOE      (1u << 9)   /**< \brief Ebi signal: NANDOE */
    07709 #define PIO_PC10A_NANDWE     (1u << 10)  /**< \brief Ebi signal: NANDWE */
    07710 #define PIO_PC14A_NCS0       (1u << 14)  /**< \brief Ebi signal: NCS0 */
    07711 #define PIO_PC15A_NCS1       (1u << 15)  /**< \brief Ebi signal: NCS1 */
    07712 #define PIO_PA22C_NCS2       (1u << 22)  /**< \brief Ebi signal: NCS2 */
    07713 #define PIO_PC12A_NCS3       (1u << 12)  /**< \brief Ebi signal: NCS3 */
    07714 #define PIO_PC11A_NRD        (1u << 11)  /**< \brief Ebi signal: NRD */
    07715 #define PIO_PC13A_NWAIT      (1u << 13)  /**< \brief Ebi signal: NWAIT */
    07716 #define PIO_PC8A_NWE         (1u << 8)   /**< \brief Ebi signal: NWE */
    07717 /* ========== Pio definition for HSMCI peripheral ========== */
    07718 #define PIO_PA28C_MCCDA      (1u << 28)  /**< \brief Hsmci signal: MCCDA */
    07719 #define PIO_PA29C_MCCK       (1u << 29)  /**< \brief Hsmci signal: MCCK */
    07720 #define PIO_PA30C_MCDA0      (1u << 30)  /**< \brief Hsmci signal: MCDA0 */
    07721 #define PIO_PA31C_MCDA1      (1u << 31)  /**< \brief Hsmci signal: MCDA1 */
    07722 #define PIO_PA26C_MCDA2      (1u << 26)  /**< \brief Hsmci signal: MCDA2 */
    07723 #define PIO_PA27C_MCDA3      (1u << 27)  /**< \brief Hsmci signal: MCDA3 */
    07724 /* ========== Pio definition for PIOA peripheral ========== */
    07725 #define PIO_PA24D_PIODC0     (1u << 24)  /**< \brief Pioa signal: PIODC0 */
    07726 #define PIO_PA25D_PIODC1     (1u << 25)  /**< \brief Pioa signal: PIODC1 */
    07727 #define PIO_PA26D_PIODC2     (1u << 26)  /**< \brief Pioa signal: PIODC2 */
    07728 #define PIO_PA27D_PIODC3     (1u << 27)  /**< \brief Pioa signal: PIODC3 */
    07729 #define PIO_PA28D_PIODC4     (1u << 28)  /**< \brief Pioa signal: PIODC4 */
    07730 #define PIO_PA29D_PIODC5     (1u << 29)  /**< \brief Pioa signal: PIODC5 */
    07731 #define PIO_PA30D_PIODC6     (1u << 30)  /**< \brief Pioa signal: PIODC6 */
    07732 #define PIO_PA31D_PIODC7     (1u << 31)  /**< \brief Pioa signal: PIODC7 */
    07733 #define PIO_PA23D_PIODCCLK   (1u << 23)  /**< \brief Pioa signal: PIODCCLK */
    07734 #define PIO_PA15D_PIODCEN1   (1u << 15)  /**< \brief Pioa signal: PIODCEN1 */
    07735 #define PIO_PA16D_PIODCEN2   (1u << 16)  /**< \brief Pioa signal: PIODCEN2 */
    07736 /* ========== Pio definition for PMC peripheral ========== */
    07737 #define PIO_PA6B_PCK0        (1u << 6)   /**< \brief Pmc signal: PCK0 */
    07738 #define PIO_PB13B_PCK0       (1u << 13)  /**< \brief Pmc signal: PCK0 */
    07739 #define PIO_PA17B_PCK1       (1u << 17)  /**< \brief Pmc signal: PCK1 */
    07740 #define PIO_PA21B_PCK1       (1u << 21)  /**< \brief Pmc signal: PCK1 */
    07741 #define PIO_PA18B_PCK2       (1u << 18)  /**< \brief Pmc signal: PCK2 */
    07742 #define PIO_PA31B_PCK2       (1u << 31)  /**< \brief Pmc signal: PCK2 */
    07743 #define PIO_PB3B_PCK2        (1u << 3)   /**< \brief Pmc signal: PCK2 */
    07744 /* ========== Pio definition for PWM peripheral ========== */
    07745 #define PIO_PA9C_PWMFI0      (1u << 9)   /**< \brief Pwm signal: PWMFI0 */
    07746 #define PIO_PA0A_PWMH0       (1u << 0)   /**< \brief Pwm signal: PWMH0 */
    07747 #define PIO_PA11B_PWMH0      (1u << 11)  /**< \brief Pwm signal: PWMH0 */
    07748 #define PIO_PA23B_PWMH0      (1u << 23)  /**< \brief Pwm signal: PWMH0 */
    07749 #define PIO_PB0A_PWMH0       (1u << 0)   /**< \brief Pwm signal: PWMH0 */
    07750 #define PIO_PC18B_PWMH0      (1u << 18)  /**< \brief Pwm signal: PWMH0 */
    07751 #define PIO_PA1A_PWMH1       (1u << 1)   /**< \brief Pwm signal: PWMH1 */
    07752 #define PIO_PA12B_PWMH1      (1u << 12)  /**< \brief Pwm signal: PWMH1 */
    07753 #define PIO_PA24B_PWMH1      (1u << 24)  /**< \brief Pwm signal: PWMH1 */
    07754 #define PIO_PB1A_PWMH1       (1u << 1)   /**< \brief Pwm signal: PWMH1 */
    07755 #define PIO_PC19B_PWMH1      (1u << 19)  /**< \brief Pwm signal: PWMH1 */
    07756 #define PIO_PA2A_PWMH2       (1u << 2)   /**< \brief Pwm signal: PWMH2 */
    07757 #define PIO_PA13B_PWMH2      (1u << 13)  /**< \brief Pwm signal: PWMH2 */
    07758 #define PIO_PA25B_PWMH2      (1u << 25)  /**< \brief Pwm signal: PWMH2 */
    07759 #define PIO_PB4B_PWMH2       (1u << 4)   /**< \brief Pwm signal: PWMH2 */
    07760 #define PIO_PC20B_PWMH2      (1u << 20)  /**< \brief Pwm signal: PWMH2 */
    07761 #define PIO_PA7B_PWMH3       (1u << 7)   /**< \brief Pwm signal: PWMH3 */
    07762 #define PIO_PA14B_PWMH3      (1u << 14)  /**< \brief Pwm signal: PWMH3 */
    07763 #define PIO_PA17C_PWMH3      (1u << 17)  /**< \brief Pwm signal: PWMH3 */
    07764 #define PIO_PB14B_PWMH3      (1u << 14)  /**< \brief Pwm signal: PWMH3 */
    07765 #define PIO_PC21B_PWMH3      (1u << 21)  /**< \brief Pwm signal: PWMH3 */
    07766 #define PIO_PA19B_PWML0      (1u << 19)  /**< \brief Pwm signal: PWML0 */
    07767 #define PIO_PB5B_PWML0       (1u << 5)   /**< \brief Pwm signal: PWML0 */
    07768 #define PIO_PC0B_PWML0       (1u << 0)   /**< \brief Pwm signal: PWML0 */
    07769 #define PIO_PC13B_PWML0      (1u << 13)  /**< \brief Pwm signal: PWML0 */
    07770 #define PIO_PA20B_PWML1      (1u << 20)  /**< \brief Pwm signal: PWML1 */
    07771 #define PIO_PB12A_PWML1      (1u << 12)  /**< \brief Pwm signal: PWML1 */
    07772 #define PIO_PC1B_PWML1       (1u << 1)   /**< \brief Pwm signal: PWML1 */
    07773 #define PIO_PC15B_PWML1      (1u << 15)  /**< \brief Pwm signal: PWML1 */
    07774 #define PIO_PA16C_PWML2      (1u << 16)  /**< \brief Pwm signal: PWML2 */
    07775 #define PIO_PA30A_PWML2      (1u << 30)  /**< \brief Pwm signal: PWML2 */
    07776 #define PIO_PB13A_PWML2      (1u << 13)  /**< \brief Pwm signal: PWML2 */
    07777 #define PIO_PC2B_PWML2       (1u << 2)   /**< \brief Pwm signal: PWML2 */
    07778 #define PIO_PA15C_PWML3      (1u << 15)  /**< \brief Pwm signal: PWML3 */
    07779 #define PIO_PC3B_PWML3       (1u << 3)   /**< \brief Pwm signal: PWML3 */
    07780 #define PIO_PC22B_PWML3      (1u << 22)  /**< \brief Pwm signal: PWML3 */
    07781 /* ========== Pio definition for SPI peripheral ========== */
    07782 #define PIO_PA12A_MISO       (1u << 12)  /**< \brief Spi signal: MISO */
    07783 #define PIO_PA13A_MOSI       (1u << 13)  /**< \brief Spi signal: MOSI */
    07784 #define PIO_PA11A_NPCS0      (1u << 11)  /**< \brief Spi signal: NPCS0 */
    07785 #define PIO_PA9B_NPCS1       (1u << 9)   /**< \brief Spi signal: NPCS1 */
    07786 #define PIO_PA31A_NPCS1      (1u << 31)  /**< \brief Spi signal: NPCS1 */
    07787 #define PIO_PB14A_NPCS1      (1u << 14)  /**< \brief Spi signal: NPCS1 */
    07788 #define PIO_PC4B_NPCS1       (1u << 4)   /**< \brief Spi signal: NPCS1 */
    07789 #define PIO_PA10B_NPCS2      (1u << 10)  /**< \brief Spi signal: NPCS2 */
    07790 #define PIO_PA30B_NPCS2      (1u << 30)  /**< \brief Spi signal: NPCS2 */
    07791 #define PIO_PB2B_NPCS2       (1u << 2)   /**< \brief Spi signal: NPCS2 */
    07792 #define PIO_PA3B_NPCS3       (1u << 3)   /**< \brief Spi signal: NPCS3 */
    07793 #define PIO_PA5B_NPCS3       (1u << 5)   /**< \brief Spi signal: NPCS3 */
    07794 #define PIO_PA22B_NPCS3      (1u << 22)  /**< \brief Spi signal: NPCS3 */
    07795 #define PIO_PA14A_SPCK       (1u << 14)  /**< \brief Spi signal: SPCK */
    07796 /* ========== Pio definition for SSC peripheral ========== */
    07797 #define PIO_PA18A_RD         (1u << 18)  /**< \brief Ssc signal: RD */
    07798 #define PIO_PA20A_RF         (1u << 20)  /**< \brief Ssc signal: RF */
    07799 #define PIO_PA19A_RK         (1u << 19)  /**< \brief Ssc signal: RK */
    07800 #define PIO_PA17A_TD         (1u << 17)  /**< \brief Ssc signal: TD */
    07801 #define PIO_PA15A_TF         (1u << 15)  /**< \brief Ssc signal: TF */
    07802 #define PIO_PA16A_TK         (1u << 16)  /**< \brief Ssc signal: TK */
    07803 /* ========== Pio definition for TC0 peripheral ========== */
    07804 #define PIO_PA4B_TCLK0       (1u << 4)   /**< \brief Tc0 signal: TCLK0 */
    07805 #define PIO_PA28B_TCLK1      (1u << 28)  /**< \brief Tc0 signal: TCLK1 */
    07806 #define PIO_PA29B_TCLK2      (1u << 29)  /**< \brief Tc0 signal: TCLK2 */
    07807 #define PIO_PA0B_TIOA0       (1u << 0)   /**< \brief Tc0 signal: TIOA0 */
    07808 #define PIO_PA15B_TIOA1      (1u << 15)  /**< \brief Tc0 signal: TIOA1 */
    07809 #define PIO_PA26B_TIOA2      (1u << 26)  /**< \brief Tc0 signal: TIOA2 */
    07810 #define PIO_PA1B_TIOB0       (1u << 1)   /**< \brief Tc0 signal: TIOB0 */
    07811 #define PIO_PA16B_TIOB1      (1u << 16)  /**< \brief Tc0 signal: TIOB1 */
    07812 #define PIO_PA27B_TIOB2      (1u << 27)  /**< \brief Tc0 signal: TIOB2 */
    07813 /* ========== Pio definition for TC1 peripheral ========== */
    07814 #define PIO_PC25B_TCLK3      (1u << 25)  /**< \brief Tc1 signal: TCLK3 */
    07815 #define PIO_PC28B_TCLK4      (1u << 28)  /**< \brief Tc1 signal: TCLK4 */
    07816 #define PIO_PC31B_TCLK5      (1u << 31)  /**< \brief Tc1 signal: TCLK5 */
    07817 #define PIO_PC23B_TIOA3      (1u << 23)  /**< \brief Tc1 signal: TIOA3 */
    07818 #define PIO_PC26B_TIOA4      (1u << 26)  /**< \brief Tc1 signal: TIOA4 */
    07819 #define PIO_PC29B_TIOA5      (1u << 29)  /**< \brief Tc1 signal: TIOA5 */
    07820 #define PIO_PC24B_TIOB3      (1u << 24)  /**< \brief Tc1 signal: TIOB3 */
    07821 #define PIO_PC27B_TIOB4      (1u << 27)  /**< \brief Tc1 signal: TIOB4 */
    07822 #define PIO_PC30B_TIOB5      (1u << 30)  /**< \brief Tc1 signal: TIOB5 */
    07823 /* ========== Pio definition for TWI0 peripheral ========== */
    07824 #define PIO_PA4A_TWCK0       (1u << 4)   /**< \brief Twi0 signal: TWCK0 */
    07825 #define PIO_PA3A_TWD0        (1u << 3)   /**< \brief Twi0 signal: TWD0 */
    07826 /* ========== Pio definition for TWI1 peripheral ========== */
    07827 #define PIO_PB5A_TWCK1       (1u << 5)   /**< \brief Twi1 signal: TWCK1 */
    07828 #define PIO_PB4A_TWD1        (1u << 4)   /**< \brief Twi1 signal: TWD1 */
    07829 /* ========== Pio definition for UART0 peripheral ========== */
    07830 #define PIO_PA9A_URXD0       (1u << 9)   /**< \brief Uart0 signal: URXD0 */
    07831 #define PIO_PA10A_UTXD0      (1u << 10)  /**< \brief Uart0 signal: UTXD0 */
    07832 /* ========== Pio definition for UART1 peripheral ========== */
    07833 #define PIO_PB2A_URXD1       (1u << 2)   /**< \brief Uart1 signal: URXD1 */
    07834 #define PIO_PB3A_UTXD1       (1u << 3)   /**< \brief Uart1 signal: UTXD1 */
    07835 /* ========== Pio definition for USART0 peripheral ========== */
    07836 #define PIO_PA8A_CTS0        (1u << 8)   /**< \brief Usart0 signal: CTS0 */
    07837 #define PIO_PA7A_RTS0        (1u << 7)   /**< \brief Usart0 signal: RTS0 */
    07838 #define PIO_PA5A_RXD0        (1u << 5)   /**< \brief Usart0 signal: RXD0 */
    07839 #define PIO_PA2B_SCK0        (1u << 2)   /**< \brief Usart0 signal: SCK0 */
    07840 #define PIO_PA6A_TXD0        (1u << 6)   /**< \brief Usart0 signal: TXD0 */
    07841 /* ========== Pio definition for USART1 peripheral ========== */
    07842 #define PIO_PA25A_CTS1       (1u << 25)  /**< \brief Usart1 signal: CTS1 */
    07843 #define PIO_PA26A_DCD1       (1u << 26)  /**< \brief Usart1 signal: DCD1 */
    07844 #define PIO_PA28A_DSR1       (1u << 28)  /**< \brief Usart1 signal: DSR1 */
    07845 #define PIO_PA27A_DTR1       (1u << 27)  /**< \brief Usart1 signal: DTR1 */
    07846 #define PIO_PA29A_RI1        (1u << 29)  /**< \brief Usart1 signal: RI1 */
    07847 #define PIO_PA24A_RTS1       (1u << 24)  /**< \brief Usart1 signal: RTS1 */
    07848 #define PIO_PA21A_RXD1       (1u << 21)  /**< \brief Usart1 signal: RXD1 */
    07849 #define PIO_PA23A_SCK1       (1u << 23)  /**< \brief Usart1 signal: SCK1 */
    07850 #define PIO_PA22A_TXD1       (1u << 22)  /**< \brief Usart1 signal: TXD1 */
    07851 /* ========== Pio definition for USART2 peripheral ========== */
    07852 #define PIO_PC17B_CTS2       (1u << 17)  /**< \brief Usart2 signal: CTS2 */
    07853 #define PIO_PC16B_RTS2       (1u << 16)  /**< \brief Usart2 signal: RTS2 */
    07854 #define PIO_PC9B_RXD2        (1u << 9)   /**< \brief Usart2 signal: RXD2 */
    07855 #define PIO_PC14B_SCK2       (1u << 14)  /**< \brief Usart2 signal: SCK2 */
    07856 #define PIO_PC10B_TXD2       (1u << 10)  /**< \brief Usart2 signal: TXD2 */
    07857 /*@}*/
    07858
    07859 /* ************************************************************************** */
    07860 /*   MEMORY MAPPING DEFINITIONS FOR SAM3S8 */
    07861 /* ************************************************************************** */
    07862
    07863 #define IFLASH_ADDR  (0x00400000u) /**< Internal Flash base address */
    07864 #define IFLASH0_ADDR (0x00400000u) /**< Internal Flash 0 base address */
    07865 #define IFLASH1_ADDR (0x00440000u) /**< Internal Flash 1 base address */
    07866 #define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
    07867 #define IRAM_ADDR    (0x20000000u) /**< Internal RAM base address */
    07868 #define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
    07869 #define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
    07870 #define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
    07871 #define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
    07872
    07873 #if defined sam3sd8
    07874   #define IFLASH0_SIZE             0x40000
    07875   #define IFLASH0_PAGE_SIZE        256
    07876   #define IFLASH0_LOCK_REGION_SIZE 32768
    07877   #define IFLASH0_NB_OF_PAGES      1024
    07878   #define IFLASH0_NB_OF_LOCK_BITS  8
    07879   #define IFLASH1_SIZE             0x40000
    07880   #define IFLASH1_PAGE_SIZE        256
    07881   #define IFLASH1_LOCK_REGION_SIZE 32768
    07882   #define IFLASH1_NB_OF_PAGES      1024
    07883   #define IFLASH1_NB_OF_LOCK_BITS  8
    07884   #define IRAM_SIZE                0x10000
    07885   #define IFLASH_SIZE              0x80000
    07886 #elif defined sam3s8
    07887   #define IFLASH_SIZE             0x80000
    07888   #define IFLASH_PAGE_SIZE        256
    07889   #define IFLASH_LOCK_REGION_SIZE 32768
    07890   #define IFLASH_NB_OF_PAGES      2048
    07891   #define IFLASH_NB_OF_LOCK_BITS  16
    07892   #define IRAM_SIZE               0x10000
    07893 #else
    07894   #error Library does not support the specified device.
    07895 #endif
    07896
    07897 #ifdef __cplusplus
    07898 }
    07899 #endif
    07900
    07901 /*@}*/
    07902
    07903 #endif /* SAM3S8_H */

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